JPH09199997A - Afc circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an AFC circuit correcting the detuned frequency for a reception signal in a receiver receiving a digital broadcast program. SOLUTION: Frequency detuning data Δf being an output of an analog detection section 101 are obtained from an output of a digital demodulation section 100. A reference signal generating section 29 generates a reference frequency signal with a frequency (f) based on the frequency detuning data Δf. Since a feedback to satisfy a relation of the reference frequency signal f=(fo+Δf)/N is applied to the entire system by applying the reference frequency signal whose frequency is (f) to a PLL circuit 11 as a reference phase comparison signal, the detuned frequency is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AFC (automatic frequency adjustment) for correcting frequency detuning of a received signal caused by either a transmitting side or receiving side channel selecting device in a receiver for receiving digital broadcasting, for example. Control) circuit.

[0002]

2. Description of the Related Art As a conventional AFC circuit for digital broadcasting, a QPSK demodulation system for satellite broadcasting will be described as an example. FIG. 3 is an example in which the AFC is configured by a digital circuit.

The second intermediate frequency (2ndIF) signal supplied from the input terminal 1 is supplied as one input of the multipliers 2 and 3, respectively. The regenerated carrier generated by the voltage controlled oscillator (VCO) 5 passes through the 90 ° phase shifter 4 and the other input of the multiplier 3 is 9 times the other input of the multiplier 2.
The signals are supplied so as to have a phase delay of 0 °, and the quadrature detection outputs I and Q are obtained from the respective multiplication outputs.

Here, the reproduction carrier output of the VCO 5 is
The signal is supplied to the multiplier 9 of the PLL circuit 11 including the multiplier 9 and the filter 10 via the frequency divider 6 set to 1 / N of an arbitrary frequency division ratio. Further, the output of the PLL circuit 11
A loop is configured to feed back to the VCO 5 as a frequency control voltage. Here, in the PLL circuit 11, the phase noise of the reproduction carrier is reduced by using the reference phase signal source with good phase accuracy.

The I and Q outputs are converted into digital signals by A / D converters 17 and 18, and the digital AFC circuit 1
9. The digital AFC circuit 19 uses the AFC control signal corresponding to the frequency detuning amount of the quadrature detection signal,
Frequency detuning can be removed and output. The digital quadrature detection output from which the frequency detuning has been removed is supplied to the roll-off filters 20 and 21, and after being filtered at a prescribed roll-off rate, the demodulation circuit 2 composed of a complex multiplier or the like.
2 to output QPSK demodulation data for each of I-axis and Q-axis.

Here, the demodulated data is supplied to the frequency detuning detection circuit 25, and the frequency detuning of the QPSK detection output is detected by detecting the bit change and the phase change per unit time. By supplying this frequency detuning detection output to the digital AFC circuit 19, the system operates so that the AFC loop control in the direction of eliminating the frequency detuning is applied, and the frequency detuning component of the digital quadrature detection output can be removed. it can.

On the other hand, an inexpensive digital QPSK demodulator may use a roll-off filter by an analog circuit. In that case, as shown in FIG. 4, frequency detuning is removed using AFC (analog AFC) in which an analog quadrature detection unit is included in the loop. The configuration of the analog AFC circuit will be described below. However, the same functional blocks as those of the digital AFC are designated by the same reference numerals, and detailed description thereof will be omitted.

2ndIF is applied to one input of the multipliers 2 and 3.
Similar to the digital AFC, the signals are supplied to the other inputs with reproduction carriers having a phase difference of 90 °, and the quadrature detection outputs I and Q are obtained from the respective multiplication outputs.
Here, the oscillation frequency of the VCO 5 is varied by the DC control voltage corresponding to the frequency detuning amount of the quadrature detection signal, whereby the reproduction carrier frequency is corrected and the frequency detuning of the quadrature detection output is removed.

After passing through the analog roll-off filters 50 and 51, the I and Q outputs are converted into digital signals by the A / D converters 17 and 18. The digital quadrature detection signal is output to the demodulation circuit 22 formed of a complex multiplier or the like, and I-axis and Q-axis QPSK demodulation data can be obtained as a complex multiplication output.

Here, the demodulated data is supplied to the frequency detuning detection circuit 25, and the frequency detuning of the QPSK detection output can be detected in the same manner as described above. This frequency detuning detection output is supplied to the D / A circuit 26 and converted into an analog DC voltage (AFC control voltage). By supplying this to the VCO 5, the oscillation frequency of the VCO 5 changes so as to eliminate frequency detuning, and an AFC loop is configured to remove the frequency detuning amount of the analog quadrature detection output.

The reason for applying automatic frequency control (AFC) in a QPSK demodulation system or the like is to remove frequency detuning at the input end of the roll-off filter. That is, when AFC using a digital circuit is used, the roll-off filter also needs to be arranged in the AFC loop as a digital filter. However, when a roll-off filter composed of a digital circuit is built in a digital IC for demodulation or the like, the cost of the chip or package is increased due to an increase in the number of elements or power consumption, and when the expected transmission rate is increased in the future, However, conversion to a digital amount requires a higher sampling clock, which is disadvantageous in terms of power consumption.

On the other hand, in the demodulation system having the analog AFC structure, since the roll-off filter may be either analog or digital, generally an inexpensive analog filter is often used. In this case, VCO5 for reproducing carrier generation
Is controlled by the AFC control voltage, a PLL that is a separate loop cannot be configured, and good phase noise characteristics are required for the oscillator used for the VCO 5 alone. At that time, by using discrete parts with excellent device characteristics, VC
It is considered possible to satisfy the desired phase noise characteristic by configuring O5. However, when the VCO 5 is built in the analog IC together with the quadrature detection circuit,
It is very difficult to obtain a satisfactory phase noise characteristic unless the process performance used for IC is dramatically improved.

[0013]

As described above, in the conventional AFC circuit, both the AF of the digital AFC system and the analog AFC system used in digital broadcasting are used.
Both the C method and the C method have problems in terms of cost and characteristics such as phase noise.

The present invention is an AFC that corrects frequency detuning of a received signal in a receiver that receives digital broadcasting.
Provide a circuit.

[0015]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention is directed to an AFC circuit for correcting frequency detuning of an intermediate frequency signal of a received digital broadcast, wherein the intermediate frequency signal is converted into an arbitrary digital demodulation system. Detecting means for frequency conversion corresponding to the above, a phase synchronization control means of an oscillator for generating a reproduction carrier for detection of the detection means, and the phase synchronization control according to the frequency detuning of the detection output obtained by the detection means. It is characterized in that it is configured to control the means.

With such a configuration, the phase synchronization control means of the oscillator for generating the reproduction carrier for detection is controlled based on the frequency detuning of the detection output obtained by the detection means, thereby receiving the digital broadcast. The frequency detuning of the intermediate frequency signal can be corrected, and a satisfactory phase noise characteristic of the detection carrier for detection can be obtained.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram for explaining an embodiment of the present invention. In this embodiment, the same components as those in FIG. 3 are designated by the same reference numerals, and different portions will be mainly described here.

In FIG. 1, the second intermediate frequency (2ndIF) signal supplied from the input terminal 1 is supplied as one input of each of the multipliers 2 and 3. The reproduction carrier generated by the voltage controlled oscillator (VCO) 5 is 90 °
The other input of the multiplier 2 is supplied to the other input of the multiplier 2 through the phase shifter 4 so that the other input of the multiplier 3 has a phase delay of 90 °, and the quadrature detection outputs I and Q are output from the respective multiplication outputs. obtain.

Here, the reproduction carrier output of the VCO 5 is
It is supplied to a PLL circuit 11 including a phase comparator 9 and a loop filter 10 via a frequency divider 6 set to an arbitrary frequency division ratio of 1 / N, and the output of the PLL circuit 11 is supplied to a VCO 5 as a frequency control voltage. Configure a loop that returns.

The I and Q outputs are the roll-off filter 50,
It is supplied to the A / D converters 17 and 18 via 51 and converted into digital signals there. The digital detection output is supplied to the demodulator 22 composed of a complex multiplier or the like, and the operation output becomes each QPSK demodulation data of the I axis and the Q axis.

The I and Q demodulated data are supplied to the frequency detuning detection circuit 25, respectively, and by detecting bit changes and phase changes per unit time of the demodulated data,
Frequency detuning (Δf) data of the QPSK detection output can be obtained. The reference signal generation unit 29 generates a reference frequency signal having a frequency f based on the frequency detuning data.
If this is supplied as the reference phase comparison signal of the PLL circuit 11, f will satisfy f = (fo + Δf) / N, where fo is the oscillation frequency of the VCO 5 and N is the frequency division ratio of the frequency divider 6. QPS, because a large amount of feedback is applied to the entire system
The frequency detuning of the K detection output can be eliminated. Further, by generating a reference signal with good phase accuracy in the reference signal generator 29, the PLL circuit 11 can reduce the phase noise of the reproduction carrier, which is the oscillation output of the VCO 5.

A plurality of methods can be used as means for generating a reference signal with good phase accuracy in the reference signal generator 29. For example, by using a counter that inputs the main clock or sampling clock for the QPSK digital demodulation unit or A / D converter and resets itself at the timing according to the detection result of the frequency detuning detection circuit 25, A reference signal with a period can be obtained. Generally, the clock is obtained from an oscillator that uses a crystal oscillator or other oscillator with excellent stability, so the reference signals generated from these clocks have good phase accuracy and can provide a regenerated carrier with excellent phase stability. .

In this embodiment, even when the AFC is configured on the digital demodulation side, the PLL reference comparison signal is generated by the digital demodulation section 101, and the analog detection section 100 is generated.
However, this can be solved by the following means.

A second input terminal 13 is provided separately from the phase comparison reference signal input terminal 14 for the PLL circuit 11, and the terminal 14 is connected to the input terminal 13 via an amplifier 31. When the digital demodulation side does not have the AFC function, the phase comparison reference signal may be input from the input terminal 14 to control the oscillation frequency of the VCO 5 as described above. On the other hand, when the digital demodulation side has an AFC function, a vibrator is inserted between the input end 14 and the second input end 13 so as to operate together with the amplifier 31 as an oscillator. Also in this configuration, the phase noise of the VCO 5 can be suppressed by using a crystal oscillator or the like having excellent phase stability.

With the above-mentioned configuration, when the analog detection unit 100 is integrated as an analog IC, it can be dealt with regardless of whether the digital demodulation unit 101 is equipped with AFC. Therefore, since the analog type roll-off filter can be adopted, the circuit can be easily integrated, and as a result, the demodulator for digital broadcasting can be constructed at low cost.

FIG. 2 is a block diagram for explaining another embodiment of the present invention. In this embodiment, the detection data of the frequency detuning detection circuit 25 is converted to the D / A converter 32.
1 is different from the embodiment shown in FIG. 1 in that the constituent portion for converting into an analog amount control voltage ΔV and the like and feeding back to the analog detection unit 100.

The VCO5 output for carrier reproduction is divided by 1
The signal is supplied to the PLL circuit 11 including the phase comparator 9 and the loop filter 10 via the / N frequency divider 6. PLL
When the reference phase comparison signal of the circuit 11 is generated by the oscillator 12 that uses the oscillator X having excellent phase stability such as a crystal oscillator, the control voltage ΔVo that suppresses the phase noise of the VCO 5 from the PLL circuit 10 is generated. obtain. Control voltage ΔV and ΔVo
Is added by the adder 35 and is used as the control voltage of the VCO 5, it is possible to apply control (AFC and PLL) to the VCO 5 so as to suppress frequency detuning and phase noise. Here, the control voltages ΔV and ΔVo are appropriately matched in gain and sign according to the control sensitivity of the VCO 5 and the direction (sign) of control, or a process equivalent to this (addition amount offset). Is added, the sign is reversed, etc.).

In this embodiment, it is not necessary to configure the reference signal generator 29 of the embodiment of FIG. 1 with a QPSK digital demodulator, which is advantageous in terms of scale when integrated as a digital LSI. . Further, since the loop gains of the PLL and the AFC can be set individually and without correlation, they can be easily applied to various characteristics required for each demodulation system such as phase noise.

[0029]

As described above, the AFC of the present invention
According to the circuit, it is possible to suppress the frequency detuning of the detection output without degrading the phase accuracy of the reproduction carrier for detection in the digital demodulation with the element having the element characteristics that can be integrated.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention.

FIG. 2 is a block diagram for explaining another embodiment of the present invention.

FIG. 3 is a block diagram of an AFC circuit using a digital circuit used as a conventional AFC circuit for digital broadcasting.

FIG. 4 is a blog diagram of a conventional AFC circuit in which frequency detuning is removed by using analog AFC.

[Explanation of symbols]

2, 3 ... Multiplier, 4 ... 90 ° phase shifter, 5 ... VCO, 6 ...
Frequency divider, 11 ... PLL circuit, 12 ... Oscillator, 17, 18
... A / D converter, 22 ... Demodulator, 25 ... Frequency detuning detection circuit, 29 ... Reference signal generating section, 31 ... Amplifier, 32 ... D
/ A converter, 35 ... Adder, 50, 51 ... Roll-off filter, 100 ... Analog detector, 101 ... Digital demodulator.

Claims (13)

[Claims] 1. An AFC circuit for correcting frequency detuning of an intermediate frequency signal of a received digital broadcast, a detector for converting the frequency of the intermediate frequency signal in accordance with an arbitrary digital demodulation system, and a detector of the detector. Phase synchronization control means of an oscillator for generating a reproduction carrier for digital broadcasting, and the phase synchronization control means for controlling the phase synchronization control means according to the frequency detuning of the detection output obtained by the detection means. circuit. 2. The phase synchronization control means comprises a reference phase comparison signal, one input of which is a continuous wave signal whose frequency changes in response to frequency detuning from a desired frequency of the detection output, and the other input. Is composed of a phase comparison means which is a frequency division output obtained by dividing the oscillator output by an arbitrary frequency division ratio, and a low pass filter which receives the output of the phase comparison means as an input. The AFC circuit described. 3. The phase synchronization control means, wherein one input is a reference phase comparison signal which is an arbitrary fixed frequency signal, and the other input is a frequency division output obtained by dividing the oscillator output by an arbitrary frequency division ratio. A certain phase comparison means, a low-pass filter that receives the output of the phase comparison means, one input corresponds to the output of the low-pass filter, and the other input corresponds to frequency detuning from the desired frequency of the detection output. 2. The AFC circuit according to claim 1, further comprising an adder for adding a voltage and a current whose values change and adding them with an arbitrary ratio and an arbitrary sign. 4. The detection means distributes and outputs at least two or more multiplier groups, one input of which is an intermediate frequency signal, and a reproduced carrier for detection, in an arbitrary phase relationship, and the other of the multiplier groups. 2. The phase shifter for supplying the input to the input of ## EQU1 ## and the frequency divider for dividing the reproduction carrier for detection by an arbitrary frequency division ratio and supplying the divided carrier to the phase synchronization control means. AFC circuit. 5. The continuous wave signal is provided with an input terminal for the continuous wave signal, a terminal different from the input terminal, and a second oscillator capable of oscillating by connecting a vibrator between the terminals. 3. The AFC circuit according to claim 2, wherein the second oscillator is oscillated when no signal is supplied, and the oscillation output can be selected as the phase comparison reference signal of the phase synchronization control means. 6. A continuous wave signal whose frequency changes in response to frequency detuning from a desired frequency of the detection output, wherein each filter having the detection output group as an input and each output of the filter is desired. Digital demodulation means for demodulating in accordance with the digital modulation method of at least two axes and outputting demodulated data of at least two axes, and a demodulation data output of at least two axes and a frequency of the current detection output and a desired same frequency. Is generated from frequency detuning detection means for detecting the error amount or error direction of, and offset means for increasing or decreasing the frequency according to the detection result of the detection means with respect to a certain reference frequency signal and outputting it. The AFC circuit according to claim 2. 7. The voltage, current, etc., whose value changes in accordance with frequency detuning from the desired frequency of the detection output, includes: each filter having the detection output group as an input; A digital demodulation means for demodulating in accordance with the modulation method and outputting demodulated data of at least two axes or more, and an error between the current frequency of the detection output and the desired same frequency from the demodulated data output of at least two axes or more. Frequency detuning detection means for detecting the minute or error direction, and offset means for increasing or decreasing the value according to the detection result of the detection means and outputting the voltage or current having a certain reference value. The AF according to claim 3, characterized in that
C circuit. 8. The frequency detuning detection means outputs the frequency error component as data, and the offset means increases or decreases the output data in a 1: 1 correspondence. Or the AFC circuit described in 7. 9. The frequency detuning detection means outputs the code direction in which the frequency is deviated as data, and the offset means increases or decreases an arbitrary constant value from each original value in the code direction and outputs the data. 6. The method according to claim 6 or 7, wherein
The AFC circuit described. 10. The input of the adder, wherein the time constant of the output of the phase synchronization control unit, which is one input, is set smaller than that of the other input. AFC circuit. 11. The frequency change sensitivity of the reproduction carrier for detection is increased when detuning is not detected by the frequency detuning detection means, compared with the case where detuning is detected. Or the AFC circuit described in 6. 12. The continuous wave signal includes: a counter that resets itself with an arbitrary count value using a fixed reference frequency as a clock; and a means that varies the count value that is reset by the detection result of the frequency detuning means. 7. The AFC circuit according to claim 6, wherein the counter output is generated by means for shaping the counter output into a waveform that can be used as a phase comparison reference signal of the phase synchronization control means. 13. The AFC according to claim 12, wherein an A / D sampling clock for detection output is used as a clock of a fixed reference frequency of the counter.
circuit.