JPH0410777B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronous detection receiver used in a carrier wave digital transmission system, and more particularly to a synchronous detection receiver having a function of expanding a synchronization pull-in range.

In a synchronous detection receiver used in a carrier wave digital transmission system, the synchronous pull-in range characteristic is an important parameter. This value must be at least sufficiently larger than the carrier frequency fluctuation in this system.

Conventionally, AFC (Automatic Frequency Control) has been used as a method to expand this synchronization pull-in range.
Loop) is known, and one of them is as follows. That is, a voltage controlled oscillator whose oscillation frequency changes according to a control signal, a quadrature phase detector which detects an input signal in quadrature phase using the output of the voltage controlled oscillator, and a quadrature phase detector that detects the output of the quadrature phase detector using a certain delay difference. means for calculating the output of the quadrature phase detector to obtain a phase error signal; and means for using both the frequency error signal and the phase error signal as the control signal. This is a synchronous detection receiving device configured as follows.

According to this method, a frequency error signal is obtained by multiplying one of two outputs of a quadrature phase detector with a certain delay difference.

Briefly explaining its operation, when the synchronous detection receiver is in a phase asynchronous state, the oscillation frequency of the voltage controlled oscillator is controlled by the frequency error signal so as to approach the frequency of the input signal. Thereafter, the phase synchronization circuit included in the coherent detection receiver operates, and the coherent detection receiver enters a phase synchronized state. In this state, the role of the above-mentioned frequency error signal has ended, and it is desirable that no signal is generated at its output. However, in the conventional example described above, the main signal is A signal obtained by multiplying the output obtained by detection by two is generated. The doubled signal becomes noise, and although this noise is removed to some extent by a low-pass filter, it remains and controls the voltage controlled oscillator, degrading the C/N value of the output of the voltage controlled oscillator. Become.

As described above, the conventional example has the drawback of deteriorating the output C/N of the voltage controlled oscillator.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a novel coherent detection receiving apparatus that eliminates the above-mentioned drawbacks.

In order to achieve the above object, the synchronous detection receiving device according to the present invention includes a detection means for performing quadrature phase detection on an input signal and outputting two orthogonal phase detection outputs, and a predetermined detection output for one of the detection means. a first multiplication means that multiplies the detection output of the other with a phase delay difference to obtain a frequency error signal; a second multiplication means that multiplies the two detection outputs of the detection means;
subtracting means for subtracting between the multiplication means and the second multiplication means, means for calculating a phase error signal by inputting the two detection outputs of the detection means, and an output signal of the subtraction means and the phase error signal. The apparatus includes an oscillation means that uses the error signal as a control signal and supplies an output signal whose oscillation frequency is changed by the control signal to the detection means.

Hereinafter, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, reference number 1 is a quadrature phase detection circuit, 2 is a multiplier circuit, 3 is a delay circuit, 4 and 5 are multiplication circuits, 6 is a subtraction circuit, 7 and 8 are low-pass filters,
9 indicates a voltage controlled oscillator, respectively.

Next, the operation of this embodiment will be described. Although the circuit shown in FIG. 1 can be commonly used with any modulation signal as an input signal, the case where the input signal is a 4PSK wave will be described here.

In Fig. 1, a quadrature phase detection circuit 1, a multiplier circuit 2, a low-pass filter 7, and a voltage controlled oscillator 9 are
Operates as a phase synchronization circuit for 4PSK. Here, the multiplier circuit 2 becomes a quadruple multiplier circuit.

The delay circuit 3, multiplication circuit 4, and low-pass filter 8 are circuits for creating a frequency error signal in the conventional example, and the multiplication circuit 5 and subtractor 6 are circuits added according to the present invention.

It is now assumed that this circuit is in an asynchronous state, and the difference frequency between the input signal and the output of the voltage controlled oscillator 9 at this time is ω. Here, the input signal is assumed to be unmodulated to simplify the explanation.

Since the output of the quadrature phase detector 1 is expressed as P=sinωt and Q=cosωt, the output signal of the multiplication circuit 4 that multiplies the P signal and the Q signal via the delay circuit 3 is expressed by the following equation. Here, τ is the amount of delay of the delay circuit 3.

sin(ωt+ωτ)×cos(ωt)=1/2sinωτ−1/2sin(2ωτ+ωτ) ……(1) The first term on the right side of equation (1) is the DC that responds to the difference frequency ω.
This is a frequency error signal for detecting the difference frequency ω. Since the frequency error signal is thus obtained at the output of the multiplier circuit 4, the output of the multiplier circuit 4 is input to the voltage controlled oscillator 9 via the low-pass filter 8, and is used as the control signal for the voltage controlled oscillator 9. Ba,
The loop operates so that 1/2 sinωτ becomes zero,
AFC loop is formed. Then, when the difference frequency ω becomes near zero, the phase synchronization circuit operates and enters a synchronized state. In a synchronous state, the difference frequency ω is always zero, so the AFC loop stops operating.
As described above, the AFC loop operates even without the multiplication circuit 5 and the subtraction circuit 6 in FIG. 1, but in that case, there are the following drawbacks.

In other words, although the above explanation is based on the case where the input signal is unmodulated, in reality, the input signal is
The signal is a 4PSK signal, and when considered in a synchronous state where the AFC loop is not operating, the multiplier 4 outputs a signal obtained by doubling the 4PSK demodulated signal. This signal is simply the demodulated signal multiplied by 2, and there is not enough multiplication order for 4 multiplication, which is the condition for obtaining a 4PSK phase error signal.In the end, the output signal of multiplier 4 can also be a phase error signal. However, although it is removed to some extent by the low-pass filter 8, it remains in the output of the low-pass filter 8, and the jitter contained in the reproduced carrier signal output from the voltage controlled oscillator 9 ends up being a mere noise component. This increases the number of components and further deteriorates the bit error rate characteristic representing the overall device characteristic.

In order to eliminate such drawbacks, a multiplication circuit 5 and a subtraction circuit 6 are added in FIG.

Since the outputs of the multiplier circuits 4 and 5 are obtained by multiplying the same demodulated signal by 2, if the two are subtracted in the subtraction circuit 6, the above-mentioned signals cancel each other out, and the output of the subtraction circuit 6 is It is not output to the output, and the above drawback is eliminated. In other words, only the frequency error signal can be obtained as the output of the subtraction circuit 6.

Then, as described above, when the difference frequency ω becomes close to zero, the phase locked circuit operates.

That is, the output of the quadrature phase detector 1 is multiplied by 4 by the multiplier circuit 2 to become a phase error signal, and this phase error signal is input to the voltage controlled oscillator 9 via the low-pass filter 7 to control the voltage controlled oscillator 9. By setting it as a signal, a synchronized state is entered. In a synchronous state, the difference frequency ω is always zero, so the AFC loop stops operating. When the AFC loop is operating, the input signal and the output of the voltage controlled oscillator 9 are asynchronous, and the phase relationship between them is constantly changing by ωt radians. When the phase locked circuit is operating, the phase difference between the two is kept at nπ/2+π/4 (n=0, 1, 2, 3) and is stable.

For details of such a phase synchronization circuit, please refer to, for example, Japanese Patent Laid-Open No. 52-92464.

The delay amount .tau. of the delay circuit 3 is selected within one time slot of the main signal, and when the value is large, the sensitivity of the frequency error signal increases, but on the other hand, the amount of noise cancellation decreases. Multiplier 4, 5
Not only analog multipliers but also EX-OR circuits in digital integrated circuits can be used.

Furthermore, in FIG. 1, the explanation has been made using a 4PSK wave as the input signal, but it is clear that the present invention can be applied to a multi-level orthogonal modulated wave with more than that, and in that case, the input signal shown in FIG. As the multiplier circuit 2, a multiplier circuit suitable for the modulation method may be used.

Although the structure and operation of the present invention have been explained above with reference to one preferred embodiment thereof, it is merely an example, and it goes without saying that the present invention is not limited only to the embodiment described here. It is.

As described above, according to the present invention, it is possible to obtain a frequency error signal that does not include noise, which is the demodulated and doubled main signal, so that the C/N value of the voltage controlled oscillator output is not degraded. do not have.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Quadrature phase detector, 2... Multiplier circuit, 3...
...Delay circuit, 4, 5... Multiplication circuit, 6... Subtraction circuit, 7, 8... Low pass filter, 9... Voltage controlled oscillator.

Claims (1)

[Claims] 1. A detection means that performs orthogonal phase detection of an input signal and outputs two orthogonal phase detection outputs, and one detection output of this detection means that has a predetermined phase delay difference and is multiplied by the other detection output to generate a frequency error signal. 1st to get
a second multiplication means for multiplying the two detection outputs of the detection means; a subtraction means for subtracting between the first multiplication means and the second multiplication means; means for calculating a phase error signal by inputting the two detection outputs, and supplying an output signal whose oscillation frequency changes according to the control signal to the detection means using the output signal of the subtraction means and the phase error signal as control signals. A synchronous detection receiving device comprising oscillation means.