JPH04370968A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To control characteristics, and to inhibit a short channel effect in a MOS semiconductor device. CONSTITUTION:The bit lines 8 of N-type diffusion layers extended in the vertical direction of a paper surface are formed to a P-type silicon substrate 2, selectively formed epitaxial layers are formed among the bit lines 8, punch- through stopper layers 10 are shaped to the lower sections of the epitaxial layers 9, and channel layers 12 are formed on the surfaces of the epitaxial layers 9. A belt-like word line 18 extended in the direction orthogonal to the bit lines 8 is formed through gate oxide films 14 on the epitaxial layers 9 and insulating films 16 on the bit lines 8.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device such as a memory that requires high integration and a method of manufacturing the same.

0002

2. Description of the Related Art As semiconductor devices become more highly integrated and their elements become smaller, the characteristics of MOS transistors deteriorate due to short channel effects. In order to prevent characteristic deterioration due to the short channel effect, it is said that an LDD structure, deep channel doping, pocket implant, etc. are effective. In the LDD structure, low concentration ions are first implanted using the gate electrode as a mask, then side falls are formed on the sides of the gate electrode by high temperature CVD and RIE, and then high concentration ions are implanted using the side falls as a mask. . In deep channel doping, ions are implanted deep into the channel region at high energy of 50 to 100 KeV. In the pocket implant, ions are implanted deep with high energy after the gate electrode is formed.

0003

[Problems to be Solved by the Invention] The LDD structure requires a complicated process, which adversely affects yield and the like. In deep channel doping and pocket implants, ions are implanted deep into the substrate from the surface of the substrate, resulting in large variations in implantation, and the implanted impurities are distributed in the depth direction of the substrate, resulting in problems with threshold uniformity and Controllability is poor and it is disadvantageous to miniaturization of elements. An object of the present invention is to provide a semiconductor device whose characteristics can be easily controlled and whose short channel effect is suppressed. The present invention also aims to provide a method for manufacturing such a semiconductor device.

0004

[Means for Solving the Problems] In the MOS type semiconductor device of the present invention, the source region and the drain region are made of a diffusion layer of a semiconductor substrate, the region between the source and drain including the channel region is made of an epitaxially grown layer, and A punch-through stopper layer is present only below the channel region.

One example in which this MOS type semiconductor device is effectively utilized is a ROM having a planar structure. In the planar structure, source regions and drain regions extend in a band shape and are alternately arranged in parallel with each other, and are arranged on a channel region. The gate electrode provided through the gate oxide film also serves as a word line and extends in a direction perpendicular to the source and drain regions.

The manufacturing method of the present invention includes the following steps (A) to (H). (A) Step of introducing impurities to form the source region and drain region to the entire surface of the semiconductor substrate to form a diffusion layer, (B) Step of forming an insulating film on the substrate surface, (C) Source region and drain a step of removing the diffusion layer other than the region by etching to form an opening; (D) a step of introducing impurities of a conductivity type opposite to that of the source/drain into the bottom of the opening; (E) selective epitaxial growth in the opening. (F) forming a gate oxide film on the surface of the epitaxial growth layer; (G) introducing impurities for threshold control near the surface of the epitaxial growth layer; (H) the gate oxide film. The process of forming a gate electrode on top.

[0007]

[Operation] The presence of the punch-through stopper layer below the channel region improves the breakdown voltage. In the punch-through stopper layer, an opening is formed by etching the substrate, and impurities are introduced into the bottom surface of the opening, so that the impurity can be introduced with good controllability and there is little variation. An epitaxial layer is selectively formed in the opening where the punch-through stopper layer is introduced, and a channel region is formed in the epitaxial layer, so impurities are introduced into the punch-through stopper layer to control the threshold value of the channel region. It can be formed uniformly and with good controllability regardless of the shape.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment in which the present invention is applied to a ROM having a planar structure. However, illustrations of interlayer insulating films, wiring, passivation films, etc. are omitted. In the active region surrounded by a channel stopper layer 4 and a field oxide film 6 on the surface of a P-type silicon substrate 2, a bit line 8 of a source/drain region made of an N-type diffusion layer extending perpendicular to the plane of the paper is formed. The bit line 8 has source regions and drain regions arranged alternately. A region 9 between bit lines 8 is a selectively formed epitaxial growth layer, and a P-type impurity diffusion layer is formed as a punch-through stopper layer 10 under the epitaxial layer 9. A channel region 12 is formed in the surface of the epitaxial layer 9 by introducing P-type impurities for threshold voltage control. A gate oxide film 14 is formed on the surface of the epitaxial layer 9, and an insulating film 16 thicker than the gate oxide film 14 is formed on the bit line 8. A band-shaped word line 18 extending in a direction perpendicular to the bit line 8 is formed on the gate oxide film 14 and the insulating film 16.
is formed. The word line 18 is made of a polycrystalline silicon film and also serves as a gate electrode.

A method of manufacturing one embodiment will be explained with reference to FIG. (A) By a known process on a P-type silicon substrate 2,
A channel stopper layer 4 and a field oxide film 6 are formed. In order to form sources and drains in the memory section, N-type impurities 20 such as arsenic and phosphorus are ion-implanted into the entire surface. The implantation conditions at this time are that the implantation energy is 10 to 100Ke.
V, and the injection amount is about 1015 to 1020/cm3.

(B) N by heat treatment and implanted impurities
A mold diffusion layer 8 is formed. A silicon oxide film 16 is formed on the substrate on which the diffusion layer 8 is formed by thermal oxidation or CVD. The thickness of the oxide film 16 affects the oxide film capacitance between the polycrystalline silicon film for the gate electrode formed in a later step and the diffusion layer 8, so it is made thick enough to cause few problems in terms of steps. Therefore, the thickness of this oxide film 16 is set to 100
The thickness is 0 to 5000 Å.

(C) By photolithography and etching, the diffusion layer 8 other than the source/drain regions is removed to form an opening 22. Thereafter, P-type impurity 24 such as boron is ion-implanted to prevent punch-through. The implantation conditions at this time are that the implantation energy is 10 to 50 KeV and the implantation amount is approximately 1014 to 1018/cm3.

(D) A silicon epitaxial layer 9 is formed only in the opening 22 by low temperature selective epitaxial growth. This epitaxial layer 9 is formed at a low temperature of 800 to 1000°C, and the film thickness is about the same as that of the diffusion layer 8, with a thickness of 1000 to 500°C.
000 Å. Further, the impurity implanted into the bottom of the opening 22 in the previous step becomes the punch-through stopper layer 10 by heat treatment. Next, a gate oxide film 14 is formed on the epitaxial layer 9 to form a gate of the memory transistor.
It is formed to a thickness of about 0 to 500 Å. After that, channel doping 26 for controlling the threshold value of the memory transistor is performed.
Do this. The implantation conditions at this time are that the implantation energy is 1
0-50KeV, injection amount 1014-1018/cm3
degree. Heat treatment is performed to form channel region 12 with implanted impurities for channel doping.

Next, a polycrystalline silicon film for a word line which also serves as a gate electrode is formed and patterned into a band shape extending in a direction perpendicular to the bit line 8 by photolithography and etching to form a word line 18. Thereafter, a memory device is completed by forming an interlayer insulating film, forming contact holes, forming metal wiring, and forming a passivation film using known processes.

In step (B) of FIG. 2, the silicon oxide film 16
A silicon nitride film may be formed instead. The word line 18 may be formed by depositing a high melting point metal film such as tungsten on the surface of the polycrystalline silicon film and converting it into a polycide in order to lower the resistance.

[0015]

According to the present invention, since the punch stopper layer is present under the channel region, the source/drain breakdown voltage is improved. The punch-through stopper layer is formed by etching the silicon substrate and shallowly implanting the hole into the opening, so that variations in implantation are small. Since the channel region is formed in the epitaxial layer formed on the punch-through stopper layer, the concentration of the channel region can be controlled only by channel doping, and the uniformity of the threshold value is improved. Since the punch-through stopper layer is formed only in the region between the source and drain and does not go under the source or drain region, the junction capacitance between the source or drain region and the substrate does not increase. Since the manufacturing method of the present invention is a combination of only established and known techniques, it can be carried out with a high yield.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a main part showing one embodiment.

FIG. 2 is a process sectional view showing a manufacturing method of one embodiment.

[Explanation of symbols]

2 P-type silicon substrate 8 Bit line (source/drain region)
9 Epitaxial layer 10 Punch-through stopper layer 12
Channel region 14 Gate oxide film 18 Word line 22 which also serves as a gate electrode
opening

Claims (3)

[Claims] Claim 1: The source region and the drain region are made of a diffusion layer of a semiconductor substrate, the region between the source and drain including the channel region is made of an epitaxial growth layer, and the punch-through stopper layer is present only under the channel region. MOS type semiconductor device. 2. A source region and a drain region extend in a strip shape and are alternately arranged parallel to each other, and a gate electrode provided on the channel region with a gate oxide film serving as a word line serves as a source region and a drain region. 2. The MOS semiconductor device according to claim 1, which is a ROM having a planar structure extending in orthogonal directions. 3. A method for manufacturing a semiconductor device comprising the following steps (A) to (H). (A) Step of introducing impurities to form the source region and drain region to the entire surface of the semiconductor substrate to form a diffusion layer, (B) Step of forming an insulating film on the substrate surface, (C) Source region and drain a step of removing the diffusion layer other than the region by etching to form an opening; (D) a step of introducing impurities of a conductivity type opposite to that of the source/drain into the bottom of the opening; (E) selective epitaxial growth in the opening. (F) forming a gate oxide film on the surface of the epitaxial growth layer; (G) introducing impurities for threshold control near the surface of the epitaxial growth layer; (H) the gate oxide film. The process of forming a gate electrode on top.