JPH04369622A - Liquid crystal display substrate, liquid crystal display panel, and liquid crystal display device - Google Patents

Abstract

PURPOSE:To eliminate a defect in connection between connection terminals and signal line terminals on a circuit board by converging extension lines from the signal line terminal group of a signal line terminal group on a single point. CONSTITUTION:Gate terminals GTM and drain terminals DTM are divided into plural signal terminal groups and the extension lines from the drain terminals DTM is, for example, the drain terminal DTM group are converged on single point OS. Further, the extension lines from the respective connection terminals TTM in the connection terminal TTM group which is formed on a TAB substrate TAB and connected to the drain terminal DTM group are converged on signal point OT. Therefore, even if an error in the distance WT between connection terminals TTM at both ends is generated, all the connection terminals TTM can be positioned on the drain terminals DTM by shifting the TAB substrate in the direction of video signal lines DL connected to the drain terminals DTM at the time of connecting the rain terminal DTM to the connection terminals TTM, so any defect in connection between the connection terminals TTM, and drain terminal DTM is not generated.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display substrate, a liquid crystal display panel, and a liquid crystal display device, and more particularly to an active matrix liquid crystal display substrate, a liquid crystal display panel, and a liquid crystal display device using thin film transistors and the like.

0002

2. Description of the Related Art An active matrix liquid crystal display device includes a nonlinear element (switching element) corresponding to each of a plurality of pixel electrodes arranged in a matrix. Theoretically, the liquid crystal in each pixel is constantly driven (duty ratio 1.0), so the active method has better contrast than the so-called simple matrix method, which uses a time-division drive method, especially for color LCDs. It is becoming an indispensable technology for display devices. A typical switching element is a thin film transistor (TFT).

FIG. 15 shows a conventional active matrix liquid crystal display device (Nikkei Electronics No. 495 (1)
990), pp. 122-136). In the figure, SUB1 is a lower transparent glass substrate, GL is a scanning signal line formed on the lower transparent glass substrate SUB1,
DL is a video signal line formed on the scanning signal line GL via an insulating film, GTM1 is a gate terminal connected to the scanning signal line GL, DTM1 is a drain terminal connected to the video signal line DL, and TAB is a TAB substrate. , DCE is TAB substrate TA
The drive circuit element mounted in B, CTM is the drive circuit element D
The connection terminal connected to CE, TTM1 is the drive circuit element D
In the connecting terminal connected to CE, the pitch PT of the connecting terminal TTM1 and the length DT are the pitch PS of the drain terminal DTM1.
, the length DS is equal, the pitches PT and PS are 0.2 mm, the lengths DT and DS are 2 to 3 mm, and the number of connection terminals TTM1 is 160, and the connection terminals TTM at both ends
The distance WT between the two is 32 mm. And the connection terminal T
TM1 is connected to the drain terminal DTM1 via an anisotropic conductive film.

0004

[Problems to be Solved by the Invention] In such a liquid crystal display device, since the TAB substrate TAB is made of an organic film such as a polyimide resin film, the TAB substrate TAB
It is easy to expand and contract during the manufacturing process, and the error in distance WT is ±
Since the pitch is 0.1 mm or more, the pitch between the connection terminal TTM1 and the drain terminal DTM1 does not match, resulting in a poor connection between the connection terminal TTM1 and the drain terminal DTM1.

The present invention has been made to solve the above-mentioned problems, and provides a liquid crystal display substrate, a liquid crystal display panel, and a liquid crystal display device in which connection failures between connection terminals of a circuit board and signal line terminals do not occur. The purpose is to provide.

[0006]

[Means for Solving the Problems] In order to achieve this object, in the present invention, in a liquid crystal display substrate, the extension lines of each signal line terminal of a group of signal line terminals are converged to one point.

Further, in a liquid crystal display panel, a liquid crystal display substrate is provided in which extension lines of each signal line terminal of a group of signal line terminals converge to one point.

Further, in the liquid crystal display device, there is provided a liquid crystal display panel having a liquid crystal display substrate in which extension lines of respective signal line terminals of a group of signal line terminals converge to one point, and a liquid crystal display panel having a liquid crystal display substrate in which extension lines of respective signal line terminals of a group of signal line terminals converge to one point, and an image display panel for supplying a video signal to the liquid crystal display panel. A signal driving circuit, a scanning circuit for applying a scanning signal to the liquid crystal display panel, and a control circuit for providing information for the liquid crystal display panel to the video signal driving circuit and the scanning circuit are provided.

In this case, the circuit elements of the video signal drive circuit and the scanning circuit are mounted on a circuit board, and each connection terminal of the connection terminal group formed on the circuit board and connected to the signal line terminal group is Converge the extension lines to one point.

In this case, the length of the connection terminal is made shorter than the length of the signal line terminal.

[0011]

[Function] In this liquid crystal display board, liquid crystal display panel, and liquid crystal display device, even if there is an error in the distance between the connection terminals at both ends, the circuit board can be used to connect the signal line terminal to the connection terminal. By shifting in the direction of the signal line connected to the line terminal, all the connection terminals can be positioned on the signal line terminal.

Furthermore, if the length of the connection terminal is made shorter than the length of the signal line terminal, even if the circuit board is shifted toward the signal line side, the edge of the circuit board will not ride on the protective film.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below along with embodiments in which the present invention is applied to a liquid crystal display substrate and a liquid crystal display panel of an active matrix color liquid crystal display device.

In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

FIG. 2 shows an active system to which this invention is applied.
A plan view showing one pixel and its surroundings of a matrix color liquid crystal display device. FIG. 3 is a cross-sectional view taken along section line 3-3 in FIG. 2 and a cross-sectional view near the seal portion of the display panel. FIG. It is a sectional view taken along the -4 cutting line. Also, Figure 7 (
2 shows a plan view when a plurality of pixels shown in FIG. 2 are arranged.

(Pixel Arrangement) As shown in FIG. 2, each pixel is connected to two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or horizontal signal lines). (vertical signal line) DL (in the area surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1, and a storage capacitor element Cadd. The scanning signal lines GL extend in the column direction, and a plurality of scanning signal lines GL are arranged in the row direction. Video signal line D
L extends in the row direction, and a plurality of L's are arranged in the column direction.

(Overall cross-sectional structure of display section) As shown in FIG. 3, a thin film transistor TFT and a transparent pixel electrode ITO1 are formed on the lower transparent glass substrate SUB1 side with respect to the liquid crystal LC, and a color electrode is formed on the upper transparent glass substrate SUB2 side. A filter FIL and a light shielding film BM forming a light shielding black matrix pattern are formed. The lower transparent glass substrate SUB1 has a thickness of, for example, about 1.1 mm. Further, silicon oxide films SIO formed by dipping treatment or the like are provided on both surfaces of the transparent glass substrates SUB1 and SUB2. Therefore, even if there are sharp scratches on the surface of the transparent glass substrates SUB1 and SUB2,
Since sharp scratches can be covered with the silicon oxide film SIO, damage to the scanning signal line GL and color filter FIL can be effectively prevented.

The center part of FIG. 3 shows a cross section of one pixel, the left side shows a cross section of the left edge of the transparent glass substrates SUB1 and SUB2 where external lead wiring is present, and the right side shows a cross section of the transparent glass substrate SUB1, SUB2. A cross section of the right edge portion of the glass substrates SUB1 and SUB2 where no external lead wiring is present is shown.

The sealing material SL shown on the left and right sides of FIG. 3 is configured to seal the liquid crystal LC, and includes the transparent glass substrate SUB1, excluding the liquid crystal sealing opening (not shown).
It is formed along the entire periphery of the SUB2. The sealing material SL is made of, for example, epoxy resin.

The common transparent pixel electrode ITO2 on the side of the upper transparent glass substrate SUB2 is connected at least in one place to an external lead wiring formed on the side of the lower transparent glass substrate SUB1 by means of a silver paste material SIL. This external lead wiring is formed in the same manufacturing process as each of the gate electrode GT, source electrode SD1, and drain electrode SD2.

Orientation films ORI1, ORI2, transparent pixel electrode ITO1, common transparent pixel electrode ITO2, protective film PSV1
, PSV2, and the insulating film GI are each made of a sealing material S.
Formed inside L. The polarizing plates POL1 and POL2 are formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively.

The liquid crystal LC is sealed between a lower alignment film ORI1 and an upper alignment film ORI2, which set the orientation of liquid crystal molecules, and is sealed by a seal portion SL.

The lower alignment film ORI1 is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.

A light shielding film BM and a color filter FI are provided on the inner surface (liquid crystal LC side) of the upper transparent glass substrate SUB2.
L, protective film PSV2, common transparent pixel electrode ITO2 (CO
M) and an upper alignment film ORI2 are sequentially stacked.

This liquid crystal display device has a lower transparent glass substrate S.
The layers on the UB1 side and the upper transparent glass substrate SUB2 side are formed separately, and then the upper and lower transparent glass substrates SUB1 are formed.
, SUB2 are stacked on top of each other and a liquid crystal LC is sealed between them.

(Thin Film Transistor TFT) The thin film transistor TFT operates such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and drain becomes small, and when the bias is reduced to zero, the channel resistance becomes large.

The thin film transistor TFT of each pixel is divided into two (plurality) within the pixel, and is composed of thin film transistors (divided thin film transistors) TFT1 and TFT2. Each of the thin film transistors TFT1 and TFT2 has substantially the same size (channel length and width are the same). Each of the divided thin film transistors TFT1 and TFT2 mainly has a gate electrode GT.
, gate insulating film GI, i-type (intrinsic)
, a pair of source electrodes SD1 and drain electrodes SD2. Note that the source and drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is reversed during operation, so it should be understood that the source and drain are interchanged during operation. However, in the following description, for convenience, one side is fixed as a source and the other side is fixed as a drain.

(Gate electrode GT) The gate electrode GT is shown in FIG.
As shown in detail in (a plan view depicting only the second conductive film g2 and i-type semiconductor layer AS in FIG. 2), the shape projects vertically from the scanning signal line GL (upward in FIGS. 2 and 8). (branched into a T-shape)
. Gate electrode GT is thin film transistor TFT1, TFT
It is configured to protrude to the respective formation regions of 2. The respective gate electrodes GT of the thin film transistors TFT1 and TFT2 are integrated (as a common gate electrode).
It is formed continuously with the scanning signal line GL. The gate electrode GT is composed of a single-layer second conductive film g2. The second conductive film g2 is formed using, for example, an aluminum film formed by sputtering, and has a thickness of about 1000 to 5500 Å. Furthermore, an aluminum anodic oxide film AOF is provided on the gate electrode GT.

As shown in FIGS. 2, 3 and 8, this gate electrode GT is formed larger than the i-type semiconductor layer AS so as to completely cover it (as viewed from below). Therefore, when a backlight BL such as a fluorescent lamp is attached below the lower transparent glass substrate SUB1, the gate electrode GT made of opaque aluminum forms a shadow.
The i-type semiconductor layer AS is not irradiated with backlight light, making it difficult for a conductive phenomenon due to light irradiation, that is, deterioration of the off-characteristics of the thin film transistor TFT, to occur. Note that the original size of the gate electrode GT is the same as that of the source electrode SD1 and the drain electrode SD.
2 (including the alignment margin between the gate electrode GT, source electrode SD1, and drain electrode SD2), and the depth length that determines the channel width W is the width of the source electrode SD1. It is determined by the ratio of the distance (channel length) L between the gm and the drain electrode SD2, that is, the factor W/L that determines the mutual conductance gm.

Gate electrode GT in this liquid crystal display device
Of course, the size is made larger than the original size mentioned above.

(Scanning signal line GL) The scanning signal line GL is the second
It is composed of a conductive film g2. The second conductive film g2 of the scanning signal line GL is formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT, and is configured integrally. Moreover, an aluminum anodic oxide film AO is formed on the scanning signal line GL.
F is provided.

(Insulating Film GI) The insulating film GI is used as a gate insulating film for each of the thin film transistors TFT1 and TFT2. The insulating film GI is formed on the gate electrode GT and the scanning signal line GL. The insulating film GI is formed using, for example, a silicon nitride film formed by plasma CVD, and has a thickness of about 3000 Å.

(I-type semiconductor layer AS) As shown in FIG. 8, the i-type semiconductor layer AS is used as a channel forming region for each of thin film transistors TFT1 and TFT2 which are divided into a plurality of parts. The i-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film and has a thickness of about 1800 Å.

This i-type semiconductor layer AS was formed by the same plasma CVD process following the formation of the insulating film GI to be used as a gate insulating film made of Si3N4 by changing the composition of the supplied gas.
The plasma CVD device is formed without being exposed to the outside from the plasma CVD device. Further, an N(+) type semiconductor layer d0 (FIG. 3) doped with 2.5% phosphorus (P) for ohmic contact is similarly formed continuously to a thickness of about 400 Å. After that, the lower transparent glass substrate SUB1 is
It is taken out from the VD device and processed into N(
The +) type semiconductor layer d0 and the i type semiconductor layer AS are patterned into independent island shapes as shown in FIGS. 2, 3, and 8.

As shown in detail in FIGS. 2 and 8, the i-type semiconductor layer AS is also provided between the scanning signal line GL and the video signal line DL at an intersection (crossover section). The i-type semiconductor layer AS at this intersection is configured to reduce short circuits between the scanning signal line GL and the video signal line DL at the intersection.

(Source electrode SD1, drain electrode SD2
) Thin film transistors TFT1 and TFT divided into multiple parts
2, each of the source electrode SD1 and drain electrode SD2
As shown in detail in FIGS. 2, 3, and 9 (a plan view depicting only the first to third conductive films d1 to d3 in FIG. 2),
They are provided separately on the i-type semiconductor layer AS.

[0037] Each of the source electrode SD1 and the drain electrode SD2 includes a first conductive film d1, a second conductive film d2, and a third conductive film d from the lower layer side in contact with the N(+) type semiconductor layer d0.
3 are stacked one on top of the other in sequence. Source electrode SD
The first conductive film d1, the second conductive film d2, and the third conductive film d3 of No. 1 are formed in the same manufacturing process as the first conductive film d1, the second conductive film d2, and the third conductive film d3 of the drain electrode SD2. .

The first conductive film d1 is a chromium film formed by sputtering, and is formed with a thickness of 500 to 1000 Å (in this liquid crystal display device, the thickness is about 600 Å). The thicker the chromium film is, the greater the stress will be.
The film thickness is formed within a range of approximately 000 Å. The chromium film has good contact with the N(+) type semiconductor layer d0. In the chromium film, the aluminum of the second conductive film d2, which will be described later, is N(
It constitutes a so-called barrier layer that prevents diffusion into the +) type semiconductor layer d0. As the first conductive film d1, in addition to a chromium film, a high melting point metal (Mo, Ti, Ta, W) film, a high melting point metal silicide (MoSi2, TiSi2, TaSi
2. It may be formed using a WSi2) film.

After patterning the first conductive film d1 by photoprocessing, using the same photoprocessing mask or patterning the first conductive film d1,
Using the conductive film d1 as a mask, the N(+) type semiconductor layer d0 is removed. That is, the portions of the N(+) type semiconductor layer d0 remaining on the i-type semiconductor layer AS other than the first conductive film d1 are removed by self-alignment. At this time, since the N(+) type semiconductor layer d0 is etched so that its entire thickness is removed, the i-type semiconductor layer AS is also slightly etched on its surface, but the extent is controlled by the etching time. do it.

Thereafter, the second conductive film d2 is formed by sputtering aluminum to a thickness of 3000 to 5500 Å (in this liquid crystal display device, the thickness is about 3500 Å). The aluminum film has less stress than the chromium film, and can be formed to a thick film thickness, so that the source electrode SD
1. It is configured to reduce the resistance values of the drain electrode SD2 and the video signal line DL. The second conductive film d2 may be formed of an aluminum film containing silicon or copper (Cu) as an additive in addition to the aluminum film.

After patterning the second conductive film d2 using a photoprocessing technique, a third conductive film d3 is formed. This third conductive film d3 is a transparent conductive film (I) formed by sputtering.
ndium-Tin-Oxide ITO: Nesa film)
It is formed with a film thickness of 1000 to 2000 Å (in this liquid crystal display device, the film thickness is about 1200 Å). This third conductive film d3 includes a source electrode SD1 and a drain electrode SD.
2 and the video signal line DL, and also constitutes the transparent pixel electrode ITO1.

Each of the first conductive film d1 of the source electrode SD1 and the first conductive film d1 of the drain electrode SD2 is located inward (
(into the channel region). That is, the first conductive film d1 in these parts is the second conductive film d2,
The structure is such that the channel length L of the thin film transistor TFT can be defined independently of the third conductive film d3.

Source electrode SD1 is transparent pixel electrode ITO1
It is connected to the. The source electrode SD1 has a stepped shape of the i-type semiconductor layer AS (corresponds to the sum of the thickness of the first conductive film g1, the thickness of the N(+)-type semiconductor layer d0, and the thickness of the i-type semiconductor layer AS). It is constructed along the steps (steps). Specifically, the source electrode SD1 includes a first conductive film d1 formed along the step shape of the i-type semiconductor layer AS, and a first conductive film d1 formed along the step shape of the i-type semiconductor layer AS.
In contrast, a transparent pixel electrode ITO1 is formed on the upper part of the conductive film d1.
a second conductive film d formed with a smaller size on the side connected to
2, and the first conductive film d1 exposed from the second conductive film d2.
and a third conductive film d3 connected to the third conductive film d3. The second conductive film d2 of the source electrode SD1 cannot overcome the step shape of the i-type semiconductor layer AS because the chromium film of the first conductive film d1 cannot be formed thickly due to increased stress, so the second conductive film d2 of the source electrode SD1 can overcome this i-type semiconductor layer AS. It is configured for. In other words, step coverage is improved by forming the second conductive film d2 thickly. Since the second conductive film d2 can be formed thickly, the resistance value of the source electrode SD1 (drain electrode SD2
(The same applies to the video signal line DL). Since the third conductive film d3 cannot overcome the step shape caused by the i-type semiconductor layer AS of the second conductive film d2, by reducing the size of the second conductive film d2,
It is configured to be connected to the exposed first conductive film d1. The first conductive film d1 and the third conductive film d3 not only have good adhesion, but also have a small step shape at the connection between them, so it is possible to reliably connect the source electrode SD1 and the transparent pixel electrode ITO1. can.

(Transparent pixel electrode ITO1) Transparent pixel electrode I
TO1 constitutes one of the pixel electrodes of the liquid crystal display section.

The transparent pixel electrode ITO1 is connected to the source electrode SD1 of the thin film transistor TFT1 and the thin film transistor T
It is connected to the source electrode SD1 of FT2. Therefore, when a defect occurs in one of the thin film transistors TFT1 and TFT2, for example, the thin film transistor TFT1, the thin film transistor TFT1 and the video signal line DL are separated by laser light or the like during the manufacturing process, and the thin film transistor TFT1 and the transparent pixel electrode ITO1 are separated from each other by laser light or the like during the manufacturing process.
If you separate them, there will be no point defects or line defects, and 2
Since defects rarely occur in the two thin film transistors TFT1 and TFT2 at the same time, the probability of point defects occurring can be extremely reduced.

(Protective film PSV1) Thin film transistor TF
A protective film PSV1 is provided on the T and transparent pixel electrode ITO1. The protective film PSV1 is formed mainly to protect the thin film transistor TFT from moisture etc.
Use a material that is highly transparent and has good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and has a film thickness of 80%.
The film thickness is approximately 00 Å.

(Gate terminal GTM, drain terminal DTM
) As shown in FIG. 5, the gate terminal GTM is connected to the first conductive film g.
1 and a third conductive film d3.

Furthermore, as shown in FIG. 6, the drain terminal D
TM is composed of a first conductive film g1 and a third conductive film d3.

The first conductive film g1 is formed using, for example, a chromium (Cr) film formed by sputtering, and has a thickness of about 1000 Å.

As shown in FIGS. 1 and 14, the gate terminal G
TM and drain terminal DTM are divided into a plurality of signal line terminal groups, and for example, the extension line of each drain terminal DTM of the drain terminal DTM group converges at one point OS. In addition, a drain terminal DT formed on the TAB substrate TAB
The extension lines of the connection terminals TTM of the connection terminals TTM group connected to the M group converge at one point OT. Therefore, even if an error occurs in the distance WT between the connecting terminals TTM at both ends, when connecting the drain terminal DTM and the connecting terminal TTM, the TAB substrate TAB is connected to the drain terminal DTM.
By shifting the connection terminals TTM in the direction of the video signal line DL connected to the drain terminal DTM, all the connection terminals TTM can be positioned above the drain terminal DTM.
There will be no connection failures with the Here, the distance between the drain terminals DTM at both ends of the drain terminal DTM group is W
S, points OS, OT and drain terminal DTM group, connection terminal T
Drain terminal DTM and connection terminal TTM in the center of TM group
When WT/WS is within the range shown by the following equation, all the connection terminals TTM can be positioned over the drain terminal DTM by shifting the TAB substrate TAB.

1-(DS-DT)/2R<WT/WS<
1+(DS-DT)/2R For example, when the length DT is 2 mm, the length DS is 3 mm, the distance R is 10 cm, and the distance WS is 32 mm, the distance W
If the error of T is within ±0.16mm, TAB substrate T
By shifting AB, all the connection terminals TTM can be positioned above the drain terminal DTM.

Furthermore, since the length DT is shorter than the length DS, even if the TAB substrate TAB is shifted toward the video signal line DL side, the end of the TAB substrate TAB will not ride on the protective film PSV1. The drain terminal DTM and the connection terminal TTM can be reliably connected.

It should be noted that the configurations of the other drain terminal DTM sections and gate terminal GTM sections are also similar to the above-described drain terminal DTM sections.
The composition is similar to that of the county. (Light-shielding film BM) On the upper transparent glass substrate SUB2 side, an i-type semiconductor layer A is used as a channel formation region to which external light (light from above in FIG. 3) is applied.
A light shielding film BM is provided to prevent light from entering S, and the light shielding film BM has a pattern as shown by hatching in FIG. Note that FIG. 10 is a plan view depicting only the third conductive film d3 made of an ITO film, the color filter FIL, and the light shielding film BM in FIG. The light shielding film BM is formed of, for example, an aluminum film or a chromium film having a high light shielding property, and in this liquid crystal display device, the chromium film is formed by sputtering to a thickness of about 1300 Å.

Therefore, the thin film transistors TFT1,
The i-type semiconductor layer AS of the TFT2 is sandwiched between the upper and lower light-shielding films BM and the large gate electrode GT, and that portion is not exposed to external natural light or backlight light. The light shielding film BM is formed around the pixel as shown by the hatched area in FIG.
The effective display area of pixels is partitioned. Therefore, the outline of each pixel becomes clear due to the light shielding film BM, and the contrast is improved. In other words, the light shielding film BM has two functions: shielding the i-type semiconductor layer AS and serving as a black matrix.

[0055] Also, a portion opposite to the edge portion on the root side in the rubbing direction of the transparent pixel electrode ITO1 (lower right portion in FIG. 2)
is shielded from light by the light-shielding film BM, so even if a domain occurs in the above-mentioned portion, the domain will not be visible and the display characteristics will not deteriorate.

Note that it is also possible to attach the backlight to the upper transparent glass substrate SUB2 side and make the lower transparent glass substrate SUB1 the observation side (externally exposed side).

(Common Transparent Pixel Electrode ITO2) The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is determined by each pixel electrode ITO1. It changes in response to the potential difference (electric field) between the ITO2 and the common transparent pixel electrode ITO2. The configuration is such that a common voltage Vcom is applied to this common transparent pixel electrode ITO2. The common voltage Vcom is a low-level drive voltage Vdmin and a high-level drive voltage Vdmax applied to the video signal line DL.
It is the intermediate potential between

(Color Filter FIL) The color filter FIL is constructed by coloring a dyed base material made of a resin material such as acrylic resin with a dye. Color filter F
The IL is formed in a stripe shape at a position facing the pixel (
(Fig. 11) shows only the third conductive film layer d3, light shielding film BM, and color filter FIL in Fig. 7, and each of the B, R, and G color filters F
ILs are 45°, 135°, and cross hatched, respectively). As shown in FIG. 10, the color filter FIL is formed in a large size so as to cover the entire transparent pixel electrode ITO1, and the light shielding film BM is formed on the periphery of the transparent pixel electrode ITO1 so as to overlap with the edge portions of the color filter FIL and the transparent pixel electrode ITO1. It is formed more inward.

Color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyed base material other than the red filter forming area is removed using photolithography technology. Thereafter, the dyed base material is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing similar steps.

(Protective film PSV2) The protective film PSV2 is a liquid crystal L using dyes that dye the color filter FIL in different colors.
This is provided to prevent leakage to C. The protective film PSV2 is made of a transparent resin material such as acrylic resin or epoxy resin.

(Equivalent circuit of entire display device) FIG. 12 shows a wiring diagram of the equivalent circuit of the display matrix section and its peripheral circuits. Although this figure is a circuit diagram, it is drawn to correspond to the actual geometrical arrangement. AR is a matrix array in which a plurality of pixels are arranged two-dimensionally.

In the figure, X means a video signal line DL, and subscripts G, B, and R are added corresponding to green, blue, and red pixels, respectively. Y means the scanning signal line GL, and the subscripts 1, 2, 3, . . . , end are added according to the order of scanning timing.

Video signal lines X (subscript omitted) are arranged alternately on the upper side (
(or odd number) video signal drive circuit He, and is connected to the lower (or even number) video signal drive circuit Ho.

A scanning signal line Y (subscript omitted) is connected to a vertical scanning circuit V.

[0065] The SUP uses a power supply circuit to obtain a plurality of divided and stabilized voltage sources from one voltage source and information for a CRT (cathode ray tube) from a host (upper processing unit) to a TFT liquid crystal display device. This is a circuit that includes a circuit that exchanges information for use.

(Structure of storage capacitor element Cadd) The transparent pixel electrode ITO1 is formed so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TFT. This superposition is shown in Figure 4.
As is clear from the above, the transparent pixel electrode ITO1 is used as one electrode PL2, and the adjacent scanning signal line GL is used as the other electrode P.
A storage capacitance element (electrostatic capacitance element) Cadd designated as L1 is configured. The dielectric film of this storage capacitor element Cadd is composed of an insulating film GI used as a gate insulating film of the thin film transistor TFT and an anodic oxide film AOF.

As is clear from FIG. 8, the storage capacitor element Cadd is formed in the widened portion of the second conductive film g2 of the scanning signal line GL. Note that the second conductive film g2 at the portion intersecting with the video signal line DL is made thin in order to reduce the probability of short circuit with the video signal line DL.

Similar to the source electrode SD1, the transparent pixel electrode ITO1 is disconnected in a part between the transparent pixel electrode ITO1 and the electrode PL1, which are overlapped to form the storage capacitor element Cadd, when the transparent pixel electrode ITO1 goes over the step shape. An island region made up of the first conductive film d1 and the second conductive film d2 is provided to prevent this. This island area is the transparent pixel electrode I
The structure is made as small as possible so as not to reduce the area (aperture ratio) of TO1. (Equivalent circuit of storage capacitor element Cadd and its operation) An equivalent circuit of the pixel shown in FIG. 2 is shown in FIG. In FIG. 13, Cgs is a thin film transistor TF
This is a parasitic capacitance formed between the gate electrode GT and source electrode SD1 of T. The dielectric film of the parasitic capacitance Cgs is an insulating film GI. Cpix is the transparent pixel electrode ITO1 (PI
This is a liquid crystal capacitor formed between the common transparent pixel electrode ITO2 (COM) and the common transparent pixel electrode ITO2 (COM). The dielectric film of the liquid crystal capacitor Cpix includes the liquid crystal LC, the protective film PSV1, and the alignment films ORI1 and O.
It is RI2. Vlc is a midpoint potential.

The storage capacitor element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the thin film transistor TFT switches. This situation can be expressed as the following formula.

ΔVlc={Cgs/(Cgs+Cadd+Cpix)
}×ΔVg Here, ΔVlc represents a change in the midpoint potential due to ΔVg. This variation ΔVlc causes a direct current component applied to the liquid crystal LC, but the larger the holding capacitance Cadd is, the smaller its value can be. Furthermore, the storage capacitor element Cadd also has the effect of lengthening the discharge time, so that image information is stored for a long time after the thin film transistor TFT is turned off. Reducing the DC component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce so-called burn-in, in which the previous image remains when switching between liquid crystal display screens.

As described above, since the gate electrode GT is made large enough to completely cover the i-type semiconductor layer AS, the overlapping area with the source electrode SD1 and drain electrode SD2 increases, and therefore the parasitic capacitance Cgs increases. , the opposite effect occurs that the midpoint potential Vlc becomes more susceptible to the influence of the gate (scanning) signal Vg. However, the storage capacitor C
By providing add, this disadvantage can also be eliminated.

The storage capacitance of the storage capacitor element Cadd is 4 to 8 times (
4・Cpix<Cadd<8・Cpix), parasitic capacitance C
8 to 32 times that of gs (8・Cgs<Cadd<32
・Set to a value of about Cgs).

(Connection method of storage capacitor element Cadd electrode line) The first-stage scanning signal line GL (Y0), which is used only as a storage capacitor electrode line, is connected to the common transparent pixel electrode ITO2 (Vcom) as shown in FIG. Connecting. As shown in FIG. 3, the common transparent pixel electrode ITO2 is connected to an external wiring at the peripheral edge of the liquid crystal display device by a silver paste material SL. Furthermore, a part of the conductive film (g1 and g2) of this external wiring is formed in the same manufacturing process as the scanning signal line GL. As a result, the storage capacitor electrode line GL at the final stage can be easily connected to the common transparent pixel electrode ITO2.

The holding capacitor electrode line Y0 of the first stage is connected to the scanning signal line Yend of the final stage, connected to a DC potential point (AC grounding point) other than Vcom, or one extra scanning pulse Y0 is applied from the vertical scanning circuit V. You may also connect it so that it is received.

Next, a method for manufacturing a liquid crystal display device according to the present invention will be explained. First, a silicon oxide film SIO was provided on both sides of the lower transparent glass substrate SUB1 made of 7059 glass (trade name) by dip treatment, and then
Bake at 00°C for 60 minutes. Next, a first conductive film g1 made of chromium and having a film thickness of 1100 Å is provided on the lower transparent glass substrate SUB1 by sputtering. Next, by selectively etching the first conductive film g1 using a photolithography technique using a ceric ammonium nitrate solution as an etching solution, a gate terminal GTM and a drain terminal DTM are formed, and the gate terminal GTM is connected. anodized bus line (not shown),
Form an anodized pad (not shown) connected to an anodized bus line. Next, remove the resist using stripping liquid S502.
(trade name) and then perform O2 ashing for 1 minute. Next, a second conductive film g2 made of aluminum-palladium, aluminum-silicon, aluminum-silicon-titanium, aluminum-silicon-copper, etc. and having a thickness of 2800 Å is provided by sputtering. Next, by selectively etching the second conductive film g2 using a photolithography technique using a mixed acid of phosphoric acid, nitric acid, and acetic acid as an etching solution, the scanning signal line GL, gate electrode GT
and electrode PL1 of storage capacitor element Cadd is formed. Next, SF6 gas is introduced into a dry etching apparatus to remove residues such as silicon, and then the resist is removed. Next, a resist for anodic oxidation is provided. next,
Lower transparent glass substrate SUB1 is placed in an anodic oxidation solution consisting of a solution of 3% tartaric acid adjusted to pH 7.0 ± 0.5 with ammonia and diluted 1:9 with ethylene glycol solution.
By dipping the part to be anodized and applying an anodizing voltage to the anodizing pad, the second conductive film g2 is anodized, and a film thickness of about 1800 Å is formed on the scanning signal line GL and the gate electrode GT. An anodic oxide film AOF is provided. Next, ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a silicon nitride film with a thickness of 2000 Å, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus to form an i-type film with a thickness of 2000 Å. After forming the amorphous silicon film, hydrogen gas and
Introducing phosphine gas to form a N(+) film with a thickness of 300 Å
A mold amorphous silicon film is provided. Next, by selectively etching the N(+) type amorphous silicon film and the i-type amorphous silicon film by photolithography using SF6 and CCl4 as dry etching gas, the i-type semiconductor layer A
form S. Next, after removing the resist, the silicon nitride film is selectively etched by photolithography using SF6 as a dry etching gas, thereby forming an insulating film GI. Next, after removing the resist, a first conductive film d1 made of chromium and having a thickness of 1000 Å is provided by sputtering. Next, the first layer of the video signal line DL, source electrode SD1, and drain electrode SD2 is formed by selectively etching the first conductive film d1 using photolithography. Next, before removing the resist, CCl4 and SF6 were added to the dry etching equipment.
is introduced and selectively etches the N(+) type amorphous silicon film, thereby forming an N(+) type semiconductor layer d0. Next, after removing the resist, O2 ashing is performed for 1 minute. Next, a second conductive film d2 made of aluminum-palladium, aluminum-silicon, aluminum-silicon-titanium, aluminum-silicon-copper, etc. and having a thickness of 3500 Å is provided by sputtering. Next, the second conductive film d2 is selectively etched using photolithography to form a second layer of the video signal line DL, the source electrode SD1, and the drain electrode SD2. Next, after removing the resist, O2 ashing is performed for 1 minute. Next, a third conductive film d3 made of an ITO film having a thickness of 1000 Å is provided by sputtering. Next, by selectively etching the third conductive film d3 using a mixed acid of hydrochloric acid and nitric acid as an etching solution, the video signal line DL and the source electrode SD1 are etched.
, the third layer of the drain electrode SD2, the gate terminal GTM, the top layer of the drain terminal DTM, and the transparent pixel electrode ITO1
form. Next, after removing the resist, ammonia gas, silane gas, and nitrogen gas are introduced into a plasma CVD apparatus to form a silicon nitride film with a thickness of 1 μm. Next, a protective film PSV1 is formed by selectively etching the silicon nitride film by photolithography using SF6 as a dry etching gas.

[0076] As described above, the invention made by the present inventor is as follows.
Although this invention has been specifically explained based on the above embodiments,
It goes without saying that the invention is not limited to the embodiments described above, and that various changes can be made without departing from the spirit thereof.

For example, in the above embodiment, the steps are as follows: gate electrode formation→gate insulating film formation→semiconductor layer formation→source/
Although an inverted staggered structure in which the drain electrode is formed is shown, the present invention is also effective in a staggered structure in which the vertical relationship or the order of formation is reversed. Further, in the above embodiment, the third conductive film d3 made of ITO was formed after forming the first and second conductive films d1 and d2 made of chromium and aluminum, but after forming the ITO film, the chromium film was formed. , an aluminum film may be formed.

[0078]

Effects of the Invention As explained above, in the liquid crystal display substrate, liquid crystal display panel, and liquid crystal display device according to the present invention, even if an error occurs in the distance between the connecting terminals at both ends, all the connecting terminals can be connected to a signal. Since it can be positioned above the line terminal, poor connection between the connection terminal of the circuit board and the signal line terminal will not occur.

Furthermore, if the length of the connection terminal is made shorter than the length of the signal line terminal, even if the circuit board is moved toward the signal line side, the edge of the circuit board will not ride on the protective film. The signal line terminal and the connection terminal can be reliably connected.

[0080] As described above, the effects of the present invention are remarkable.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing a drain terminal portion of the liquid crystal display device shown in FIG. 2;

FIG. 2 is a plan view of a main part showing one pixel of a liquid crystal display section of an active matrix color liquid crystal display device to which the present invention is applied.

FIG. 3 is a cross-sectional view of a portion taken along section line 3-3 in FIG. 2 and a peripheral portion of a seal portion.

FIG. 4 is a sectional view taken along section line 4-4 in FIG. 2;

FIG. 5 is a cross-sectional view showing a gate terminal portion of the liquid crystal display device shown in FIG. 2;

6 is a sectional view showing a drain terminal portion of the liquid crystal display device shown in FIG. 2. FIG.

7 is a plan view of a main part of a liquid crystal display section in which a plurality of pixels shown in FIG. 2 are arranged; FIG.

FIG. 8 is a plan view depicting only a predetermined layer of the pixel shown in FIG. 2;

9 is a plan view depicting only a predetermined layer of the pixel shown in FIG. 2; FIG.

FIG. 10 is a plan view depicting only a predetermined layer of the pixel shown in FIG. 2;

11 is a plan view of main parts depicting only a pixel electrode layer, a light shielding film, and a color filter layer shown in FIG. 7; FIG.

FIG. 12 is an equivalent circuit diagram showing a liquid crystal display section of an active matrix color liquid crystal display device.

13 is an equivalent circuit diagram of the pixel shown in FIG. 2. FIG.

14 is a schematic diagram showing a liquid crystal display substrate of the liquid crystal display device shown in FIG. 2. FIG.

FIG. 15 is a schematic exploded view showing a part of a conventional active matrix liquid crystal display device.

[Explanation of symbols]

SUB…Transparent glass substrate GL...Scanning signal line DL...Video signal line GI...Insulating film GT...gate electrode AS...i-type semiconductor layer SD...source electrode or drain electrode PSV…Protective film BM...shading film LC…Liquid crystal TFT...Thin film transistor ITO...transparent pixel electrode g, d...conductive film Cadd...Holding capacitor element Cgs...parasitic capacitance Cpix…Liquid crystal capacity AOF…anodized film GTM…gate terminal DTM…Drain terminal TAB…TAB board TTM…Connection terminal

Claims (5)

[Claims] 1. A liquid crystal display substrate characterized in that extension lines of each signal line terminal of a group of signal line terminals converge to one point. 2. A liquid crystal display panel comprising a liquid crystal display substrate in which extension lines of respective signal line terminals of a group of signal line terminals converge to one point. 3. A liquid crystal display panel having a liquid crystal display substrate in which extension lines of respective signal line terminals of a group of signal line terminals converge to one point, and a video signal drive circuit for providing a video signal to the liquid crystal display panel; A liquid crystal display device comprising: a scanning circuit for providing a scanning signal to the liquid crystal display panel; a control circuit for providing information for the liquid crystal display panel to the video signal driving circuit; and the scanning circuit. . 4. Circuit elements of the video signal drive circuit and the scanning circuit are mounted on a circuit board, and an extension of each connection terminal of a group of connection terminals formed on the circuit board and connected to the group of signal line terminals. 4. The liquid crystal display device according to claim 3, wherein the lines converge to one point. 5. The liquid crystal display device according to claim 4, wherein the length of the connection terminal is shorter than the length of the signal line terminal.