JPH05341322A - Thin-film transistor substrate, liquid crystal display panel and liquid crystal display device - Google Patents

Abstract

PURPOSE:To prevent the generation of a cruciform line defect and to substantially prevent the generation of the short circuit between a scanning signal line and a video signal line. CONSTITUTION:The video signal line DL is branched to the first branch video signal line DL1 and the second branch video signal line DL2. The first branch video signal line DL1 intersects with the scanning signal line GL. The part of the second branch video signal line DL2 existing on a gate electrode GT faces a source electrode SD1 over nearly the entire length and is a drain electrode SD2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate, and more particularly to a thin film transistor substrate for an active matrix type liquid crystal display device using thin film transistors,
The present invention relates to a liquid crystal display panel and a liquid crystal display device.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device is provided with a non-linear element (switching element) corresponding to each of a plurality of pixel electrodes arranged in a matrix. Since the liquid crystal in each pixel is theoretically always driven (duty ratio 1.0), the active system has better contrast than the so-called simple matrix system, which employs the time-division driving system, and especially the color liquid crystal. It is becoming an indispensable technology for display devices. A typical example of the switching element is a thin film transistor (TFT).

FIG. 17 is a view showing a part of a thin film transistor substrate of a conventional active matrix type liquid crystal display device. In this thin film transistor substrate, the plurality of scanning signal lines GL and the plurality of video signal lines DL are provided at right angles, the transparent pixel electrode ITO1 is provided between the scanning signal lines GL and the video signal lines DL, and the scanning signal lines GL are provided. An i-type semiconductor layer AS is provided on the gate electrode GT connected to
The type semiconductor layer AS and the transparent pixel electrode ITO1 are connected by the source electrode SD1, and the video signal line DL is branched into a branch video signal line DL1 and a branch video signal line DL2 at a portion intersecting the scanning signal line GL. Branch video signal line DL2
Of the gate electrode GT, the i-type semiconductor layer AS, the source electrode SD1, the drain electrode SD2 and the like form a thin film transistor TFT. There is.

In such a thin film transistor substrate, when the scanning signal line GL and the branch video signal line DL1 are short-circuited, if the branch video signal line DL1 is cut at points a and b, a cross-shaped line defect occurs. Can be prevented, and when the scanning signal line GL and the branch video signal line DL2 are short-circuited, the branch video signal line DL2 is located at points c and d.
By cutting, it is possible to prevent the generation of cruciform line defects.

An active matrix type liquid crystal display device using a thin film transistor is, for example, "12.5 type active matrix type color liquid crystal display employing a redundant structure", Nikkei Electronics,
Pp. 193-210, Dec. 15, 1986, published by Nikkei McGraw-Hill, JP-A-2-85826, JP-A-3-50731.

[0006]

However, in such a thin film transistor substrate, since the scanning signal line GL and the video signal line DL intersect at two points, the scanning signal line GL is formed.
Since the intersecting area between the scanning signal line GL and the video signal line DL increases, a short circuit between the scanning signal line GL and the video signal line DL easily occurs.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to prevent the generation of cross-shaped line defects, and moreover, it is hard to cause a short circuit between the scanning signal line and the video signal line. An object is to provide a thin film transistor substrate, a liquid crystal display panel, and a liquid crystal display device.

[0008]

In order to achieve this object, according to the present invention, a plurality of scanning signal lines, video signal lines provided to intersect the scanning signal lines, and the scanning signal lines and the video are provided. In a thin film transistor substrate including a thin film transistor arranged at an intersection with a signal line, the video signal line is branched, the first branch video signal line is crossed with the scanning signal line, and the second branch video signal line is crossed. The portion located on the gate electrode is opposed to the source electrode over almost the entire length.

Further, a thin film transistor substrate having a plurality of scanning signal lines, a video signal line provided so as to intersect the scanning signal line, and a thin film transistor arranged at an intersection of the scanning signal line and the video signal line. In the liquid crystal display panel having, the video signal line is branched, the first branch video signal line is intersected with the scanning signal line, and the portion of the second branch video signal line located on the gate electrode is provided over substantially the entire length. Face the source electrode.

Further, a thin film transistor substrate having a plurality of scanning signal lines, a video signal line provided to intersect with the scanning signal line, and a thin film transistor arranged at an intersection of the scanning signal line and the video signal line. The video signal line is branched, the first branch video signal line intersects the scanning signal line, and the portion of the second branch video signal line located on the gate electrode is the source electrode over substantially the entire length. A liquid crystal display panel facing each other, a video signal drive circuit for giving a video signal to the liquid crystal display panel, a scanning circuit for giving a scanning signal to the liquid crystal display panel, the video signal drive circuit, and the scanning circuit And a control circuit for giving information for the liquid crystal display panel.

[0011]

[Function] This thin film transistor substrate, liquid crystal display panel,
In the liquid crystal display device, when the scanning signal line and the first and second branch video signal lines are short-circuited, if the first and second branch video signal lines are cut, a cross-shaped line defect occurs. Since the crossing area between the second branch video signal line and the scanning signal line is very small, the crossing area between the scanning signal line and the video signal line hardly increases. A short circuit between the signal line and the video signal line hardly occurs.

[0012]

【Example】

(Active Matrix Liquid Crystal Display Device) An embodiment in which the present invention is applied to a thin film transistor substrate and a liquid crystal display panel of an active matrix color liquid crystal display device will be described below. In the drawings described below, components having the same function are designated by the same reference numeral, and repeated description thereof will be omitted.

FIG. 2 shows an active system to which the present invention is applied.
FIG. 3 is a plan view showing one pixel of the matrix type color liquid crystal display device and its periphery, FIG. 3 is a sectional view taken along line 3-3 of FIG. 2, and FIG. 4 is a sectional view taken along line 4-4 of FIG. .. Further, FIG. 5 shows a plan view when a plurality of pixels shown in FIG. 2 are arranged.

(Pixel Arrangement) As shown in FIG. 2, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or drain signal lines). The signal line is arranged in an area intersecting with the vertical signal line DL (in an area surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1 and a storage capacitor element Cadd. The scanning signal lines GL extend in the column direction, and a plurality of scanning signal lines GL are arranged in the row direction. Video signal line DL
Extend in the row direction and are arranged in the column direction.

(Overall Structure of Display Section) As shown in FIG. 3, a thin film transistor TFT and a transparent pixel electrode ITO1 are provided on the lower transparent glass substrate SUB1 side based on the liquid crystal LC.
On the upper transparent glass substrate SUB2 side, a color filter FIL and a light-shielding black matrix pattern B are formed.
M is formed. The lower transparent glass substrate SUB1 has a thickness of, for example, about 1.1 mm. Further, a silicon oxide film SIO formed by dipping or the like is provided on both surfaces of the transparent glass substrates SUB1 and SUB2. Therefore, the transparent glass substrates SUB1 and SUB
Even if there are sharp scratches on the surface of No. 2, since the sharp scratches can be covered with the silicon oxide film SIO, the film quality of the scanning signal lines GL, the light shielding film BM, etc. deposited thereon can be kept uniform. ..

Although not shown, a sealing material is formed along the entire periphery of the transparent glass substrates SUB1 and SUB2 excluding the liquid crystal sealing port so as to seal the liquid crystal LC, and the sealing material is made of epoxy resin, for example. The common transparent pixel electrode ITO2 on the upper transparent glass substrate SUB2 side is connected to an external lead wire formed on the lower transparent glass substrate SUB1 side by a silver paste material at least at one place. The external lead-out wiring is a gate terminal GTM, which will be described later,
It is formed in the same manufacturing process as the drain terminal DTM.

The respective layers of the alignment films ORI1 and ORI2, the transparent pixel electrode ITO1 and the common transparent pixel electrode ITO2 are formed inside the sealing material. Polarizing plates POL1, P
The OL2 is formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively.
The liquid crystal LC is a lower alignment film ORI that sets the orientation of liquid crystal molecules.
1 and the upper orientation film ORI2, and is sealed by a sealing material. The lower alignment film ORI1 is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.

A light-shielding film BM and a color filter FI are formed on the inner surface (liquid crystal LC side) of the upper transparent glass substrate SUB2.
L, protective film PSV2, common transparent pixel electrode ITO2 (CO
M) and the upper alignment film ORI2 are sequentially stacked.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and then the lower transparent glass substrate SUB1.
And the upper transparent glass substrate SUB2 are overlapped with each other, and the liquid crystal LC is sealed between the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2.

(Thin Film Transistor TFT) The thin film transistor TFT operates so that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain becomes small, and when the bias is zero, the channel resistance becomes large.

The thin film transistor TFT of each pixel includes a gate electrode GT, a gate insulating film GI, an i type (intrinsic, intrinsic
c, Conductivity determining impurities are not doped) Amorphous S
i-type semiconductor layer AS made of i, pair of source electrodes SD
1 and has a drain electrode SD2. The source and drain are originally determined by the bias polarity between them,
In the circuit of this liquid crystal display device, the polarities are inverted during operation, so it should be understood that the source and drain are switched during operation. However, in the following explanation, one is the source for convenience,
The other is fixed and expressed as a drain.

(Gate Electrode GT) The gate electrode GT is shown in FIG.
As shown in (a plan view in which only the second conductive film g2 and the i-type semiconductor layer AS of FIG. 2 are drawn), it is formed in a shape protruding in the vertical direction (vertical direction in FIGS. 2 and 6) from the scanning signal line GL. Has been done. The gate electrode GT projects so as to extend beyond the active region of the thin film transistor TFT. In this embodiment, the gate electrode GT is a single-layer second conductive film g2.
Is formed by. The second conductive film g2 is, for example, an Al film formed by sputtering, and is formed with a film thickness of about 1000 to 5500Å. An Al anodic oxide film AOF is provided on the gate electrode GT.

As shown in FIGS. 2, 3 and 6, this gate electrode GT is formed larger than it so as to completely cover the i-type semiconductor layer AS (as viewed from below).
Therefore, when a backlight such as a fluorescent lamp is attached below the lower transparent glass substrate SUB1, this opaque A
The i-type semiconductor layer AS is not exposed to backlight light due to the shadow of the gate electrode GT made of l, and the conduction phenomenon due to light irradiation, that is, the off-characteristic deterioration of the thin film transistor TFT is less likely to occur. The original size of the gate electrode GT is the minimum required to extend between the source electrode SD1 and the drain electrode SD2 (the gate electrode GT and the source electrode S).
D1 has a width (including an alignment margin with the drain electrode SD2), and its depth length that determines the channel width W is a ratio of the distance (channel length) L between the source electrode SD1 and the drain electrode SD2, Ie mutual conductance
It is determined by the factor W / L that determines gm. Gate electrode GT in this liquid crystal display device
Of course is made larger than the original size described above.

(Scanning Signal Line GL) The scanning signal line GL is the second
It is composed of a conductive film g2. The second conductive film g2 of the scanning signal line GL is formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT, and is integrally formed. Further, an Al anodic oxide film AOF is also provided on the scanning signal line GL.

(Insulating Film GI) The insulating film GI is used as a gate insulating film of the thin film transistor TFT. Insulation film G
I is formed in the upper layer of the gate electrode GT and the scanning signal line GL. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is used, and 1200 to 2700Å
Film thickness (in this liquid crystal display device, a film thickness of about 2000 Å).

(I-type semiconductor layer AS) i-type semiconductor layer AS
Is used as a channel forming region of the thin film transistor TFT, as shown in FIG. The i-type semiconductor layer AS is formed of an amorphous Si film or a polycrystalline Si film and has a thickness of 200 to 22.
It is formed with a film thickness of 00Å (in this liquid crystal display device, a film thickness of about 2000Å).

The i-type semiconductor layer AS is continuously formed by the same plasma CVD apparatus and plasma in the same manner as the formation of the insulating film GI used as a gate insulating film made of Si ₃ N ₄ by changing the composition of the supply gas. It is formed without being exposed to the outside from the CVD device. Further, phosphorus (P) for ohmic contact is doped with 2.5% of N (+) type semiconductor layer d.
0 (FIG. 3) is similarly continuously formed with a film thickness of 200 to 500 Å (in this liquid crystal display device, a film thickness of about 300 Å). After that, the lower transparent glass substrate SUB1 is CV
It is taken out from the D device and is N (+) by the photo processing technology.
The type semiconductor layer d0 and the i-type semiconductor layer AS are patterned into independent islands as shown in FIGS. 2, 3 and 6.

As shown in FIGS. 2 and 6, the i-type semiconductor layer AS is also provided between both the intersections (crossover portions) of the scanning signal lines GL and the video signal lines DL. The i-type semiconductor layer AS at the intersection reduces the short circuit between the scanning signal line GL and the video signal line DL at the intersection.

(Transparent Pixel Electrode ITO1) Transparent Pixel Electrode I
TO1 constitutes one of the pixel electrodes of the liquid crystal display section.

The transparent pixel electrode ITO1 is composed of a first conductive film d1, and the first conductive film d1 is a transparent conductive film (Indium-Tin-Oxide I) formed by sputtering.
(TO: Nesa film), and is formed with a film thickness of 1000 to 2000Å (in this liquid crystal display device, a film thickness of about 1400Å).

(Video Signal Line DL) As shown in FIG. 1, the video signal line DL is branched into a first branch video signal line DL1 and a second branch video signal line DL2, and a first branch video signal is obtained. The signal line DL1 intersects with the scanning signal line GL, and the second
The portion of the branched video signal line DL2 located on the gate electrode GT faces the source electrode SD1 over almost the entire length and serves as the drain electrode SD2.

When the scanning signal line GL and the first branch video signal line DL1 are short-circuited, if the first branch video signal line DL1 is cut at the points a and b, a cross-shaped line defect occurs. Of the gate electrode G
When T and the drain electrode SD2 are short-circuited, by cutting the second branch video signal line DL2 at the points c and d, it is possible to prevent the generation of a cruciform line defect, and further, the second branch. Since the crossing area between the video signal line DL2 and the scanning signal line GL is very small, the crossing area between the scanning signal line GL and the video signal line DL hardly increases.
A short circuit between the scanning signal line GL and the video signal line DL is unlikely to occur.

(Source electrode SD1, drain electrode SD
2) The source electrode SD1 and the drain electrode SD2 of the thin film transistor TFT are, as shown in FIG. 2, FIG. 3 and FIG. 7 (a plan view showing only the first to third conductive films d1 to d3 of FIG. 2), i It is provided on the type semiconductor layer AS.

Each of the source electrode SD1 and the drain electrode SD2 is formed by sequentially stacking a second conductive film d2 and a third conductive film d3 from the lower layer side in contact with the N (+) type semiconductor layer d0. Second conductive film d2 of the source electrode SD1
The third conductive film d3 is formed in the same manufacturing process as the second conductive film d2 and the third conductive film d3 of the drain electrode SD2.

The second conductive film d2 is Cr formed by sputtering.
The film is formed with a film thickness of 500 to 1000 Å (in this liquid crystal display device, a film thickness of about 600 Å). If the Cr film is formed thick, the stress increases, so 200
It is formed within a range not exceeding the film thickness of about 0Å. Cr film is N
Good contact with the (+) type semiconductor layer d0. The Cr film constitutes a so-called barrier layer that prevents Al of the third conductive film d3 described later from diffusing into the N (+) type semiconductor layer d0.
As the second conductive film d2, a refractory metal (M
o, Ti, Ta, W) film, refractory metal silicide (Mo
A Si ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used.

The third conductive film d3 is formed by sputtering Al and has a thickness of 3000 to 5000 Å (in this liquid crystal display device,
The film thickness is about 4000 Å). The Al film has less stress than the Cr film, can be formed to have a thick film thickness, and is configured to reduce the resistance values of the source electrode SD1, the drain electrode SD2, and the video signal line DL. As the third conductive film d3, an Al film containing Si or Cu as an additive may be used instead of the pure Al film.

After patterning the second conductive film d2 and the third conductive film d3 with the same mask pattern, an N (+) type film is formed by using the same mask or by using the second conductive film d2 and the third conductive film d3 as a mask. The semiconductor layer d0 is removed. That is,
The N (+) type semiconductor layer d0 remaining on the i type semiconductor layer AS
The portions other than the second conductive film d2 and the third conductive film d3 are removed by self-alignment. At this time, the N (+) type semiconductor layer d
Since 0 is etched so that the entire thickness thereof is removed, the surface portion of the i-type semiconductor layer AS is also slightly etched, but the degree may be controlled by the etching time.

The source electrode SD1 is the transparent pixel electrode ITO1.
It is connected to the. The source electrode SD1 has the i-type semiconductor layer AS step (thickness of the second conductive film g2, thickness of the anodic oxide film AOF, thickness of the i-type semiconductor layer AS, and thickness of the N (+)-type semiconductor layer d0. It is configured along a step corresponding to the added film thickness). Specifically, the source electrode SD1 is the second conductive film d2 formed along the step of the i-type semiconductor layer AS.
And the third conductive film d formed on the second conductive film d2.
3 and 3. The third conductive film d3 of the source electrode SD1 cannot be formed thick due to the increased stress of the Cr film of the second conductive film d2, and cannot overcome the step shape of the i-type semiconductor layer AS. Is configured for. That is, the step coverage is improved by forming the third conductive film d3 thick. Since the third conductive film d3 can be formed thick, it greatly contributes to the reduction of the resistance value of the source electrode SD1 (the same applies to the drain electrode SD2 and the video signal line DL).

(Protective film PSV1) Thin film transistor TF
A protective film PSV1 is provided on the T and the transparent pixel electrode ITO1. The protective film PSV1 is formed mainly for protecting the thin film transistor TFT from moisture and the like,
Use one with high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and has a thickness of 1 μm.
It is formed with a film thickness of about m.

(Light-shielding film BM) Upper transparent glass substrate SUB
A light-shielding film BM is provided on the second side so that external light (light from above in FIG. 3) does not enter the i-type semiconductor layer AS used as a channel formation region.
The pattern is as shown by the hatching. Note that FIG. 8 shows the first conductive film d made of the ITO film in FIG.
FIG. 1 is a plan view illustrating only a color filter FIL and a light shielding film BM. The light-shielding film BM is formed of, for example, an Al film or a Cr film having a high light-shielding property. In this liquid crystal display device, the Cr film is formed by sputtering to have a film thickness of about 1300 Å.

Therefore, i of the thin film transistor TFT
The type semiconductor layer AS is sandwiched by the upper and lower light-shielding films BM and the large gate electrode GT, and that portion is not exposed to external natural light or backlight light. The light-shielding film BM is formed around the pixel as shown by the hatched portion in FIG. 8, that is, the light-shielding film BM is formed in a grid shape (black matrix), and the effective display area of one pixel is partitioned by this grid. .. Therefore, the contour of each pixel is made clear by the light shielding film BM, and the contrast is improved. That is, the light blocking film BM has two functions of blocking the i-type semiconductor layer AS and serving as a black matrix.

A portion facing the edge portion of the transparent pixel electrode ITO1 on the base side in the rubbing direction (the lower right portion in FIG. 2).
Since the light is shielded by the light shielding film BM, even if a domain is generated in the above portion, the domain cannot be seen, so that the display characteristics are not deteriorated.

The backlight may be attached to the upper transparent glass substrate SUB2 side and the lower transparent glass substrate SUB1 may be the observation side (externally exposed side).

(Color Filter FIL) The color filter FIL is constructed by coloring a dye base material made of a resin material such as acrylic resin with a dye. Color filter F
ILs are formed in stripes at positions facing the pixels (FIG. 9) and are dyed separately (FIG. 9 shows only the first conductive film d1, the light shielding film BM and the color filter FIL in FIG. B, R, G color filters FI
L is 45 °, 135 °, and has a cross hatch). As shown in FIGS. 8 and 9, the color filter FIL is formed to have a large size so as to cover all of the transparent pixel electrode ITO1, and the light-shielding film BM overlaps the edge portions of the color filter FIL and the transparent pixel electrode ITO1. Is formed inside the peripheral edge of the.

The color filter FIL can be formed as follows. First, a dyeing base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyeing base material other than the red filter forming region is removed by a photolithography technique. After that, the dyed substrate is dyed with a red dye and a fixing process is performed to form a red filter R. Next, the green filter G and the blue filter B are sequentially formed by performing the same process.

(Protective Film PSV2) In the protective film PSV2, the liquid crystal L is a dye in which the color filter FIL is dyed in different colors.
It is provided to prevent leakage to C. The protective film PSV2 is formed of a transparent resin material such as acrylic resin or epoxy resin.

(Common Transparent Pixel Electrode ITO2) The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is the pixel electrode ITO1. And the common transparent pixel electrode ITO2 change in response to a potential difference (electric field). A common voltage Vcom is applied to the common transparent pixel electrode ITO2. The common voltage Vcom is an intermediate potential between the low level drive voltage Vdmin and the high level drive voltage Vdmax applied to the video signal line DL.

(Gate Terminal GTM) FIGS. 16A and 16B are views showing a connection structure from the scanning signal line GL of the display matrix to the gate terminal GTM which is an external connection terminal thereof. FIG. 16A is a plane and FIG. The cross section in the BB cutting line of (A) is shown. The figure shows the vicinity of the left end of the lower transparent glass substrate SUB1 based on the matrix of FIG.

AO is a mask pattern for photographic processing, in other words, a photoresist pattern for selective anodic oxidation. Therefore, this photoresist is removed after anodic oxidation, and although the mask pattern AO shown in the figure does not remain as a finished product, the anodic oxide film AOF is selectively formed on the gate line GL as shown in the cross-sectional view. The trail remains. In the plan view, with respect to the photoresist boundary line AO, the left side is a region covered with the resist and not anodized, and the right side is a region exposed from the resist and anodized.
The surface of the anodized second conductive film g2 is made of the oxide Al.
_{A 2} O ₃ film, that is, an anodized film AOF is formed, and the volume of the conductive portion below is reduced. Of course, the anodic oxidation is performed by setting an appropriate time and voltage so that the conductive portion remains. The mask pattern AO does not intersect the scanning signal line GL with a single straight line, but is bent in a crank shape and intersects with it. For this reason, even if the second conductive film g2 is melted by the anodic oxidation voltage because the peeling starts from the photoresist portion that intersects the step portion of the scanning signal line GL, the melting progresses along the end surface of the photoresist film. The fusing of the second conductive film g2 stops at the crank-shaped portion. Therefore, it is possible to prevent the scanning signal line GL from being broken during anodization.

In this embodiment, the photoresist pattern on the second conductive film g2 has a crank shape, but the shape is not limited to this. In short, when peeling occurs in the hot pattern and progresses, it may be formed of a rectangle, a triangle, a circle, a trapezoid or the like alone or in combination so as to stop the peeling.

The second conductive film g2 in FIG. 9A is hatched for easy understanding, but the region not anodized is patterned in a comb shape. This is the second conductive film g2
If the width is large, whiskers will be generated on the surface. Therefore, by narrowing the width of each one and bundling them in parallel, the probability of wire breakage and conductivity can be prevented while preventing whiskers from occurring. The aim is to minimize the sacrifice of. Therefore, in this liquid crystal display device, the portion corresponding to the root of the comb is also displaced along the mask pattern AO.

The gate terminal GTM is a silicon oxide film SIO.
And a first conductive film g1 made of a Cr film having good adhesiveness, and a transparent first conductive layer d1 which protects the surface of the first conductive film g1 and has the same level (same layer, simultaneous formation) as the transparent pixel electrode ITO1. .. The second conductive film d2 and the third conductive film d3 formed on the gate insulating film GI and the side surface thereof are
It remains as a result of covering the region with the photoresist so that the second conductive film g2 and the first conductive film g1 are not etched together due to pinholes or the like during the etching of the third conductive film d3 and the second conductive film d2. It is a thing. In addition, the first conductive film d1 which extends over the gate insulating film GI and extends rightward is one in which the same measures are taken more thoroughly.

In the plan view, the gate insulating film GI is formed on the right side of the boundary line and the protective film PSV1 is formed on the right side of the boundary line, and the gate terminal G located at the left end is formed.
The TMs are exposed from them so that they can make electrical contact with external circuits. In the figure, only one pair of the scanning signal line GL and the gate terminal GTM is shown, but in reality, a plurality of such pairs are arranged vertically in the figure, and the left end of the gate terminal GTM in the figure is the manufacturing process. , Extended beyond the cutting region of the lower transparent glass substrate SUB1 and short-circuited. Such a short circuit in the manufacturing process is due to power supply during anodization,
This helps prevent electrostatic damage during rubbing of the alignment film ORI1.

(Drain Terminal DTM) FIG. 10 shows a drain terminal DTM which is an external connection terminal of the video signal line DL.
Is a diagram showing the connection up to, (A) shows the plane,
(B) shows a cross section taken along the line BB of (A). This figure shows the upper and lower ends of the lower transparent glass substrate SUB1 based on the matrix of FIG. 5, and the direction is changed for convenience, but the left end direction is the lower transparent glass substrate SU.
It corresponds to the upper end or the lower end of B1.

TSTd is an inspection terminal, and inspection terminal TS
No external circuit is connected to Td. The inspection terminals TSTd and the drain terminals DTM are alternately arranged in a zigzag pattern in the vertical direction, and the inspection terminals TSTd terminate without reaching the end portion of the lower transparent glass substrate SUB1 as shown in the drawing. DTM is lower transparent glass substrate SU
It is further extended beyond the cutting line of B1 and all of them are short-circuited to each other to prevent electrostatic damage during the manufacturing process. In the drawing, the drain terminal DTM is connected to the opposite side of the matrix of the video signal lines DL having the inspection terminals TSTd, and conversely the inspection is performed to the opposite side of the matrix of the video signal lines DL having the drain terminals DTM. The terminal TSTd is connected.

The drain terminal DTM is formed of two layers of the first conductive film g1 made of a Cr film and the first conductive film d1 made of an ITO film for the same reason as the gate terminal GTM described above. The removed portion is connected to the video signal line DL. The semiconductor layer AS formed on the end portion of the gate insulating film GI is for etching the edge of the gate insulating film GI in a tapered shape. Drain terminal D
Protective film PSV on TM to connect to external circuit
Of course, 1 has been removed. AO is the above-mentioned anodizing mask, and its boundary line is formed so as to largely surround the entire matrix.
The left side from the boundary line of O is covered with a mask, but since the second conductive film g2 does not exist in the portion not covered in this figure, this pattern is not directly related.

(Structure of Storage Capacitance Element Cadd) The transparent pixel electrode ITO1 is formed so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TFT. In this superposition, as is clear from FIG. 4, the transparent pixel electrode ITO1 is used as one electrode PL2 and the adjacent scanning signal line GL is used as the other electrode PL.
A holding capacitance element (electrostatic capacitance element) Cadd which is 1 is configured. The dielectric film of the storage capacitor Cadd is an insulating film G used as a gate insulating film of the thin film transistor TFT.
I and the anodic oxide film AOF.

As is apparent from FIG. 6, the storage capacitor element Cadd is formed in a portion where the width of the second conductive film g2 of the scanning signal line GL is widened. The second conductive film g2 at the portion intersecting the video signal line DL is thinned in order to reduce the probability of short circuit with the video signal line DL. Storage capacitor C
In the step portion of the electrode PL1 of add, the transparent pixel electrode ITO
Even if 1 is broken, the defect is compensated by the island region formed by the second conductive film d2 and the third conductive film d3 formed so as to cross the step. This island region is made as small as possible so as not to reduce the aperture ratio.

(Equivalent Circuit of Entire Display Device) FIG. 11 shows a wiring diagram of an equivalent circuit of the display matrix portion and its peripheral circuits.
Although the figure is a circuit diagram, it is drawn corresponding to the actual geometrical arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X means a video signal line DL, and subscripts G, B and R are added corresponding to green, blue and red pixels, respectively. Y represents the scanning signal line GL, and subscripts 1, 2, 3, ..., End are added according to the order of scanning timing.

The video signal lines X (subscripts omitted) are alternately connected to the upper (or odd) video signal drive circuit He and the lower (or even) video signal drive circuit Ho.

The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V.

The SUP is a TFT liquid crystal display device for displaying information for a CRT (cathode ray tube) from a power supply circuit or a host (upper processing unit) for obtaining a stabilized voltage source obtained by dividing a plurality of voltages from one voltage source. It is a circuit including a circuit for exchanging information for use.

(Equivalent Circuit of Retaining Capacitance Element Cadd and Its Operation) FIG. 12 shows an equivalent circuit of the pixel shown in FIG. In FIG. 12, Cgs is a parasitic capacitance formed between the gate electrode GT and the source electrode SD1 of the thin film transistor TFT. The dielectric film having the parasitic capacitance Cgs is the insulating film GI and the anodic oxide film AOF. Cpix is a transparent pixel electrode ITO
A liquid crystal capacitor formed between 1 (PIX) and the common transparent pixel electrode ITO2 (COM). The dielectric film of the liquid crystal capacitance Cpix is the liquid crystal LC, the protective film PSV1 and the alignment film ORI.
1, ORI2. Vlc is the midpoint potential.

The storage capacitor element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the thin film transistor TFT switches. This can be expressed by the following equation.

ΔVlc = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg Here, ΔVlc represents a change amount of the midpoint potential due to ΔVg. This variation ΔVlc causes a direct current component applied to the liquid crystal LC, but the value can be reduced as the holding capacitance Cadd is increased. In addition, the storage capacitor element C
add also has the effect of lengthening the discharge time, and accumulates image information for a long time after the thin film transistor TFT is turned off. The reduction of the DC component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.

As described above, since the gate electrode GT is made large enough to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 is increased, and thus the parasitic capacitance Cgs is increased. The reverse effect is that the midpoint potential Vlc is easily affected by the gate (scanning) signal Vg. However, the storage capacitor Cadd
By providing the above, this demerit can be eliminated.

The storage capacitance of the storage capacitance element Cadd is 4 to 8 times (4.C
pix <Cadd <8 · Cpix), 8 to 3 for parasitic capacitance Cgs
Set to a value about twice (8 · Cgs <Cadd <32 · Cgs).

(Method of Connecting Storage Capacitance Element Cadd Electrode Wire)
The first stage scanning signal line GL (Y ₀ ) used only as the storage capacitor electrode line is connected to the common transparent pixel electrode ITO2 (Vcom) as shown in FIG. Since the common transparent pixel electrode ITO2 of the upper transparent glass substrate SUB2 is connected to the external lead wiring of the lower transparent glass substrate SUB1 by the silver paste material in the peripheral portion of the liquid crystal display device, as described above, the scanning signal line of the first stage. GL (Y ₀ ) may be connected to the external lead wiring on the lower transparent glass substrate SUB1 side. Alternatively, the storage capacitor electrode line Y ₀ in the first stage is connected to the scanning signal line Yend in the final stage and is connected to a DC potential point (AC ground point) other than Vcom, or one extra scanning pulse Y ₀ from the vertical scanning circuit V. You may connect to receive.

(Manufacturing Method) Next, a manufacturing method of the lower transparent glass substrate SUB1 side of the above-mentioned liquid crystal display device will be described with reference to FIGS. In the figure, the letters in the center are abbreviations of process names, the left side shows the pixel portion shown in FIG. 3, and the right side shows the processing flow as seen in the sectional shape near the gate terminal shown in FIG. Except for the step D, steps A to I are divided corresponding to each photographic process, and all the cross-sectional views of each process show the stage where the processing after the photographic process is completed and the photoresist is removed. In this description, the photographic processing means a series of operations from the application of the photoresist to the selective exposure using the mask to the development thereof, and the repetitive description will be omitted. Description will be given below according to the divided steps.

Step A (FIG. 13) After a silicon oxide film SIO is formed on both surfaces of a lower transparent glass substrate SUB1 made of 7059 glass (trade name) by dip processing, baking is performed at 500 ° C. for 60 minutes. The film thickness is about 1000 on the lower transparent glass substrate SUB1.
The first conductive film g1 made of a Cr film of Å is provided by sputtering, and after the photographic processing, the first conductive film g1 is selectively etched with a cerium ammonium nitrate solution as an etching solution. Thereby, the gate terminal GTM, the drain terminal DTM, the anodized bus line (not shown) connecting the gate terminal GTM, the bus line (not shown) short-circuiting the drain terminal DTM, and the anode connected to the anodized bus line. Form an oxide pad (not shown).

Step B (FIG. 13) Al-Ta having a film thickness of about 3000Å (the addition amount of Ta is 1.
The second conductive film g2 composed of 5 atomic%) is provided by sputtering. After the photographic processing, the second conductive film g2 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid and glacial acetic acid.

Step C (FIG. 13) After photographic processing (after forming the above-described anodic oxidation mask AO), 3
The lower transparent glass substrate SUB1 is dipped in an anodizing solution consisting of a solution in which the pH of tartaric acid is adjusted to pH 7 ± 0.5 with ammonia and diluted 1: 9 with ethylene glycol solution, and the anodizing current density is 0.5 mA. / Cm ² (constant current anodic oxidation). Next, a predetermined Al ₂ O ₃
Anodization is performed until the anodic oxidation voltage 144 V required to obtain the film thickness is reached. After that, it is desirable to hold this state for several minutes to several tens of minutes (constant voltage anodization). This is important in obtaining a uniform anodic oxide film AOF. As a result, the second conductive film g2 is anodized, and an anodized film AOF having a film thickness of 2000 Å is formed on the scanning signal line GL, the gate electrode GT and the electrode PL1.

Step D (FIG. 14) Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a silicon nitride film having a film thickness of 2000Å, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus to form the film. After forming an i-type amorphous Si film having a thickness of 2000 Å, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to form an N (+) type amorphous Si film having a film thickness of 300 Å.

Step E (FIG. 14) After photoprocessing, SF ₆ and CC are used as dry etching gas.
Use l ₄ N (+) type amorphous Si film, i-type amorphous Si
The island of the i-type semiconductor layer AS is formed by selectively etching the film.

Step F (FIG. 14) After photoprocessing, the silicon nitride film is selectively etched by using SF ₆ as a dry etching gas.

Step G (FIG. 15) A first conductive film d1 made of an ITO film having a film thickness of 1000 Å is provided by sputtering. After the photographic processing, the first conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etching solution, whereby the uppermost layers of the gate terminal GTM and the drain terminal DTM and the transparent pixel electrode ITO1.
To form.

Step H (FIG. 15) A second conductive film d2 made of a Cr film having a film thickness of 1000Å is provided by sputtering, and A having a film thickness of 4000Å is provided.
A third conductive film d3 made of 1-Ta (the added amount of Ta is 2 atomic%) is provided by sputtering. After the photographic processing, the third conductive film d3 is etched with the same liquid as in the process B,
The conductive film d2 is etched with the same liquid as in the process A to form the video signal line DL, the source electrode SD1 and the drain electrode SD2. Then, dry etching equipment is used for CCl ₄ , S
By introducing F ₆ and etching the N (+) type amorphous Si film, the N (+) type semiconductor layer d0 between the source and the drain is selectively removed.

Step I (FIG. 15) Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to form a silicon nitride film having a film thickness of 1 μm. After photo processing, SF _{6 is used} as a dry etching gas.
The protective film PSV1 is formed by selectively etching the silicon nitride film by a photo-etching technique using.

(Application Range) The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited to the embodiments and does not depart from the gist of the invention. Needless to say, various changes can be made in.

For example, in the above-mentioned embodiments, the thin film transistor substrate of the liquid crystal display device, which is expected to have the greatest mass production effect, has been described. Can also be applied to. Further, although the anodized film AOF and the insulating film GI are used as the gate insulating film in the above-described embodiments, only the anodized film AOF may be used as the gate insulating film. Further, in the above-mentioned embodiment, the silicon nitride film is used as the insulating film GI,
A silicon oxide film may be used. Further, in the above-mentioned embodiment, the thickness of the anodic oxide film AOF is 2000 Å, but a maximum voltage of about 25 V is applied between the gate electrode GT and the source electrode SD1 and the drain electrode SD2. The film thickness of the oxide film AOF must be 500 Å or more. Further, in the above-described embodiment, the pixels are arranged in rows, but they may be arranged with a half pitch shift.
Further, although the holding capacitor element Cadd is provided in the above-described embodiment, the holding capacitor element may not be provided. In addition, although the Cr film is used as the first conductive film g1 in the above-described embodiment, a Ta film may be used.

[0082]

As described above, in the thin film transistor substrate, the liquid crystal display panel, and the liquid crystal display device according to the present invention, it is possible to prevent the generation of cross-shaped line defects, and moreover, the scanning signal line and the image. Since the area of intersection with the signal line hardly increases, a short circuit between the scanning signal line and the video signal line hardly occurs. As described above, the effect of the present invention is remarkable.

[Brief description of drawings]

FIG. 1 is a plan view showing only conductive films g2, d2, and d3 of the pixel shown in FIG.

FIG. 2 is a main-portion plan view showing one pixel and its periphery of a liquid crystal display portion of an active matrix type color liquid crystal display device to which the present invention is applied.

FIG. 3 is a cross-sectional view showing one pixel and its periphery taken along the line 3-3 in FIG.

FIG. 4 is a storage capacitor element Cad taken along section line 4-4 of FIG.
It is sectional drawing of d.

5 is a plan view of a main part of a liquid crystal display unit in which a plurality of pixels shown in FIG. 2 are arranged.

6 is a conductive film g2, i-type semiconductor layer A of the pixel shown in FIG.
It is a top view which drew only S.

7 is a plan view illustrating only conductive films d1, d2, and d3 of the pixel shown in FIG.

8 is a plan view illustrating only a pixel electrode layer, a light shielding film, and a color filter layer of the pixel shown in FIG.

FIG. 9 is a plan view of a principal part illustrating only a pixel electrode layer, a light shielding film, and a color filter layer of the pixel array shown in FIG.

FIG. 10 is a plan view and a cross-sectional view showing the vicinity of a connection between a drain terminal DTM and a video signal line DL.

FIG. 11 is an equivalent circuit diagram showing a liquid crystal display unit of an active matrix type color liquid crystal display device.

FIG. 12 is an equivalent circuit diagram of the pixel shown in FIG.

FIG. 13: Processes A to C on the lower transparent glass substrate SUB1 side
6 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing the manufacturing process of FIG.

FIG. 14: Processes D to F on the lower transparent glass substrate SUB1 side
6 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing the manufacturing process of FIG.

FIG. 15: Processes G to I on the lower transparent glass substrate SUB1 side
6 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing the manufacturing process of FIG.

FIG. 16 is a plan view and a cross-sectional view showing the vicinity of a connecting portion between a gate terminal GTM and a scanning signal line GL.

FIG. 17 is a plan view of relevant parts of a liquid crystal display section of a conventional liquid crystal display device.

[Explanation of symbols]

SUB ... Transparent glass substrate, GL ... Scan signal line, DL ... Video signal line GI ... Insulating film, GT ... Gate electrode, AS ... i-type semiconductor layer SD ... Source electrode or drain electrode, PSV ... Protective film, BM ... Light-shielding film LC ... Liquid crystal, TFT ... Thin film transistor, ITO ... Transparent pixel electrode g, d ... Conductive film, Cadd ... Storage capacitor element, AOF ... Anodized film AO ... Anodized mask, GTM ... Gate terminal, DTM ...
Drain terminal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/784

Claims (3)

[Claims] 1. A thin film transistor substrate comprising a plurality of scanning signal lines, a video signal line provided so as to intersect the scanning signal line, and a thin film transistor arranged at an intersection of the scanning signal line and the video signal line. , The video signal line is branched, the first branch video signal line is intersected with the scanning signal line, and the portion of the second branch video signal line located on the gate electrode is opposed to the source electrode over substantially the entire length. A thin film transistor substrate characterized by the above. 2. A thin film transistor substrate comprising a plurality of scanning signal lines, a video signal line provided so as to intersect the scanning signal line, and a thin film transistor arranged at an intersection of the scanning signal line and the video signal line. In the liquid crystal display panel having, the video signal line is branched, the first branch video signal line is intersected with the scanning signal line, and the portion of the second branch video signal line located on the gate electrode is provided over substantially the entire length. A liquid crystal display panel characterized by being opposed to a source electrode. 3. A thin film transistor substrate comprising a plurality of scanning signal lines, a video signal line provided so as to intersect the scanning signal line, and a thin film transistor arranged at an intersection of the scanning signal line and the video signal line. The video signal line is branched, the first branch video signal line intersects the scanning signal line, and the portion of the second branch video signal line located on the gate electrode is the source electrode over substantially the entire length. A liquid crystal display panel facing each other, a video signal drive circuit for giving a video signal to the liquid crystal display panel, a scanning circuit for giving a scanning signal to the liquid crystal display panel, the video signal drive circuit, and the scanning circuit And a control circuit for giving information for the liquid crystal display panel to the liquid crystal display device.