JPH06342809A - Method of manufacturing liquid crystal display substrate - Google Patents

Abstract

PURPOSE:To prevent wire disconnection, shortcircuit or point defect caused by flakes or foreign substances in a finished TFT by washing a semiconductor layer with a washing liquid containing an organic alkali after a semiconductor layer has been formed. CONSTITUTION:After an oxide silicon film SIO is provided on both sides of a lower transparent glass substrate SUB1, a first conductivity film g1 made of chrome is provided on it. The first conductivity film g1 is selectively etched to form a gate terminal GTM and a drain terminal. Then, a second conductivity film g2 made of Aluminum-Palladium is provided. The second conductivity film g2 is anode-oxidized to provide an anode oxide film AOF on a scanning signal line GL. Hydrogen gas is introduced into a plasma CVD unit to provide an N(+)-type amorphous silicon film. Then, the N(+)-type amorphous layer is washed with organic alkali liquid. Thus, it is possible to remove flakes or foreign substances adhering to the surface of the semiconductor layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal display substrate, and more particularly to a method for manufacturing a liquid crystal display substrate which is a so-called active matrix type.

[0002]

2. Description of the Related Art A so-called active matrix type liquid crystal display substrate is provided with a non-linear element (switching element) corresponding to each of a plurality of matrix-shaped pixel electrodes. Since the liquid crystal in each pixel is theoretically always driven (duty ratio 1.0), the active system has better contrast than the so-called simple matrix system, which employs the time-division driving system. It is becoming an indispensable technology for display boards. A typical example of the switching element is a thin film transistor (TFT).

A thin film transistor (TFT) having such a structure has a large amount of so-called flakes or foreign substances attached to its surface after a semiconductor layer made of a-Si forming the film is formed, which is a cause. It was often the case that disconnection, short circuit, point defect, etc. occurred in the completed TFT.

Therefore, conventionally, after the semiconductor layer is formed, the flakes or foreign matters are removed by ultrasonic cleaning with pure water.

Incidentally, such a thin film transistor (TF
An active matrix type liquid crystal display substrate using T) is disclosed in, for example, Japanese Patent Application Laid-Open No. 63-309921, "12.5 type active matrix type color liquid crystal display adopting redundant structure", Nikkei Electronics, page 193. ~ 210, December 15, 1986
Known by Nikkei McGraw-Hill, Inc.

[0006]

However, it has been pointed out that even if the semiconductor layer is ultrasonically cleaned with pure water, defects such as disconnection, short circuit and point defect still occur in the completed TFT. Came to

This indicates that the flakes or foreign substances attached to the semiconductor layer are not yet sufficiently removed, and that the conventional cleaning method is not complete.

Therefore, the present invention has been made under such circumstances, and an object of the present invention is to provide a TFT, which has been completely manufactured, with a disconnection, a short circuit, or a break caused by flakes or foreign matters. It is an object of the present invention to provide a method for manufacturing a liquid crystal display substrate capable of completely and reliably preventing point defects and the like.

[0009]

In order to achieve such an object, the present invention basically provides a method for manufacturing a liquid crystal display substrate including a TFT having a-Si as a semiconductor layer, the semiconductor layer being used. After forming, the semiconductor layer is washed with a washing liquid containing an organic alkali.

[0010]

According to the method of manufacturing a liquid crystal display substrate having such a structure, the semiconductor layer washed with the washing liquid is in the same state as when its surface is light-etched.

Unlike the inorganic alkali, the organic alkali does not contain Na (+) ions, and therefore has an advantage that it does not cause a harmful effect due to this ionic substance.

For this reason, so-called flakes or foreign substances adhering to the surface of the semiconductor layer can be removed almost completely and reliably.

This makes it possible to completely and reliably prevent a disconnection, a short circuit, a point defect or the like caused by the flakes or the foreign matter in the manufactured TFT.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below with reference to embodiments in which the present invention is applied to an active matrix type color liquid crystal display substrate.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 2 shows an active system to which the present invention is applied.
FIG. 4 is a plan view showing one pixel of the matrix type color liquid crystal display substrate and its periphery, FIG. 3 is a cross sectional view taken along the line 3-3 of FIG. 2 and a cross section near the seal portion of the display panel, and FIG. 4 is a cross-sectional view taken along line -4. Further, FIG. 7 (plan view of a main part) shows a plan view when a plurality of pixels shown in FIG. 2 are arranged.

(Pixel Arrangement) As shown in FIG. 2, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or drain signal lines). The signal line is arranged in an area intersecting with the vertical signal line DL (in an area surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1 and a storage capacitor element Cadd. The scanning signal lines GL extend in the column direction and are arranged in the row direction. Video signal line D
L extends in the row direction and a plurality of L's are arranged in the column direction.

(Overall Structure of Display Section) As shown in FIG. 3, a thin film transistor TFT and a transparent pixel electrode ITO1 are provided on the lower transparent glass substrate SUB1 side based on the liquid crystal LC.
And a color filter FIL and a light shielding film BM forming a light shielding black matrix pattern are formed on the upper transparent glass substrate SUB2 side. The lower transparent glass substrate SUB1 has a thickness of about 1.1 mm, for example. In addition, the transparent glass substrates SUB1 and SUB2
A silicon oxide film SIO formed by dipping or the like is provided on both surfaces of the. Therefore, even if there are sharp scratches on the surfaces of the transparent glass substrates SUB1 and SUB2, the sharp scratches can be covered with the silicon oxide film SIO, so that the scanning signal lines GL and the color filters FIL are effectively prevented from being damaged. Can be prevented.

The central portion of FIG. 3 shows a cross section of one pixel portion, but the left side shows the cross section of the left edge portion of the transparent glass substrates SUB1 and SUB2 where the external lead wiring exists, and the right side is transparent. The cross section of the right edge portion of the glass substrates SUB1 and SUB2 where the external lead-out wiring does not exist is shown.

Sealing materials Sl shown on the left side and the right side of FIG. 3 are configured to seal the liquid crystal LC, and a transparent glass substrate SUB1 excluding a liquid crystal sealing port (not shown),
It is formed along the entire periphery of the edge of SUB2. The seal material SL is formed of, for example, an epoxy resin.

The common transparent pixel electrode ITO2 on the upper transparent glass substrate SUB2 side is connected to the external lead wiring formed on the lower transparent glass substrate SUB1 side by the silver paste material SIL at at least one location. The external lead-out wiring is formed in the same manufacturing process as the gate electrode GT, the source electrode SD1 and the drain electrode SD2.

Orientation films ORI1 and ORI2, transparent pixel electrode ITO1, common transparent pixel electrode ITO2, protective film PSV
The respective layers of 1, PSV2, and the insulating film GI are formed inside the sealing material SL. The polarizing plates POL1 and POL2 are formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively.

The liquid crystal LC is enclosed between the lower alignment films ORI1 and ORI2 that set the orientation of the liquid crystal molecules, and is sealed by the seal portion SL.

The lower alignment film ORI1 is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.

A light-shielding film BM and a color filter FI are formed on the inner surface (liquid crystal LC side) of the upper transparent glass substrate SUB2.
L, protective film PSV2, common transparent pixel electrode ITO2 (CO
M) and the upper alignment film ORI2 are sequentially stacked.

This liquid crystal display substrate is a lower transparent glass substrate S.
Layers on the UB1 side and the upper transparent glass substrate SUB2 side are separately formed, and then the upper and lower transparent glass substrates SUB are formed.
1 and SUB2 are superposed on each other, and a liquid crystal LC is sealed between them to assemble.

(Thin Film Transistor TFT) When a positive bias is applied to the gate electrode GT of the thin film transistor,
When the channel resistance between the source and the drain becomes small and the bias becomes zero, the channel resistance operates so as to become large.

The thin film transistor TFT of each pixel is divided into two (plural) in the pixel, and is composed of thin film transistors (divided thin film transistors) TFT1 and TFT2. Each of the thin film transistors TFT1 and TFT2 has substantially the same size (channel length and width are the same). Each of the divided thin film transistors TFT1 and TFT2 mainly has a gate electrode G.
T, gate insulating film GI, i-type (intrinsic, intrinsic
c, an i-type semiconductor layer AS made of amorphous silicon (Si) which is not doped with conductivity determining impurities, a pair of source electrode SD1 and drain electrode SD2.
It should be understood that the source and drain are originally determined by the bias polarity between them, and the polarity is reversed during operation in the circuit of this liquid crystal display substrate, so it should be understood that the source and drain are switched during operation. However, also in the following description, for convenience, one is fixed as the source and the other is fixed as the drain.

(Gate Electrode GT) The gate electrode GT is shown in FIG.
As shown in detail in (a plan view illustrating only the second conductive film g2 and the i-type semiconductor layer AS in FIG. 2), a shape protruding in the vertical direction (upward in FIGS. 2 and 8) from the scanning signal line GL. (It is branched into a T-shape). The gate electrode GT is a thin film transistor TFT1, T
It is configured to project to the respective formation regions of the FT2. The gate electrodes GT of the thin film transistors TFT1 and TFT2 are integrally formed (as a common gate electrode) and are formed continuously with the scanning signal line GL. The gate electrode GT is composed of a single-layer second conductive film g2. The second conductive film g2 is, for example, an aluminum film formed by sputtering, and is formed with a film thickness of about 1000 to 5500Å. An aluminum anodic oxide film AOF is provided on the gate electrode GT.

As shown in FIGS. 2, 3 and 8, the gate electrode GT is formed to be larger than the i-type semiconductor layer AS (when viewed from below).
Therefore, when the backlight BL such as a fluorescent lamp is attached below the lower transparent glass substrate SUB1, the gate electrode GT made of opaque aluminum becomes a shadow,
The i-type semiconductor layer AS is not exposed to the backlight light, so that the conduction phenomenon due to the light illumination, that is, the deterioration of the off characteristics of the thin film transistor TFT is less likely to occur. The original size of the gate electrode GT is the source electrode SD1 and the drain electrode SD.
2 has a minimum width (including a margin for combining the gate electrode GT with the source electrode SD1 and the drain electrode SD2) so as to extend over the source electrode SD1, and the depth length that determines the channel width W is the source electrode SD1. It is determined by the ratio of the distance (channel length) L between the drain electrode SD2 and the drain electrode SD2, that is, the factor W / L that determines the mutual conductance gm.

The gate electrode GT in this liquid crystal display substrate
Of course is made larger than the original size described above.

(Scanning signal line GL) The scanning signal line GL is the second
It is composed of a conductive film g2. The second conductive film g2 of the scanning signal line GL is formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT, and is integrally formed. An aluminum anodic oxide film A is formed on the scanning signal line GL.
OF is provided.

(Dummy line DGL) As shown in FIG.
A dummy line DGL is provided outside the outermost scanning signal line GL.

Therefore, during anodization for providing the anodized film AOF on the scanning signal line GL, the electric field in the outermost scanning signal line GL portion does not become nonuniform, and the masking for the anodization is performed. Since the outermost scanning signal line GL is unlikely to be contaminated during the formation of the photoresist used for, the outermost scanning signal line GL may be disconnected when the anodic oxide film AOF is provided on the scanning signal line GL. Absent.

The anodic oxide film AO is formed on the scanning signal line GL.
When the F is provided, the dummy line DGL may be broken, but even if the dummy line DGL is broken, it does not affect the display quality of the liquid crystal display substrate. In addition, the dummy line DG
L is masked by the panel frame or the light shielding film BM.

(Insulating Film GI) The insulating film GI is used as each gate insulating film of the thin film transistors TFT1 and TFT2. The insulating film GI is formed on the gate electrode GT and the scanning signal line GL. The insulating film GI is a silicon nitride film formed by plasma CVD, for example, and is formed with a film thickness of about 3000 Å.

(I-type semiconductor layer AS) i-type semiconductor layer AS
Is used as a channel forming region for each of the thin film transistors TFT1 and TFT2, as shown in FIG. The I-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film and has a thickness of about 1800 Å.

This i-type semiconductor layer AS is continuously formed by the same plasma CVD apparatus and plasma in the same manner as the formation of the insulating film GI used as a gate insulating film made of Si ₃ N ₄ by changing the composition of the supply gas. It is formed without being exposed to the outside from the CVD device. Similarly, the N (+) type semiconductor layer d0 (FIG. 3) doped with phosphorus (P) for ohmic contact is also continuously formed to a thickness of about 400Å.
After that, the lower transparent glass substrate SUB1 is taken out from the CVD apparatus, and the N (+) type semiconductor layer d0 and the i type semiconductor layer AS are independent as shown in FIGS. 2, 3 and 8 by the photo processing technique. Patterned into islands.

As shown in detail in FIGS. 2 and 8, the i-type semiconductor layer AS is also provided between both the intersections (crossover portions) of the scanning signal lines GL and the video signal lines DL. The i-type semiconductor layer AS at the intersection is configured to reduce the short circuit between the scanning signal line GL and the video signal line DL at the intersection.

(Source electrode SD1, drain electrode SD
2) Thin film transistors TFT1 and TF divided into a plurality of parts
Source electrode SD1 and drain electrode SD of T2
2 is separated from each other on the i-type semiconductor layer AS as shown in detail in FIGS. 2, 3 and 9 (plan views showing only the first to third conductive films d1 to d3 of FIG. 2). Is provided. Each of the source electrode SD1 and the drain electrode SD2 is, from the lower layer side in contact with the N (+) type semiconductor layer d0,
The first conductive film d1, the second conductive film d2, and the third conductive film d3 are sequentially stacked. The first conductive film d1, the second conductive film d2, and the third conductive film d3 of the source electrode SD1.
Are formed in the same manufacturing process as the first conductive film d1, the second conductive film d2, and the third conductive film d3 of the drain electrode SD2.

The first conductive film d1 is a chromium film formed by sputtering and is formed to have a film thickness of 500 to 1000 Å (in this liquid crystal display substrate, a film thickness of about 600 Å). If the chrome film is made thick, the stress increases, so 2
It is formed within a range not exceeding the film thickness of 000Å. The chromium film has good contact with the N (+) type semiconductor layer d0. In the chromium film, the aluminum of the second conductive film d2 described later is N (+).
A so-called barrier layer that prevents diffusion into the type semiconductor layer d0 is formed. As the first conductive film d1, a refractory metal (Mo, Ti, Ta, W) film, a refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , W) other than the chromium film.
It may be formed of a Si ₂ ) film.

After patterning the first conductive film d1 by photoprocessing, the same photoprocessing mask is used, or
The N (+) type semiconductor layer d0 is removed using the conductive film d1 as a mask. That is, the portion other than the N (+) type semiconductor layer d0 first conductive film d1 remaining on the i type semiconductor layer AS is removed by self-alignment. At this time, since the N (+) type semiconductor layer d0 is etched so that the entire thickness thereof is removed, the i type semiconductor layer AS is also slightly etched on its surface portion, but the extent is controlled by the etching time. do it.

Thereafter, the second conductive film d2 is formed by sputtering aluminum to a film thickness of 3000 to 5500Å (in this liquid crystal display substrate, a film thickness of about 3500Å). The aluminum film has less stress than the chromium film and can be formed to have a large film thickness.
1, it is configured to reduce the resistance values of the drain electrode SD2 and the video signal line DL. The second conductive film d2 may be formed of an aluminum film containing silicon or copper (Cu) as an additive in addition to the aluminum film.

After patterning the second conductive film d2 by the photo processing technique, the third conductive film d3 is formed. The third conductive film d3 is a transparent conductive film (I
and a film thickness of 1000 to 2000Å (in this liquid crystal display substrate, a film thickness of about 1200Å). The third conductive film d3 has a source electrode SD1 and a drain electrode SD2.
And the video signal line DL and the transparent pixel electrode ITO1.

The first conductive film d1 of the source electrode SD1 and the first conductive film d1 of the drain electrode SD2 are inside (in the channel region) of the second conductive film d2 and the third conductive film d3 which are upper layers. It is very involved. That is,
The first conductive film d1 in these portions is the second conductive film d.
2, regardless of the third conductive film d3, the thin film transistor TF
The channel length L of T can be defined.

The source electrode SD1 is the transparent pixel electrode ITO1.
It is connected to the. The source electrode SD1 corresponds to the step shape of the i-type semiconductor layer AS (the film thickness of the first conductive film g1, the film thickness of the N (+)-type semiconductor layer d0, and the film thickness of the i-type semiconductor layer AS). It is formed along the step. Specifically, the source electrode SD1 includes a first conductive film D1 formed along the step shape of the i-type semiconductor layer AS, and the first conductive film D1.
The transparent pixel electrode ITO1 is formed above the conductive film d1.
The second conductive film d having a small size on the side connected to
2 and the first conductive film d1 exposed from the second conductive film d2
And a third conductive film d3 connected to. The second conductive film d2 of the source electrode SD1 cannot be formed thick because the chromium film of the first conductive film d1 cannot be formed due to an increase in stress, and cannot overcome the step shape of the i-type semiconductor layer AS. Is configured for. That is, the step coverage is improved by forming the second conductive film d2 thick. Since the second conductive film d2 can be formed thick, the resistance value of the source electrode SD1 (the drain electrode SD
2 and the video signal line DL are also the same). Since the third conductive film d3 cannot overcome the step shape of the second conductive film d2 due to the i-type semiconductor layer AS, the size of the second conductive film d2 can be reduced so that the exposed first conductive film d1 can be formed. Is configured to connect. The first conductive film d1 and the third conductive film d3 not only have good adhesiveness, but also have a small step difference in the connecting portion between them, so that the source electrode SD1 and the transparent electrode ITO1 can be reliably connected. .

(Transparent Pixel Electrode ITO1) Transparent Pixel Electrode I
TO1 constitutes one of the pixel electrodes of the liquid crystal display section.

The transparent pixel electrode ITO1 is the source electrode SD1 of the thin film transistor TFT1 and the thin film transistor T.
It is connected to the source electrode SD1 of FT2. Therefore, when a defect occurs in one of the thin film transistors TFT1 and TFT2, for example, the thin film transistor TFT1, the thin film transistor TFT1 and the video signal line DL are separated from each other by a laser beam or the like in the manufacturing process, and the thin film transistor TFT1 and the transparent pixel electrode ITO are separated.
If it is separated from 1, the point defect and the line defect do not occur, and the two thin film transistors TFT1 and TFT2 rarely occur at the same time. Therefore, the probability of the point defect occurring can be extremely reduced.

(Protective film PSV1) Thin film transistor TF
A protective film PSV1 is provided on the T and the transparent pixel electrode ITO1. The protective film PSV1 is formed mainly for protecting the thin film transistor TFT from moisture and the like,
Use one with high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus,
It is formed with a film thickness of about 00Å.

(Gate terminal GTM, drain terminal DT
M) As shown in FIG. 5, the gate terminal GTM is composed of a first conductive film g1 and a third conductive film d3.

Further, as shown in FIG. 6, the drain terminal D
TM is composed of a first conductive film g1 and a third conductive film d3.

The first conductive film g1 is, for example, a chromium (Cr) film formed by sputtering, and is formed with a film thickness of about 1000 Å.

(Light-shielding film BM) Upper transparent glass substrate SUB
A light-shielding film BM is provided on the second side so that external light (light from above in FIG. 3) does not enter the i-type semiconductor layer AS used as a channel formation region.
The pattern has a hatching of 0. 10 is a plan view showing only the third conductive film d3 made of the ITO film, the color filter FIL and the light shielding film BM in FIG. The light-shielding film BM is formed of, for example, an aluminum film or a chromium film having a high light-shielding property, and in this liquid crystal display substrate, the chromium film is formed by sputtering to have a film thickness of about 1300 Å.

Therefore, the thin film transistors TFT1,
The i-type semiconductor layer AS of the TFT 2 is sandwiched by the upper and lower light-shielding films BM and the large gate electrode GT, and that portion is not exposed to external natural light or backlight light. As shown by the hatched portion in FIG. 10, the light-shielding film BM is formed around the pixels, that is, the light-shielding film BM is formed in a grid shape (black matrix), and the effective display area of one pixel is partitioned by this grid. . Therefore,
The contour of each pixel is made clear by the light shielding film BM, and the contrast is improved. That is, the light blocking film BM has two functions of blocking the i-type semiconductor layer AS and serving as a black matrix.

Further, since the light-shielding film BM shields the portion of the transparent pixel electrode ITO facing the edge portion on the root side in the rubbing direction (the lower right portion in FIG. 2), even if a domain occurs in the above-mentioned portion, I can't see the domain, so
The display characteristics do not deteriorate.

The backlight may be attached to the upper transparent glass substrate SUB2 side and the lower transparent glass substrate SUB1 may be the observation side (externally exposed side).

(Common Transparent Pixel Electrode ITO2) The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is the pixel electrode ITO. And the common transparent pixel electrode ITO2 change in response to a potential difference (electric field). A common voltage Vc is applied to the common transparent pixel electrode ITO2.
om is applied. Common voltage V
com is an intermediate potential between the low level drive voltage Vdmin and the high level drive voltage Vdmax applied to the video signal line DL.

(Color Filter FIL) The color filter FIL is formed by coloring a dyeing base material made of a resin material such as acrylic resin with a dye. Color filter F
ILs are formed in stripes facing one pixel (FIG. 11) and are dyed separately (FIG. 11 shows only the third conductive film layer d3, the light shielding film BM and the color filter FIL of FIG. 7, B, R, G color filters FIL
Indicate 45 °, 135 °, and crosshatch, respectively). As shown in FIG. 10, the color filter FIL is formed to be large so as to cover the entire transparent pixel electrode ITO1, and the light shielding film BM is formed so as to overlap the edge portions of the color filter FIL and the transparent pixel electrode ITO.
It is formed inside the peripheral edge of O1.

The color filter FIL can be formed as follows. First, the upper transparent glass substrate SUB2
A dyeing base material is formed on the surface of and the dyeing base material other than the red filter forming region is removed by photolithography technology. After that, the dyed substrate is dyed with a red dye and a fixing process is performed to form a red filter R. Next, the green filter G and the blue filter B are sequentially formed by performing the same process.

(Protective Film PSV2) In the protective film PSV2, the liquid crystal L is a dye in which the color filter FIL is dyed in different colors.
It is provided to prevent leakage to c. The protective film PSV2 is formed of a transparent resin material such as acrylic resin or epoxy resin.

(Equivalent Circuit of Whole Display Substrate) FIG. 12 shows a connection diagram of the equivalent circuit of the display matrix portion and its peripheral circuits. Although the figure is a circuit diagram, it is drawn corresponding to the actual geometrical arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X means a video signal line DL, and subscripts G, B and R are added corresponding to green, blue and red pixels, respectively. Y represents the scanning signal line GL, and subscripts 1, 2, ..., End are added according to the order of scanning timing.

The video signal lines (subscripts omitted) are alternately on the upper side (or odd number) video signal drive circuit He and on the lower side (or even number).
It is connected to the video signal drive circuit Ho.

SUP is a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and a TFT liquid crystal display substrate above a CRT (cathode ray tube) from a host (upper processing unit). Is a circuit that includes a circuit for exchanging upwards.

(Structure of Storage Capacitance Element Cadd) The transparent pixel electrode ITO1 is formed so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TFT1. This overlay is shown in FIG.
As is clear from the above, the transparent depopulated electrode ITO1 is used as one electrode PL2 and the adjacent scanning signal line GL is used as the other electrode PL.
A holding capacitance element (electrostatic capacitance element) Cadd having a value of 1 is configured. The dielectric film of the storage capacitor Cadd is composed of an insulating film GI used as a gate insulating film of the thin film transistor TFT and an anodized film AOF.

As is apparent from FIG. 8, the storage capacitor element Cadd is formed in a portion where the width of the second conductive film g2 of the scanning signal line GL is widened. The second conductive film g2 at the portion intersecting the video signal line DL is thinned in order to reduce the probability of short circuit with the video signal line DL.

As in the case of the source electrode SD1, the transparent pixel electrode ITO1 is broken at a portion between the transparent pixel electrode ITO1 and the electrode PL1 which are overlapped to form the storage capacitor element Cadd, just like the source electrode SD1. In order not to do so, an island region including the first conductive film d1 and the second conductive film d2 is provided. This island region is formed as small as possible so as not to reduce the area (aperture ratio) of the transparent pixel electrode ITO1.

(Equivalent circuit of holding capacitance element Cadd and its operation) FIG. 13 shows an equivalent circuit of the pixel shown in FIG.
In FIG. 13, Cgs is a parasitic capacitance formed between the gate electrode GT and the source electrode SD1 of the thin film transistor TFT. The dielectric film having the parasitic capacitance Cgs is the insulating film GI.
Is. Cpix is a liquid crystal capacitance formed between the transparent pixel electrode ITO (PIX) and the common transparent electrode ITO2 (COM). The dielectric film of the liquid crystal capacitance Cpix is a liquid crystal LC,
The protective film PSV1 and the alignment films ORI1 and ORI2. Vlc is an intermediate potential.

The storage capacitor element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the thin film transistor TFT switches. This situation is expressed by the following equation.

ΔVlc = {Cgs / (Cgs + Cadd
+ Cpix)} × ΔVg Here, ΔVlc represents a change in the midpoint potential due to ΔVg. The variation ΔVlc causes a direct current component applied to the liquid crystal LC, and the value can be reduced as the storage capacitance Cadd is increased. Further, the storage capacitor element Cadd also has a function of prolonging the discharge time, and stores the image information after the thin film transistor TFT is turned off for a long time. The reduction of the direct current component applied to the liquid crystal LC is
It is possible to improve the life of the display device and reduce the so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.

As described above, since the gate electrode GT is made large so as to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 is increased, so that the parasitic capacitance Cgs is large. Therefore, there is an adverse effect that the midpoint potential Vlc is easily influenced by the gate (scanning) signal Vg. However, the storage capacitor C
By providing the add, this demerit can be eliminated.

The storage capacity of the storage capacity Caad is 4 to 8 times (4.times.) The liquid crystal capacity Cpix due to the writing characteristics of the pixel.
Cpix <Cadd <8 · Cpix), parasitic capacitance Cgs
8 to 32 times (8 ・ Cgs <Cadd <32 ・ C
gs).

(Tanging Method of Storage Capacitance Element Cadd Electrode Line) As shown in FIG. 12, the scanning signal line GL (Yo) at the first stage used only as a storage capacitance electrode line is connected to the common transparent pixel electrode ITO (Vcom). Connecting. As shown in FIG. 3, the common transparent pixel electrode ITO2 is connected to the external lead wiring by the silver paste material SL at the peripheral edge of the liquid crystal display substrate. Moreover, a part of the conductive films (g1 and g2) of the external lead wiring are formed in the same manufacturing process as the scanning signal line GL. As a result, the last-stage storage capacitor GL
Can be easily connected to the common transparent pixel electrode ITO2.

The storage capacitor electrode line Yo in the first stage is connected to the scanning signal line Yend in the final stage, is connected to a DC potential point (AC connection point) other than Vcom, or one extra scanning pulse Yo is supplied from the vertical scanning circuit V. You may connect to receive.

Next, a method of manufacturing the liquid crystal display substrate according to the present invention will be described. The manufacturing process is shown in FIG.

Step 1. First, a silicon oxide film SIO is provided on both surfaces of a lower transparent glass substrate SUB1 made of 7059 glass (trade name) by dip processing, and then 50
Bake at 0 ° C. for 60 minutes.

Step 2. Then, this substrate is washed.

Step 3. Lower transparent glass substrate SUB1
First conductive film g1 made of chrome with a film thickness of 1100Å on top
Are provided by sputtering. Next, the gate terminal GTM and the drain terminal DTM are formed by selectively etching the first conductive film g1 by a photoetching technique using a ceric ammonium nitrate solution as an etching solution, and as shown in FIG. Anodizing bus line A for connecting the gate terminal GTM to
OB, an anodizing pad AOP connected to the anodizing bus line AOB is formed.

Step 4. Next, after removing the resist with a stripping solution, O ₂ asher is performed for 1 minute. Next,
Aluminum-palladium, aluminum-silicon, aluminum-silicon-titanium with a film thickness of 2600Å,
The second conductive film g2 made of aluminum-silicon-copper or the like
Are provided by sputtering. Next, the second conductive film g2 is selectively etched by a photoetching technique using a mixed acid of phosphoric acid, nitric acid, and acetic acid as an etching solution, so that the scanning signal line GL, the gate electrode GT, the dummy line DGL, and the holding line are held. The electrode PL1 of the capacitive element Cadd is formed.

Step 5. Next, SF ₆ gas is introduced into the dry etching apparatus to remove residues such as silicon and then remove the resist. Next, a photoresist RST for anodization is provided. Next, a portion of the lower transparent glass substrate SUB1 to be anodized in an anodizing solution composed of a solution of 3% tartaric acid adjusted to pH 7.0 ± 0.5 with ammonia diluted with ethylene glycol solution 1: 9. By anodic oxidation of the second conductive film g2 by applying an anodic oxidation voltage to the anodic oxidation pad AOP, and the anodic oxidation film A on the scanning signal line GL and the gate electrode GT.
Provide OF.

Step 6. Next, introduce ammonia gas, silane gas, and nitrogen gas into the plasma CVD apparatus,
A silicon nitride film with a thickness of 3500Å is provided, and plasma C
By introducing silane gas and hydrogen gas into the VD device, the film thickness becomes 2
After a 100 Å i-type amorphous silicon film is provided, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus and N
A (+) type amorphous silicon layer is provided.

Step 7. Then, in this embodiment, the N (+) type amorphous silicon layer is washed with an organic alkali.

In this case, the surface of the semiconductor layer cleaned with the cleaning liquid is in the same state as the surface thereof is light-etched.

Unlike the inorganic alkali, the organic alkali does not contain Na (+) ions, and therefore does not cause any harmful effect due to this ionic substance.

When an inorganic alkali is used, a-S
The light etching of the i film becomes non-uniform, but the uniformity is good in the case of organic alkali. Organic alkalis have these advantages over inorganic alkalis.

For this reason, so-called flakes or foreign substances attached to the surface of the semiconductor layer can be removed almost completely and reliably.

This makes it possible to completely and reliably prevent a disconnection, a short circuit, a point defect or the like caused by the flakes or foreign matter in the manufactured TFT.

Step 8. Next, the N (+) type amorphous silicon film and the i type amorphous silicon film are selectively etched by a photoetching technique using SF ₆ and CCl ₄ as a dry etching gas. Form AS.

Step 9. Next, after removing the resist, the insulating film GI is formed by selectively etching the silicon nitride film by a photoetching technique using SF ₆ as a dry etching gas.

Step 10. Next, after removing the resist, the first conductive film d1 made of chromium and having a film thickness of 600 Å
Are provided by sputtering. Next, the first conductive film d1 is selectively etched by a photo etching technique to form the first layer of the video signal line DL, the source electrode SD1, and the drain electrode SD2. Next, before removing the resist, a dry etching apparatus was used to remove CCl ₄ , SF ₆
Is introduced to form an N (+) type semiconductor layer d0. Next, after removing the resist, an O ₂ asher is performed for 1 minute. Next, a second conductive film d2 made of aluminum-palladium, aluminum-silicon, aluminum-silicon-titanium, aluminum-silicon-copper or the like having a film thickness of 3500Å is provided by sputtering. next,
By selectively etching the second conductive film d2 by the photo etching technique, the video signal line DL and the source electrode S
A second layer of D1 and drain electrode SD2 is formed. Next, after removing the resist, an O ₂ asher is performed for 1 minute. Next, a third conductive film d3 made of an ITO film having a film thickness of 1200 Å is provided by sputtering. Next,
By selectively etching the third by a photo-etching technique using a mixed acid of hydrochloric acid and nitric acid as an etching liquid, the third layer of the video signal line DL, the source electrode SD1, the drain electrode SD2, the gate terminal GTM, and the drain terminal The uppermost layer of DTM and the transparent pixel electrode ITO1 are formed.

Step 11. Next, after removing the resist, an ammonia gas, a silane gas, and a nitriding gas are introduced into the plasma CVD apparatus to form a silicon nitride film having a thickness of 1 μm. Next, S as a dry etching gas
By selectively etching the silicon nitride film by a photo-etching technique using F ₆ , the protective film PSV1
To form.

As described above, the invention made by the present inventor is
Although described concretely based on the above embodiment, the present invention is
It is needless to say that the present invention is not limited to the above-mentioned embodiment, and various changes can be made without departing from the scope of the invention.

For example, in the above embodiment, gate electrode formation-gate insulating film formation-semiconductor layer formation-source.
Although the inverted staggered structure for forming the drain electrode is shown, the present invention is also effective for a staggered structure in which the vertical relationship or the order of making the electrodes is reversed.

Further, in the above-mentioned embodiment, the cleaning of the a-Si layer is described as containing only the organic alkali, but the cleaning is not limited to this, and the surfactant may be contained therein. It goes without saying that it is okay. This is because the cleaning power can be further increased by doing so.

Needless to say, ultrasonic waves may be applied during cleaning. further,
Needless to say, it may be washed by using a spray or the like.

[0096]

As is apparent from the above description,
According to the method of manufacturing a liquid crystal display substrate of the present invention, it is possible to completely and reliably prevent the adverse effects such as disconnection, short circuit, or point defect caused by flakes or foreign matter in a TFT that has been manufactured. .

[Brief description of drawings]

FIG. 1 is a flow chart showing an embodiment of a method for manufacturing a liquid crystal display substrate according to the present invention.

FIG. 2 is a plan view of relevant parts showing a pixel of a liquid crystal display section of an active matrix type liquid crystal display substrate to which the present invention is applied.

FIG. 3 is a cross-sectional view of a portion taken along a line 3-3 in FIG. 2 and a peripheral portion of a seal portion.

4 is a cross-sectional view taken along section line 4-4 of FIG.

5 is a cross-sectional view showing a gate terminal portion of the liquid crystal display substrate shown in FIG.

6 is a cross-sectional view showing a drain terminal portion of the liquid crystal display substrate shown in FIG.

7 is a plan view of a main part of a liquid crystal display unit in which a plurality of pixels shown in FIG. 2 are arranged.

FIG. 8 is a plan view showing only a predetermined layer of the pixel shown in FIG.

FIG. 9 is a plan view showing only a predetermined layer of the pixel shown in FIG.

10 is a plan view illustrating only a predetermined layer of the pixel shown in FIG.

FIG. 11 is a plan view of a principal part illustrating only the pixel electrode layer, the light shielding film, and the color filter layer shown in FIG.

FIG. 12 is an equivalent circuit diagram showing a liquid crystal display portion of an active matrix type color liquid crystal display substrate.

FIG. 13 is an equivalent circuit diagram of the pixel shown in FIG.

14 is a plan view of an essential part of the liquid crystal display substrate shown in FIG.

15 is an explanatory diagram of a method for manufacturing the liquid crystal display substrate shown in FIG.

[Explanation of symbols]

 AS i type semiconductor layer TFT thin film transistor

Front Page Continuation (72) Inventor Mitsuo Nakatani 3300 Hayano, Mobara-shi, Chiba Hitachi, Ltd. Electronic Devices Division

Claims (1)

[Claims] 1. A method of manufacturing a liquid crystal display substrate comprising a TFT having a-Si as a semiconductor layer, wherein the semiconductor layer is formed, and then the semiconductor layer is washed with a washing liquid containing an organic alkali. Manufacturing method of display substrate.