JPH04367941A - Microprocessor - Google Patents

Abstract

PURPOSE:To execute the processing immediately after receiving the interruption processing, and to improve the interruption responsiveness by providing an instruction buffer for storing in advance instructions of the number determined in advance for constituting the head of a subroutine of the interruption processing. CONSTITUTION:When an interruption control part 4 receives an interruption, a gate 7 is turned on, and three instructions for constituting the head of an instruction processing subroutine stored in an instruction buffer 3 in advance are outputted to an instruction decoder 2. Simultaneously, an address correcting part 5 adds 3 being the number of instructions outputted from the instruction buffer 3, to an address generated by an address generating part 6 and outputs it to an address terminal TA, and starts a fetch. Subsequently, when the contents of an instruction queue 1 are saved, immediately the instructions stored in buffers 31-33. respectively of the instruction buffer 3 are fetched successively, and decoding is executed by the instruction decoder 2. Also, the instruction after the buffer 33 passes through the fetch, and store to the instruction queue 1, and goes into a decoding stage subsequently to an output instruction from the buffer 33.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor having an external interrupt processing function.

0002

BACKGROUND OF THE INVENTION In a microprocessor having an instruction queue, such as the 8086 manufactured by Intel Corporation in the United States, when performing a branch operation such as external interrupt processing, the contents of the instruction queue are saved and re-entered. The instruction to be interrupted must be fetched.

As shown in FIG. 5, a conventional microprocessor of this type includes an instruction queue 1, an instruction decoder 2 output from the instruction queue 1, and an instruction decoder 2 that controls interrupt processing in response to interrupt input from the outside. The interrupt control section 4 was configured to include an interrupt control section 4 for performing interrupt processing, and an address generation section 6.

Next, the operation of a conventional microprocessor will be explained.

FIG. 6 is a flowchart showing interrupt processing of a conventional microprocessor.

[0006] When an interrupt input is received from the outside, the interrupt input terminal TI becomes active, and the interrupt control unit 4 accepts this interrupt at a timing that matches the processing execution state inside the microprocessor. When an interrupt is accepted, the instruction code that has already been fetched from the instruction queue 1 is saved to a save register or the like. At the same time, the address generation section 6 performs address calculation in order to branch to the interrupt processing subroutine.

As shown in the time chart of FIG. 6, after starting re-fetching of the interrupt destination instruction, the instruction is fetched into the instruction queue 1, the instruction is decoded by the instruction decoder 2, and then the interrupt processing is executed. It takes 3 clocks to enter. In this case, the instruction code is one word, and therefore, an example is shown in which the fetching can be completed with one fetch. However, as the instruction code becomes longer, the number of clocks required from fetch to execution of interrupt processing increases.

[0008]

[Problems to be Solved by the Invention] The above-mentioned conventional microprocessor requires a period of time ranging from several clocks to more than ten clocks after calculating an address when an interrupt occurs until it actually starts executing processing. This has the disadvantage that the interrupt response is slow.

[0009]

[Means for Solving the Problems] The microprocessor of the present invention is a microprocessor having an external interrupt processing function, in which a predetermined number of instructions constituting the beginning of the external interrupt processing subroutine are stored. It is configured with a buffer.

0010

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a microprocessor according to the present invention.

As shown in FIG. 1, the microprocessor of this embodiment includes an instruction queue 1 similar to the conventional one, an instruction decoder 2 output from the instruction queue 1, and an interrupt processing function in response to an external interrupt input. In addition to the interrupt control section 4 and the address generation section 6, there is also a buffer 31 which can store three instructions with a one-word instruction word length in this embodiment, among the instructions forming the head of the interrupt processing subroutine. 3
An instruction buffer 3 consisting of 2 and 33 components, and an address generation section 6
an address correction unit 5 that adds the number of instructions stored in the instruction buffer 3, that is, 3, to the address generated by the gate 7;
It is composed of:

Next, the operation of this embodiment will be explained.

FIG. 2 is a flowchart showing the interrupt processing of the microprocessor of this embodiment.

When an interrupt is input from the outside, the interrupt input terminal TI becomes active, and the interrupt control section 4 accepts this interrupt at a timing that matches the processing execution state inside the microprocessor. When an interrupt is accepted, the instruction code that has already been fetched from the instruction queue 1 is saved to a save register or the like. At the same time, the address generation section 6 performs address calculation in order to branch to the interrupt processing subroutine.

On the other hand, when the interrupt control unit 4 accepts an interrupt, it turns on the gate 7 and executes the interrupt processing subroutine 3 which constitutes the beginning of the interrupt processing subroutine stored in the instruction buffer 3 in advance.
outputs one instruction to the instruction decoder 2. At the same time, the address correction unit 5 adds 3, which is the number of instructions output from the instruction buffer 3, to the address generated by the address generation unit 6, and outputs the result to the address terminal TA, and starts fetching.

As shown in the time chart of FIG. 2, immediately after the contents of the instruction queue 1 are saved, the instructions stored in the buffers 31, 32, and 33 of the instruction buffer 3 are sequentially taken out and decoded by the instruction decoder 2. Do this. Further, the instructions after the buffer 33 are fetched and stored in the instruction queue 1, and then enter the decode stage next to the output instruction from the buffer 33.

As described above, by storing some of the instructions forming the beginning of the interrupt processing subroutine in advance in the instruction buffer 3, it becomes possible to fill the idle cycle from fetching the instruction to executing the interrupt processing. , responsiveness can be improved.

Next, a second embodiment of the present invention will be explained.

Most microprocessors have multiple interrupt input terminals. However, there are various types of interrupts, and some require high-speed response while others do not necessarily require high-speed response. This embodiment shows an example in which one of three interrupt inputs requires a high-speed response.

FIG. 3 is a block diagram showing a second embodiment of the microprocessor of the present invention.

The difference between this embodiment and the first embodiment described above is that the input terminals TI of the interrupt control section 8 are TI1 to TI3 corresponding to the three interrupt inputs. The present invention is equipped with a high-speed interrupt detection section 9 for detecting an interrupt input that requires a high speed interrupt.

The high-speed interrupt detection section 9 is for programmably setting one of the three input interrupt input terminals TI1 to TI3 as a high-speed interrupt input, and detecting an interrupt input from the set terminal. . An example of the configuration of the high-speed interrupt detection section 9 is shown in FIG. High-speed interrupt detection section 9
As shown in FIG. 4, the register 91 has the same bit length as the number of interrupt input terminals (3), and the AND gates A91 to A93 that take the AND of the output of each bit of the register 91 and the respective inputs of the terminals TI1 to TI3. and AND gate A91
- OR gate O91 which takes the logical sum of the outputs of A93.

Next, the operation of this embodiment will be explained.

First, register 91 of high-speed interrupt detection section 9
'100' is set in advance to designate the interrupt input terminal TI1 as a high-speed interrupt input. Now, if the interrupt input terminal TI1 of the three input interrupt input terminals TI1 to TI3 becomes active, the interrupt control unit 4 accepts this interrupt at a timing that matches the processing execution state inside the microprocessor. When an interrupt is accepted, the instruction code that has already been fetched from the instruction queue 1 is saved to a save register or the like. At the same time, the address generation section 6 performs address calculation in order to branch to the interrupt processing subroutine.

When the interrupt control unit 4 receives an interrupt, the interrupt control unit 4
The states of the input interrupt input terminals TI1 to TI3 are output to the high speed interrupt detection section 9. As mentioned above, '100' is set in advance in the register 91 of the high-speed interrupt detection unit 9, so when there is an interrupt input to the interrupt input terminal TI1, the AND gate A91 becomes 1, and the input Interrupts are detected as fast interrupt inputs. As a result, this detection output turns on the gate 7, and similarly to the first embodiment described above, the three instructions constituting the beginning of the interrupt processing subroutine stored in the instruction buffer 3 in advance are sent to the instruction decoder 2. Output. At the same time, the address correction unit 5 adds 3, which is the number of instructions output from the instruction buffer 3, to the address generated by the address generation unit 6 and outputs the result to the address terminal T.
Output to A and start fetching.

As described above, in this embodiment, it is possible to selectively store instructions in the instruction buffer for a high-speed response to an interrupt input that requires the most urgency and high-speed response, and requires less hardware. It is expected that the performance will be effectively improved by using the software.

[0028]

As explained above, the microprocessor of the present invention has an instruction buffer that stores a predetermined number of instructions that constitute the beginning of the interrupt processing subroutine. This has the effect of improving interrupt responsiveness since processing can be executed immediately.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of a microprocessor of the present invention.

FIG. 2 is a flowchart showing an example of the operation of the microprocessor of this embodiment.

FIG. 3 is a block diagram showing a second embodiment of the microprocessor of the present invention.

FIG. 4 is a diagram illustrating an example of the configuration of a high-speed interrupt detection section according to the present embodiment.

FIG. 5 is a block diagram showing an example of a conventional microprocessor.

FIG. 6 is a flowchart showing an example of operations in a conventional microprocessor.

[Explanation of symbols]

1 Instruction queue 2 Instruction decoder 3. Instruction buffer 4, 8 Interrupt control section 5 Address correction section 6 Address generation section 7 Gate 9 High-speed interrupt detection section 31-33 Buffer 91 Register A1-A3 AND gate O1 OR gate

Claims (2)

[Claims] 1. A microprocessor having an external interrupt processing function, comprising an instruction buffer for storing a predetermined number of instructions forming the beginning of the external interrupt processing subroutine. 2. n comprising a bit corresponding to each of the n external interrupt inputs requesting the external interrupt processing;
The present invention further includes a high-speed interrupt detection section that includes a bit length register and detects the first external interrupt input by setting in advance the bit corresponding to the first external interrupt input that requests a high-speed response in the register. A microprocessor as claimed in claim 1.