JPH0436465B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the layout of semiconductor memory devices.

Generally, as shown in FIG. 1, a semiconductor memory device generally has a memory cell array section 1 such as a memory cell matrix and decoder arranged in the center, and a clock generator and input/output circuits 2a and 2b arranged around the periphery. Figure 1 shows a typical example of the layout that is most commonly used today.In order to organically arrange increasingly complex circuit networks, peripheral circuits are often laid out in a concentrated manner on the upper and lower sides of the memory cell array. On the other hand, due to the width limitations of the case, peripheral circuits are not placed on the left and right sides of the memory cell array section, and only the power supply line, ground line, and about 10 other clock lines are placed. There are many.

It is necessary to arrange power supply main wiring and ground main wiring in both the memory cell array part and the peripheral part, respectively, and most of them are arranged in a ring shape as shown in FIGS. 2 and 3. Figures 2 and 3 illustrate configurations with only aluminum main wiring for power and ground, the former being shown by broken lines and the latter by solid lines.
35 is a bonding pad. A group of wires such as peripheral power supply lines 23 and 33 and a clock are arranged between the inner ground lines 21 and 31 for the memory cell array section and the outer ground lines 22 and 32 for the peripheral section. (The power supply line for the memory cell array is omitted.) Conventionally, rising potential on the ground line often causes malfunctions such as decoder multi-select, so the inner and outer ground lines were connected in consideration of wiring resistance. It was common sense to connect with aluminum (A-A', B-B').

The problem here is that the peripheral power supply line is A-
Similarly, several to more than ten clock wires are cut at A', B-B' and cannot form a ring, and there is a thick grounding with a width of about 30 μm at A-A', B-B'. Since these two points intersect, it becomes necessary to conduct wiring using a thin impurity diffusion layer or a polycrystalline silicon layer, resulting in a wiring resistance of several hundreds of ohms.

Semiconductor memory devices are rapidly becoming larger in storage capacity and faster in speed, increasing the load capacity of each clock and increasing the current capacity of the transistors that charge it. The current flowing through is very large, especially instantaneous current, which can reach several 100 mA in 10 nanoseconds, and the two problems mentioned above are becoming serious. For example, regarding clocks that drive the memory cell array, such as word line drive clocks and data line precharge clocks,
Many have a resistance of several tens of pF, and the wiring resistance is several hundred ohms.
If the amount of readout signals is reduced, it may become an obstacle to speeding up or cause malfunctions.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed, large-storage-capacity semiconductor memory device that reduces the resistance of power supply lines and clock lines without significantly affecting the overall layout such as chip size.

According to the present invention, a semiconductor chip of one conductivity type has an array region including a memory cell matrix, a decoder, etc. at the center of the main surface, and peripheral circuit regions are almost unevenly distributed around the chip in two directions above and below. A semiconductor memory device having a first metal main wiring layer forming a power supply line or a ground line belonging to an array region and a second metal main wiring layer forming a power supply line or a ground line belonging to a peripheral region of the semiconductor chip. The first and second metal main wiring layers are formed along the array region by an impurity diffusion region extending to the chip peripheral region in the left and right directions of the array region or by a polycrystalline silicon layer containing impurities. This is a semiconductor memory device characterized in that the two metal wiring layers are connected to each other, but are not connected to other metal wiring layers.

Next, an embodiment of the present invention is shown in FIGS. 4 and 5.
Figure 5 shows the configuration within the dotted line in Figure 4.
The inner ground lines 41 and 52 and the outer ground lines 42 and 53 are formed using impurity diffusion layers or polycrystalline wires on the entire side surface of the memory cell array section where peripheral circuits are not arranged (the left side of the memory cell array section can be constructed in the same way as the right side). They are connected by a silicon layer 51. In the area shown in FIG. 5C, a group of clock wiring lines is arranged. 44 and 45 are bonding pads, and 54 is a contact opening array.

For example, the chip length is 6mm, the ground wire width is 6mm.
Assuming that aluminum has a thickness of 30 μm and 1.2 μm, the layer resistance of the impurity diffusion layer 51 is 30 Ω, and the width of the C region is 100 μm.
The wiring resistance from the bonding pad to the far end of the memory cell array ground wire is Na in the conventional example in Figure 2.
About 4.5Ω for Nb, and about 4.7Ω for Nb in Fig. 4 of the embodiment of the present invention.
The increase is less than 5%, which can be said to be sufficiently small.

On the other hand, in FIG. 4, there is no wiring section shown as A-A', B-B' in FIGS. Even when the width is used, the resistance can be reduced to 1/2 that of the conventional example. As mentioned above, this is very effective against the current potential drop that occurs when the current, especially the instantaneous current, is large as in a high speed, large storage capacity semiconductor memory device. Furthermore, the resistance of the clock wiring as described above is small, preventing malfunctions and increasing speed.

Furthermore, the current in the memory cell array section is A-
It is not concentrated like in part A' but is dispersed into two, which can be said to be advantageous against aluminum and migration.

[Brief explanation of drawings]

FIG. 1 shows a typical example of the current block layout, with reference numeral 1 indicating a memory cell array section and 2a and 2b indicating peripheral circuit sections. Figures 2 and 3 are examples of conventional power supply and ground line layouts, with 21 and 31 being inner lines,
22 and 32 are outer grounding wires, 23 and 33 are power supply lines, and 24, 25, 34, and 35 are bonding pads. 4 and 5 show examples of the present invention, 41 and 52 are inner grounding wires, 42 and 53 are outer grounding wires, 43 is a power supply line, 44 and 45 are bonding pads, and 51 is an impurity diffusion wire. The layer or polycrystalline silicon layer 54 represents the contact opening. Incidentally, FIG. 5 shows the configuration diagram within the dotted line in FIG. 4.

Claims (1)

[Claims] 1. A semiconductor memory device having an array region including a memory cell matrix, a decoder, etc. in the center on one main surface of a semiconductor chip of one conductivity type, and peripheral circuit regions laid out around the chip in two directions above and below the array region. A first power supply line belonging to the region and a second power supply line belonging to the peripheral circuit region and located outside the first power supply line are both formed of a first metal wiring layer, and the first and second power supply lines A third power line formed of the first metal wiring layer is provided in a continuous ring between the power lines, and the first and second power lines are supplied with one of a power supply potential and a ground potential. , the third power supply line is supplied with the other of a power supply potential and a ground potential, and an impurity diffusion region or an impurity-containing region extending along the array region in the chip peripheral region in the left and right sides of the array region. The first polycrystalline silicon layer
and a second power supply line are connected to each other.