JPS594158A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve the layout efficiency of a semiconductor memory device by composing cell plate and bit lines of a polycrystaline silicon layer, a high melting point metal and metal silicide and the like. CONSTITUTION:A memory cell is formed by interposing a dielectric film 7 for a storage capacitor between a capacitor electrode 5 of a polycrystalline silicon layer and a cell plate and bit line 9A. A gold layer electrode and wiring layer 13 is formed via an insulating layer 11 on the memory cell. In this manner, the metal electrode and wiring layer is used as wirings or bonding pad which do not relate directly to the memory cell itself, and is effective for the reduction in the size of the memory chip and in the wiring length of the bit line.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor memory device having a dynamic random access memory (d-RAM) consisting of a memory cell including one transfer transistor and a storage capacitor. Regarding improvements.

Conventional technology and problems Conventionally, d-RAM, especially MOS dynamic random access memory (MOS-d-RA(1)M), consists of two layers of polycrystalline silicon electrodes/wiring layers and one layer of metal electrodes/wiring layers. It was configured using .

Since such a MOS-d-RAM has a structure in which the transfer transistor and the storage capacitor are laid out on the same plane, the area occupied by the storage capacitor in the memory cell cannot be made very large. At most 2
It was about 5%.

However, in recent years, a three-dimensional structure has been proposed in which the polycrystalline silicon electrode/wiring layer is three-layered and the storage capacitor is formed up to the top of the transfer transistor. It is now possible to occupy more than 50%.

FIG. 1 is a sectional view of a main part for explaining the structure of a memory cell having the three-layer polycrystalline silicon electrode/wiring layer.

In the figure, 1 is a p-type silicon semiconductor substrate, 2 is a field insulating film made of a silicon dioxide film, 3 is a transfer gate which is a first polycrystalline silicon layer, 4 is an n+ type bit line contact region, and 5 is a (2) n+ type electrode contact region, 6 is a storage capacitor electrode which is a second polycrystalline silicon layer, 7 is a storage capacitor dielectric film made of a silicon nitride film, etc., and 8 is a third polycrystalline silicon layer. A certain cell plate, 9 a bit line made of a metal layer such as aluminum, TG a transfer l/transistor part, and BT one bit.

In this memory cell, the first polycrystalline silicon layer also serves as the 1-transfer gate 1 and 3-transfer transistor word line. A storage capacitor electrode 6 made of a second polycrystalline silicon layer is connected to an n+ type contact region 5 which is a source region or a drain region of a transfer transistor. The third layer is a polycrystalline silicon layer.
Plate 8 is the counter electrode of the storage capacitor in each memory cell. The bit line 9 is connected to n+ which is the source region or drain region of the transfer transistor every two pins 1-.
type bit line contact region 4.

By the way, there are considerable problems in laying the bit line 9 in this memory cell. That is, as described in (3) above, the n+ type bit line contact region 4 is formed every 2 bits.
In the process of connecting to the wire, it is necessary to overcome a step equal to the total thickness of the three polycrystalline silicon layers and the thickness of the insulating film between the layers, which is likely to cause disconnection 72.

In order to eliminate such drawbacks, the present inventor has previously proposed an improved invention. That is, the conventional side circuit shown in FIG. 2 is as shown in FIG. 2, but by changing this to the circuit shown in FIG. 3, a storage capacitor is formed on the transfer transistor. It also made it possible to realize a memory cell with two layers of polycrystalline silicon and one layer of metal electrodes and wiring (if required, please refer to Japanese Patent Application No. 55-98426).
(see issue).

In FIG. 2, the same parts as those described with respect to FIG. 1 are indicated by the same symbols. Note that MC indicates a storage capacitor.

In FIG. 3, the same parts as those explained in connection with FIG. 2 are indicated by the same symbols. Note that 10 indicates a reference potential line.

(4) FIG. 4 is a cross-sectional view of a main part of the circuit shown in FIG. 3 as a specific semiconductor memory device, and the same parts as those explained with reference to FIG. 1 are indicated by the same symbols.

This semiconductor memory device is different from the conventional example shown in FIG. The equivalent is cell plate/bit line 9A
As seen in the conventional example in FIG.
Since there is no need to connect to the bit line contact area 4, there is no need to go over steep and high steps, and the possibility of disconnection is therefore reduced.Furthermore, since there is no need for a contact window for the bit line, there is no need to climb over a steep and high step. Since the capacitor can be used as a storage capacitor, almost the entire area of the memory cell can be used as a storage capacitor.

Therefore, the output voltage of the memory cell is large and slightly N
If it is acceptable to sacrifice the capacitance of the product capacitor, reliability can be improved by increasing the thickness of the insulating film.

Object of the Invention (5) In the improved semiconductor memory device, the present invention provides that the cell plate/bit line is formed of a third layer of polycrystalline silicon, a high melting point metal, metal silicide, or the like. This improves the layout efficiency of the acoustic conductor storage device.
It's something that will hit you.

Structure of the Invention The present invention is based on the technical concept of further reducing the number of electrodes and wiring layers of memory cells by using cell plates and bit lines. Second, while in the conventional example explained with reference to FIG. The memory cell itself does not use an aluminum electrode/wiring layer, but is instead used as the electrode/wiring layer necessary for the operational function of the memory cell.

Incidentally, if an attempt is made to do something similar to the present invention in the prior art explained with reference to FIG. 1, at least three polycrystalline silicon layers and two aluminum layers or four polycrystalline silicon layers are used. , is not possible without using an additional layer of aluminum(6).

Embodiment of the Invention FIG. 5 is a cross-sectional view of a main part of an embodiment of the present invention, and the same portions as those described in connection with FIG. 4 are designated by the same symbol 1h.

The difference between this embodiment and the conventional example shown in FIG. 4 is that Cell Play! - A double layer 71 and a line 9A are formed of a third layer of polycrystalline silicon, and on top of that a silicon dioxide insulation I*11 formed by, for example, chemical vapor deposition, and further on top of that is a metal electrode/wiring made of aluminum. Layer 12 is formed. In the present invention, the first to third polycrystalline silicon layers can all be replaced with high melting point metal layers or metal silicide layers.

The performance of the memory can be greatly improved depending on how the metal electrode/wiring layer 12 is used in this embodiment.

FIG. 6 is a block diagram of a semiconductor memory device to which the memory cell shown in FIG. 5 is applied.

In the figure, MA is the memory cell array (1(7)/2), SA is the sense amplifier, RD is the row decoder, CD is the column decoder, DB is the data bar, and MA is the I10 buffer amplifier. Each is shown below.

Conventionally, in such semiconductor storage devices, data
Buses are taken out in a complementary manner. In other words, by sending the voltage across the sense amplifier to the data bus, noise mixed in the common mode is canceled, and data can be written without going through the sense amplifier. was installed near the sense amplifier. For this reason, the column switch that connects the data bus and bit line or sense amplifier must be placed near the sense amplifier, and as a result, the column decoder for driving the column switch must also be placed near the sense amplifier. need to be placed.

For this reason, the area around the sense amplifier is complicated and the design is not easy. Furthermore, the bit line must be routed to the sense amplifier through the gap between the column decoders, and this wiring section may cause undesired problems. This caused capacitance to be applied to the bit line, causing the output voltage of the memory cell to drop. The above problem can be solved by placing the column decoder outside the cell array, but in that case, the line connecting the column switch and column decoder must be routed through the cell array, and the memory cell・The efficiency of the layout in the array becomes extremely poor.

However, according to the present invention, an efficient memory cell can be created simply by using an electrode/wiring layer made of three layers of polycrystalline silicon (or a metal silicide layer, etc.).・Memory wiring layer
Memory cell data from decoder CD outside cell array MA
This wiring can be used to connect the column switches near the sense amplifier SA in the center of the array MA.
It can be placed on the memory cell array without sacrificing the density of the memory cell array.

The effect of the metal electrode/wiring layer 12 in FIG. 5 will be further explained.

FIG. 7 is a block diagram (9) of a semiconductor memory device having a multi-bit configuration, and the same parts as those explained in connection with FIG. 6 are indicated by the same symbols. Furthermore, DBG is a memory cell.
It shows the data bus bundle drawn out onto the array.

The metal electrode/wiring layer 12 can be used as a multi-bit data bus.

A multi-bit configuration is one in which multiple pieces of data are output in parallel for one address, and in such a case, the number of data buses drawn out from the memory cell array becomes extremely large. Wiring near the sense amplifier occupies a considerable area.

Therefore, the bit line becomes unnecessarily long and the bit line capacitance increases accordingly, which is undesirable and also increases the chip area of the memory.

On the other hand, by applying the memory cell of the present invention, a data bus can be laid over the memory cell array MA as indicated by the symbol DBG in FIG. The area occupied by this data bus wiring does not substantially increase the size of the memory chip.

(10) FIG. 7 shows a case in which one word has 8 bits. In this embodiment, at least 8 pairs of data buses are required, so 8 data buses per side are connected to the cell.
wired on the array.

Assuming that the number of bits on the column decoder side is 256, one of the 32 bit lines for one data lot is selected by the column decoder CD (8 bits x 3
2 = 256 bits).

In the above embodiments, the metal electrode/wiring layer 12 is used as a so-called wiring such as a data lot, but the present invention is not limited to this, and may be used as a bonding pad, for example.

Generally, bonding pads are placed around the chip, but when the number of input/output terminals is large, such as in a multi-bit memory, the area occupied by the bonding band cannot be ignored. In such a case, if bonding pads are formed on the cell array via a thick insulating film according to the present invention, the chip size can be determined almost independently of the number of bonding pads.

Effects of the Invention A semiconductor memory device according to the present invention has a dynamic random access memory cell consisting of an M product capacitor and a transfer transistor, and one electrode of the storage capacitor is also used as a pin line. Since a metal electrode/wiring layer can be formed on the memory cell through insulating H moxibustion, it is possible to use the metal electrode/wiring layer as a wiring or bonding pad that is not directly related to the memory cell itself. This is effective for reducing memory chip dimensions, bit line wiring lengths, etc.

[Brief explanation of drawings]

FIG. 1 is a sectional view of the main part of the conventional example, FIGS. 2 and 3 are circuit diagrams of the main part of the conventional example, FIG. 4 is a sectional view of the main part of the conventional example, and FIG. 5 is a sectional view of the main part of the conventional example. 6 and 7 are block diagrams of a semiconductor memory device suitable for use with the memory cell of the present invention. In the figure, 1 is a p-type silicon semiconductor substrate, 2 is a field insulating film made of a silicon dioxide film, 3 is a transfer gate which is a first polycrystalline silicon layer, 5 is an n1-type electrode contact region, and 6 is a third A storage capacitor electrode is a two-layer polycrystalline silicon layer, 7 is a storage capacitor dielectric film made of a silicon nitride film, 9A is a cell plate/bit line, 10 is a reference potential line, ] 1 is a silicon dioxide insulating film, 12 is a metal electrode/wiring layer. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Tools: Kugobe (3 others) (I3) Figure 1 G BT □ Figure 2 Figure 3 Figure 4 7G Mine-□---- BT □ Figure 5 Figure 6 Figure 7 281

Claims (1)

[Claims] In a semiconductor memory device having a dynamic random access memory cell consisting of an M-product capacitor and a transfer transistor, an insulating film is provided over a bit line that also serves as one electrode of the storage capacitor and the memory cell. 1. A semiconductor memory device comprising a metal electrode and a wiring layer formed through the metal electrode and wiring layer.