JPH0231454A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0231454A JPH0231454A JP63181370A JP18137088A JPH0231454A JP H0231454 A JPH0231454 A JP H0231454A JP 63181370 A JP63181370 A JP 63181370A JP 18137088 A JP18137088 A JP 18137088A JP H0231454 A JPH0231454 A JP H0231454A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- power source
- pads
- lead
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000000872 buffer Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 abstract description 17
- 230000010354 integration Effects 0.000 abstract description 4
- 230000002238 attenuated effect Effects 0.000 abstract description 3
- 230000015654 memory Effects 0.000 description 16
- 230000002829 reductive effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000001934 delay Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12033—Gunn diode
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に半導体集積回路の電
源ノイズの低減に適用して有効な技術に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a technique effective when applied to reducing power supply noise of a semiconductor integrated circuit.
スタティックＲＡＭ （Ｓｔａｔｉｃ Ｒａｎｄｏｍ
Ａｃｃｅｓｓ ）１ｅｍｏｒｙ、以下ＳＲＡＭという）
、特にＭＯＳ−ＳＲＲＡは、近年、高速化および低消費
電力化が進行し、例えばコンピュータのキャッシュメモ
リ、メイン゛メモリ、高速端末メモリに使用されるなど
、その利用分野は、広範囲にわたりつつあり、より一層
の高速化、低消費電力化が求められている。Static RAM (Static Random)
Access) 1 memory, hereinafter referred to as SRAM)
In particular, MOS-SRRA has become faster and has lower power consumption in recent years, and its fields of use are becoming more widespread, such as being used for computer cache memory, main memory, and high-speed terminal memory. There is a need for even higher speeds and lower power consumption.
高速化に適したＭＯＳ−３ＲＡＭは、周辺回路をＣＭ
ＯＳ ’（ＣｏＬＩｌｐｌｅｍｅｎｔａｒｙ ＢＩＯＳ
）、メモリセルを負荷抵抗形ｎチャネルＭＯＳでそれぞ
れ構成したＳＲＡＭが主流となっており、プロセスおよ
び回路面で高速化を追求するための種々の改良がなされ
ている。MOS-3RAM, which is suitable for high-speed operation, allows peripheral circuits to be CM
OS' (CoLIplementary BIOS
) and SRAMs in which the memory cells are each configured with load resistance type n-channel MOS have become mainstream, and various improvements have been made in terms of processes and circuits in order to pursue higher speeds.
例えば、プロセス面では、ポリシリコンで形成したワー
ド線の抵抗による配線遅延を低減するため、ワード線を
シリサイド化したり、上層のＡＩ配線と接続させたりす
る方法や、メモリセルアレイを分割することによって、
−本の選択ワード線に結合したメモリセルの数を減らす
方法などが用いられている。For example, in terms of process, in order to reduce wiring delays due to the resistance of word lines formed of polysilicon, there are methods to silicide the word lines, connect them to upper layer AI wiring, and to divide the memory cell array.
- Methods such as reducing the number of memory cells coupled to one selected word line are used.
また、回路面では、メモリセルを挟む一対のデータ線間
に平衡化回路を設けることによって、情報を読み出す際
、一対のデータ線間の電位差が反転するのに要する時間
を低減する方法などが用いられている。In addition, in terms of circuits, methods are used to reduce the time required for the potential difference between a pair of data lines to reverse when reading information by providing an equalization circuit between a pair of data lines that sandwich a memory cell. It is being
一方、特開昭６１−２１８１３９号や、米国特許第４６
１２５６４号などのように、半導体チップ（以下、チッ
プという）を封止するパッケージの構造を改良すること
によって配線遅延を低減する工夫もなされている。On the other hand, Japanese Patent Application Laid-Open No. 61-218139 and U.S. Patent No. 46
No. 12564 and the like, efforts have been made to reduce wiring delays by improving the structure of a package that seals a semiconductor chip (hereinafter referred to as a chip).
例えば、タブ（ダイパッド部）をなくしたリードフレー
ムのインナリードをポリイミド樹脂などの絶縁フィルム
を介してチップの上面（Ｌｅａｄ ｏｎＣｈｉｐ）
あるいは下面（Ｃｈｉｐ ｏｎ Ｌｅａｄ） に配置
する、いわゆるタブレスリードフレーム方式を用いたパ
ッケージ構造が知られている〈特開昭６１−２１８１３
９号）。For example, the inner lead of a lead frame without a tab (die pad part) is connected to the top surface of the chip (Lead on Chip) through an insulating film such as polyimide resin.
Alternatively, a package structure using the so-called tableless lead frame method, which is arranged on the bottom surface (Chip on Lead), is known (Japanese Patent Laid-Open No. 61-21813).
No. 9).
上記タブレスリードフレーム方式によれば、ボンディン
グワイヤ長を短くすることができるため、配線遅延を低
減することができる。According to the tableless lead frame method, the bonding wire length can be shortened, so wiring delays can be reduced.
また、パッケージ内部のインナリードを長くすることが
できるため、パッケージの耐熱性や耐湿性が向上し、大
形化したチップでも従来寸法のパッケージに搭載するこ
とができる、また、樹脂とリードフレームとの密着性が
向上するため、リフロークラック耐性が向上するなど、
信頼性の面でも多くの利点を有している。In addition, since the inner leads inside the package can be made longer, the heat resistance and moisture resistance of the package are improved, and even larger chips can be mounted in packages with conventional dimensions. This improves adhesion and improves reflow crack resistance, etc.
It also has many advantages in terms of reliability.
ところで、ＳＲＡＭは、情報を保持するメモリセルをマ
トリクス状に配置したメモリセルアレイ、任意のメモリ
セルを選択するための行および列デコーダ、人出力バッ
ファ回路、センスアンプなどの回路によって構成されて
いる。Incidentally, an SRAM is constituted by circuits such as a memory cell array in which memory cells that hold information are arranged in a matrix, row and column decoders for selecting arbitrary memory cells, an output buffer circuit, and a sense amplifier.
ところが、語構成（ワード・ビット構成）が×４ビット
、×８ビットなどの多ビツト出力方式のＳＲＡＭにおい
ては、語構成に対応する複数の出力バッファを同時に動
作させるため、充放電電流が瞬間的に増減するため、チ
ップ内の電源配線やボンディングワイヤなどのインダク
タンス成分によって大きな電源ノイズが発生し、このＮ
源ノイズがチップ内の回路を伝わって入力レベルや動作
電源範囲などの余裕度を低下させてしまうという問題が
発生する。However, in multi-bit output type SRAMs with word configurations (word/bit configurations) such as ×4 bits and ×8 bits, multiple output buffers corresponding to the word configurations are operated simultaneously, so the charging/discharging current is instantaneous. As a result, large power supply noise is generated by inductance components such as power wiring and bonding wires within the chip,
A problem arises in that the source noise is transmitted through the circuits within the chip, reducing margins such as the input level and operating power supply range.
上記電源ノイズは、一般に動作速度が大きい程大きくな
るため、高速ＳＲＡＭでは、特に深刻な問題となる。Generally, the power supply noise increases as the operating speed increases, so it becomes a particularly serious problem in high-speed SRAMs.
そこで、この余裕度の低下を防ぐため、複数の］
出力バッファが同時に動作しないよう、出力バッファの
動作にタイミング差を設定することによって電源ノイズ
の発生を低減させる方法や、電源用パッドとリードとの
間に２本のワイヤを接続する、いわゆるダブルボンディ
ング方式が用いられている。Therefore, in order to prevent this loss of margin, we have developed a method to reduce the generation of power supply noise by setting timing differences in the operation of output buffers so that multiple output buffers do not operate at the same time, and to A so-called double bonding method is used in which two wires are connected between them.
また、電源ノイズによる特性の低下を防止するため、電
源配線を太くするなどの方法も用いられている。Furthermore, in order to prevent the characteristics from deteriorating due to power supply noise, methods such as making the power supply wiring thicker are also used.
しかしながら、本発明者の検討によれば、これらの電源
ノイズ低減対策には、次のような問題がある。However, according to studies by the present inventors, these power supply noise reduction measures have the following problems.
すなわち、出力バラ・ファの動作にタイミング差を設定
する方法は、出力バッファ回路の動作速度を遅くし、Ｓ
ＲＡＭの高速化を妨げる。In other words, the method of setting a timing difference in the operation of the output buffer circuit slows down the operation speed of the output buffer circuit and
Prevents speeding up of RAM.
また、電源配線を太くする方法は、チップ内に占める電
源配線の面積を増大させ、回路の高集積化を妨げる。Further, the method of increasing the thickness of the power supply wiring increases the area occupied by the power supply wiring within the chip, which hinders high integration of the circuit.
さらに、ダブルボンディング方式は、パラトノ位置によ
っては、２本のワイヤをボンディングすることができな
いという位置的な制限があり、また、必ずしも電源ノイ
ズ低減の効果が得られるとはいえない場合もある。Furthermore, the double bonding method has a positional limitation in that two wires cannot be bonded depending on the paratonne position, and it may not necessarily be possible to obtain the effect of reducing power supply noise.
本発明は、上記した問題点に着目してなされたものであ
り、その目的は、集積回路の動作速度を低下させること
なく、電源ノイズを低減することのできる技術を提供す
ることにある。The present invention has been made in view of the above problems, and its purpose is to provide a technique that can reduce power supply noise without reducing the operating speed of an integrated circuit.
また、本発明の他の目的は、集積回路の集積度を低下さ
せることなく、電源ノイズを低減することのできる技術
を提供することにある。Another object of the present invention is to provide a technique that can reduce power supply noise without reducing the degree of integration of an integrated circuit.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、所定数の信号用パッドおよび基準電位に接続
された複数の電源用パッドを備えた半導体チップと、上
記複数の電源用パッドに対応する複数のインナリード部
を互いに接続した電源用リードと、上記所定数の信号用
パッドに対応する所定数の信号用リードとをパッケージ
に封止した半導体装置構造である。That is, a semiconductor chip including a predetermined number of signal pads and a plurality of power supply pads connected to a reference potential, a power supply lead in which a plurality of inner lead parts corresponding to the plurality of power supply pads are connected to each other; This is a semiconductor device structure in which a predetermined number of signal leads corresponding to the predetermined number of signal pads are sealed in a package.
上記した手段によれば、電源ノイズは、基準電位に接続
された電源用パッドから電源用リードを経て他の電源用
パッドに伝達されるため、その間の浮遊容量や抵抗など
によって速やかに減衰する。According to the above-mentioned means, power supply noise is transmitted from the power supply pad connected to the reference potential to other power supply pads via the power supply lead, and is quickly attenuated by the stray capacitance, resistance, etc. therebetween.
第１図は本発明の一実施例である半導体装置の要部分解
斜視図、第２図はこの半導体装置のパッケージ長辺方向
断面図、第３図は同じくパッケージ短辺方向断面図、第
４図はこの半導体装置の回路ブロックを示す半導体チッ
プの略平面図である。FIG. 1 is an exploded perspective view of essential parts of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view along the long side of the package of this semiconductor device, FIG. 3 is a sectional view along the short side of the package, and FIG. The figure is a schematic plan view of a semiconductor chip showing circuit blocks of this semiconductor device.
本実施例の半導体装置のパッケージ構造は、例えば第１
図〜第３図に示すように、タブレスリードフレーム方式
を用いた表面実装形のＳＯＪ（Ｓｍａｌｌ ０ｕｔｌｉ
ｎｅ Ｊ−１ｅａｄ ｐａｃｋａｇｅ） である。The package structure of the semiconductor device of this embodiment is, for example, a first
As shown in Figs.
ne J-1ead package).
パッケージ本体１は、例えばエポキシ樹脂にシリカ（Ｓ
１Ｏｓ）などのフィラーを充填してその熱膨張係数を
シリコンの熱膨張係数に近づけた樹脂によって構成され
、曲げ強度やりフロー・クラックに強い構造になってい
る。The package body 1 is made of silica (S) in epoxy resin, for example.
It is made of resin whose thermal expansion coefficient is close to that of silicon by filling it with a filler such as 1Os), and has a structure that is strong in bending strength and resistant to flow cracks.
パッケージ本体１の長辺方向の両側面からは、断面１字
状に折り曲げ形成された複数本の信号用リード２が外方
に延在している。これらの信号用リード２は、信号用の
外部端子を構成し、その中の一本は、電源（Ｖｃｃ）用
の外部端子である。A plurality of signal leads 2 each bent into a single-character cross section extend outward from both sides in the long side direction of the package body 1 . These signal leads 2 constitute external terminals for signals, and one of them is an external terminal for power supply (Vcc).
各信号用リード２は、例えばＣｕからなり、表面には、
５ｎ−Ｎｉ合金などのメツキを施しである。Each signal lead 2 is made of Cu, for example, and has a surface with
It is plated with 5n-Ni alloy or the like.
パッケージ本体１の内部に埋設された信号用リード２の
上面には、ポリイミド樹脂などからなる矩形の絶縁フィ
ルム３ａが接着されている。各信号用リード２は、この
絶縁フィルム３ａの裏面で水平方向に９０度折り曲げら
れ、Ａｇメツキなどを施したインナリード部の先端が絶
縁フィルム３ａの短辺側から外方に突出されている。A rectangular insulating film 3a made of polyimide resin or the like is adhered to the upper surface of the signal lead 2 buried inside the package body 1. Each signal lead 2 is bent 90 degrees in the horizontal direction on the back surface of the insulating film 3a, and the tip of the inner lead portion, which is plated with Ag, projects outward from the short side of the insulating film 3a.
絶縁フィルム３ａの上面には、電源用リード４が接着さ
れている。この電源用リード４には、パッケージ本体１
の長辺方向と短辺方向とに延びる、例えば７本の分枝５
ａ〜５ｇが互いに接続された状態で延在している。A power supply lead 4 is adhered to the upper surface of the insulating film 3a. This power supply lead 4 is connected to the package body 1.
For example, seven branches 5 extending in the long side direction and short side direction of
a to 5g extend in a state where they are connected to each other.
その中の一本の分枝５ｇは、パッケージ本体１の側面か
ら外方に延在し、前記信号用リード２同様、断面１字状
に折り曲げ形成されている。この分枝５ｇは、基準電位
（Ｖｓｓ）用の外部端子を構成している。One of the branches 5g extends outward from the side surface of the package body 1, and is bent to have a single-character cross section, similar to the signal lead 2. This branch 5g constitutes an external terminal for reference potential (Vss).
一方、残りの分枝５ａ〜５ｆは、電源用リード４のイン
ナリード部を構成し、前記信号用リード２のインナリー
ド部同様、それらの先端が絶縁フィルム３ａの短辺側か
ら外方に突出されている。On the other hand, the remaining branches 5a to 5f constitute the inner lead portion of the power supply lead 4, and like the inner lead portion of the signal lead 2, their tips protrude outward from the short side of the insulating film 3a. has been done.
この電源用リード４は、前記信号用リード２同様、例え
ば表面に５ｎ−Ｎｉ合金などのメツキを施したＣｕから
なり、インナリード部には、Ａｇメツキなどを施しであ
る。Like the signal lead 2, the power supply lead 4 is made of Cu with a 5n-Ni alloy plating on the surface, and the inner lead part is plated with Ag.
電源用リード４の上面には、前記絶縁フィルム３ａと同
一材料、同一寸法の第二の絶縁フィルム３ｂが接着され
ている。A second insulating film 3b made of the same material and having the same dimensions as the insulating film 3a is adhered to the upper surface of the power supply lead 4.
絶縁フィルム３ｂの上面には、シリコン単結晶などから
なるチップ６が接着されている。このチップ６は、上面
側が集積回路形成面となっており、その表面には、平坦
化などを目的として、例えばポリイミド樹脂からなる保
護膜（図示せず）が被着されている。A chip 6 made of silicon single crystal or the like is adhered to the upper surface of the insulating film 3b. The upper surface of this chip 6 is the integrated circuit formation surface, and a protective film (not shown) made of, for example, polyimide resin is adhered to the surface for the purpose of planarization.
このチップ６の集積回路形成面には、例えば２５６に語
×４ビットの語構成を有する１メガピツ） （Ｍｂｉｔ
）ＭＯＳ−３ＲＡＭが形成されている。The integrated circuit forming surface of this chip 6 has, for example, a 1 megabit (Mbit) word structure of 256 words x 4 bits.
) MOS-3RAM is formed.
チップ６の短辺側周縁部には、所定数の信号用パッド７
と、電源用リード４を介して基準電位（Ｖｓｓ） に
接続される１つの電源用バッド８ｆが配設されている。A predetermined number of signal pads 7 are provided on the periphery of the short side of the chip 6.
and one power supply pad 8f connected to the reference potential (Vss) via the power supply lead 4.
また、チップ６の長辺側周縁部には、同じく電源用リー
ド４を介して基準電位に接続される５つの電源用パッド
８ａ〜８ｅが配設されている。Furthermore, five power supply pads 8a to 8e, which are similarly connected to the reference potential via the power supply lead 4, are arranged on the long side peripheral portion of the chip 6.
電源用パッド８３〜８ｆは、電源用リード４の分枝５ａ
〜５ｆとほぼ対応する位置に配設され、電源用パッド８
ａ〜８ｆと分枝５ａ〜５ｆとの間には、Ａｕ、Ｃｕある
いはＡｌなどからなるワイヤ９がそれぞれボンディング
され、両者を電気的に接続している。The power supply pads 83 to 8f are the branches 5a of the power supply lead 4.
It is arranged at a position approximately corresponding to ~5f, and the power supply pad 8
Wires 9 made of Au, Cu, Al, or the like are bonded between a to 8f and branches 5a to 5f, respectively, to electrically connect them.
また、信号用バッド７と信号用リード２との間には、同
じ（Ａｕ、ＣｕあるいはＡＩなどからなるワイヤ９がそ
れぞれボンディングされ、両者を電気的に接続している
。Further, wires 9 made of the same material (Au, Cu, AI, etc.) are bonded between the signal pads 7 and the signal leads 2 to electrically connect them.
第４図に示すように、本実施例の１メガビツト（Ｍｂｉ
ｔ） ＭＯＳ −Ｓ ＲＡＭの回路は、電源用パッド
８ａ〜８ｆと同数のブロックに分割され、各ブロック内
に配設された電源配線１０の基準電位側が電源用パッド
８ａ〜８ｆの各々に接続されている。この電源配線１０
０線幅は、回路内の信号用配線（図示せず）の線幅とほ
ぼ同一であり、面配線は、いずれもストレスマイグレー
ション耐性およびエレクトロマイグレーション耐性を向
上させるため、例えばＡｊ！−３ｉ−Ｃｕ合金で構成さ
れいる。As shown in FIG.
t) The MOS-S RAM circuit is divided into the same number of blocks as the power supply pads 8a to 8f, and the reference potential side of the power supply wiring 10 arranged in each block is connected to each of the power supply pads 8a to 8f. ing. This power wiring 10
The 0 line width is almost the same as the line width of signal wiring (not shown) in the circuit, and surface wiring improves both stress migration resistance and electromigration resistance, so for example, Aj! -3i-Cu alloy.
メモリセルアレイ１１内に配設された電源配線１０の一
端は、例えば電源用パッド８ｂに接続されている。この
メモリセルアレイ１１は、高速化および低消費電力化を
達成するため、例えば３２のメモリマット（図示せず）
に分割されている。One end of the power supply wiring 10 arranged in the memory cell array 11 is connected to, for example, a power supply pad 8b. This memory cell array 11 includes, for example, 32 memory mats (not shown) in order to achieve high speed and low power consumption.
It is divided into
×４ビットの語構成に対応する４つの出力バッファＤ。4 output buffers D corresponding to ×4 bit word structure.
−Ｄコ は、２つのブロックに分割され、例えば出力バ
ッファＤｏ 、 Ｄ＋ 内に配設された電源配線１０
の一端が電源用パッド８ｅに、また、出力バッファＤ２
、 Ｄｓ 内に配設された電源配線１０の一端が電源
用パッド８ｄにそれぞれ接続されている。４つの出力バ
ッファＤ０〜Ｄ３ は、同時に動作するようになってお
り、それらの間に動作タイミング差は設定されていない
。-D is divided into two blocks, for example, the power supply wiring 10 arranged in the output buffers Do and D+.
One end of the power supply pad 8e is connected to the output buffer D2.
, Ds, one end of each power supply wiring 10 is connected to each power supply pad 8d. The four output buffers D0 to D3 operate simultaneously, and no difference in operating timing is set between them.
アドレスバッファ１２内に配設された電源配線１０の一
端は、例えば電源用パッド８ａに、また、その他の周辺
回路からなる論理ブロック１３．１４内に配設された電
源配線１０．１０の各一端は、例えば電源用パッド３ｃ
、３ｆにそれぞれ接続されている。One end of the power supply wiring 10 arranged in the address buffer 12 is connected to, for example, the power supply pad 8a, and one end of each power supply wiring 10.10 arranged in the logic block 13.14 consisting of other peripheral circuits. For example, the power supply pad 3c
, 3f, respectively.
以上の構成からなる本実施例によれば、例えば４つの出
力バッファＤ０〜Ｄ、が同時に動作した際などに瞬間的
に充放電電流が増減して大きな電源ノイズが発生した場
合、この電源ノイズは、出力バッファＤｏ〜Ｄｓ 、電
源用パッドｇｄ、３ａ。According to this embodiment having the above configuration, when large power supply noise occurs due to instantaneous increase or decrease in charging/discharging current when, for example, four output buffers D0 to D operate simultaneously, this power supply noise is , output buffers Do to Ds, power supply pads gd, 3a.
ワイヤ９、電源用リード４、ワイヤ９、他のブロックに
接続された電源用パッド８ａ〜３ｃ、３ｆという長い経
路を経て他のブロックの電源配線１０に伝達されるため
、その間に電源用リード４の浮遊容量や抵抗などによっ
て減衰する。The power is transmitted to the power wiring 10 of the other block through a long path of the wire 9, the power lead 4, the wire 9, and the power pads 8a to 3c, 3f connected to other blocks. It is attenuated by stray capacitance and resistance.
このように、本実施例によれば、電源ノイズの発生源と
なる出力バッファＤ０〜Ｄ、などの回路に動作タイミン
グ差を設定しなくとも、電源ノイズを低減することがで
きるため、１メガピツ）ＭＯ３−５ＲＡＭの高速化が促
進される。In this way, according to this embodiment, power supply noise can be reduced without setting operational timing differences in circuits such as the output buffers D0 to D, which are sources of power supply noise, so that power supply noise can be reduced by 1 megapixel). Speed-up of MO3-5RAM is promoted.
また、電源ノイズによる特性の低下を防止するために電
源配線１０を太くする、などの対策が不要となるため、
１メガビツトＭＯ３−３ＲＡＭの微細化が促進され、そ
のチップ面積を縮小することができる。In addition, there is no need to take measures such as making the power supply wiring 10 thicker to prevent deterioration of characteristics due to power supply noise.
The miniaturization of 1 megabit MO3-3 RAM is promoted, and its chip area can be reduced.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.
例えば、前記実施例では、４つの出力バッファＤ０〜Ｄ
、に２つの電源用パッドを設けたが、出力バッファＤ０
〜Ｄ、の各々に１つずつ電源用パッドを設けてもよい。For example, in the embodiment, four output buffers D0 to D
, two power supply pads are provided in the output buffer D0.
-D, one power supply pad may be provided for each of.
また、語構成が×８ビットのＳＲＡＭに適用することも
できる。Further, the present invention can also be applied to an SRAM with a word structure of x8 bits.
パッケージ構造は、ＳＯＪのみならず、ＤＩＰ（Ｄｕａ
ｌ Ｉｎ−１ｉｎｅ Ｐａｃｋａｇｅ）やＰ Ｌ ＣＣ
（Ｐｌａｓｔｉｃしｅａｄｅｄ Ｃｈｉｐ Ｃａｒｒｉ
ｅｒ）などであってもよい。The package structure is not only SOJ but also DIP (Dua
l In-1ine Package) and P L CC
(Plastic and leaded Chip Carri
er) etc.
前記実施例では、チップの下方に電源用リードを配置し
、さらにその下方に信号用リードを配置したが、それら
の配置は任意に変更してよい。In the embodiment described above, the power supply lead is arranged below the chip, and the signal lead is further arranged below it, but the arrangement thereof may be changed as desired.
以上の説明では、主として本発明者によってなされた発
明をその背景となった利用分野であるＭＯＳ−３ＲＡＭ
に適用した場合について説明したが、本発明は、それに
限定されるものではなく、多数の出力が同時に動作する
集積回路を備えた半導体装置であれば、ＤＲＡＭなどの
他の半導体メモリや、マイクロコンピユータなどの論理
ＬＳＩにも適用することができる。In the above explanation, the invention made by the present inventor will be mainly explained in relation to the field of application, MOS-3RAM, which is the background of the invention.
Although the present invention is not limited thereto, the present invention can be applied to other semiconductor memories such as DRAM, microcomputers, etc. as long as it is a semiconductor device equipped with an integrated circuit in which a large number of outputs operate simultaneously. It can also be applied to logic LSIs such as.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、所定数の信号用パッド右よび基準電位に接続
される複数の電源用パッドを備えた半導体チップと、上
記複数の電源用パッドに対応する複数のインナリード部
を互いに接続した電源用リードと、上記所定数の信号用
パッドに対応する所定数の信号用リードとをパッケージ
に封止した半導体装置構造とすることにより、半導体装
置の高速化、高集積化を妨げることなく、電源ノイズを
低減することができる。That is, a semiconductor chip includes a plurality of power supply pads connected to a predetermined number of signal pads and a reference potential, and a power supply lead in which a plurality of inner lead parts corresponding to the plurality of power supply pads are connected to each other. By creating a semiconductor device structure in which a predetermined number of signal leads corresponding to the predetermined number of signal pads are sealed in a package, power supply noise can be reduced without hindering the speedup and high integration of semiconductor devices. can do.
第１図は本発明の一実施例である半導体装置の要部分解
斜視図、
第２図はこの半導体装置のパッケージ長辺方向断面図、
第３図は同じくパッケージ短辺方向断面図、第４図はこ
の半導体装置の回路ブロックを示す半導体チップの略平
面図である。
ｌ・・・パッケージ本体、２・・・信号用リード、３ａ
、３ｂ・・・絶縁フィルム、４・・・電源用リード、５
ａ〜５ｇ・・・分枝、６・・・半導体チップ、７・・・
信号用パッド、８ａ〜８ｆ・・・電源用パッド、９・・
・ワイヤ、１０・・・電源配線（Ｖｓｓ） １１・
・・メモリセルアレイ、１２・・・アドレスバッファ、
１３．１４・・・論理ブロック、Ｄ０〜Ｄ、・・・出力
バッフ第１図
代理人 弁理士 筒 井 大 和
ｂ９
第
図
第
図
第
図FIG. 1 is an exploded perspective view of essential parts of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view along the long side of the package of this semiconductor device, FIG. 3 is a cross-sectional view along the short side of the package, and FIG. The figure is a schematic plan view of a semiconductor chip showing circuit blocks of this semiconductor device. l...Package body, 2...Signal lead, 3a
, 3b... Insulating film, 4... Power supply lead, 5
a~5g...branch, 6...semiconductor chip, 7...
Signal pads, 8a to 8f...Power supply pads, 9...
・Wire, 10...Power supply wiring (Vss) 11・
...Memory cell array, 12...Address buffer,
13.14...Logic block, D0-D,...Output buffer Figure 1 Agent Patent attorney Daiwa Tsutsui b9 Figure Figure Figure
Claims (1)
よび基準電位に接続された複数の電源用パッドを備えた
半導体チップと、前記複数の電源用パッドに対応する複
数のインナリード部を互いに接続した電源用リードと、
前記所定数の信号用パッドに対応する所定数の信号用リ
ードとをパッケージに封止したことを特徴とする半導体
装置。 ２、半導体チップと、電源用リードと、信号用リードと
を絶縁フィルムを介して互いに絶縁させたことを特徴と
する請求項１記載の半導体装置。 ３、複数の出力バッファを備えていることを特徴とする
請求項１記載の半導体装置。[Scope of Claims] 1. A semiconductor chip having a predetermined number of signal pads and a plurality of power supply pads connected to a reference potential around an integrated circuit forming area, and a plurality of power supply pads corresponding to the plurality of power supply pads. A power supply lead whose inner lead parts are connected to each other,
A semiconductor device characterized in that a predetermined number of signal leads corresponding to the predetermined number of signal pads are sealed in a package. 2. The semiconductor device according to claim 1, wherein the semiconductor chip, the power supply lead, and the signal lead are insulated from each other via an insulating film. 3. The semiconductor device according to claim 1, further comprising a plurality of output buffers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63181370A JPH0231454A (en) | 1988-07-20 | 1988-07-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63181370A JPH0231454A (en) | 1988-07-20 | 1988-07-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0231454A true JPH0231454A (en) | 1990-02-01 |
Family
ID=16099540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63181370A Pending JPH0231454A (en) | 1988-07-20 | 1988-07-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0231454A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0411761A (en) * | 1990-04-27 | 1992-01-16 | Toshiba Corp | Resin sealing type semiconductor device |
| EP0503201A3 (en) * | 1990-12-20 | 1994-03-16 | Toshiba Kk | |
| EP0620593A1 (en) * | 1993-04-16 | 1994-10-19 | Kabushiki Kaisha Toshiba | Semiconductor device with smaller package |
| US5592020A (en) * | 1993-04-16 | 1997-01-07 | Kabushiki Kaisha Toshiba | Semiconductor device with smaller package having leads with alternating offset projections |
| JP2009032899A (en) * | 2007-07-27 | 2009-02-12 | Renesas Technology Corp | Semiconductor device |
-
1988
- 1988-07-20 JP JP63181370A patent/JPH0231454A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0411761A (en) * | 1990-04-27 | 1992-01-16 | Toshiba Corp | Resin sealing type semiconductor device |
| EP0503201A3 (en) * | 1990-12-20 | 1994-03-16 | Toshiba Kk | |
| US5473514A (en) * | 1990-12-20 | 1995-12-05 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board |
| US5613295A (en) * | 1990-12-20 | 1997-03-25 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board and method for manufacturing same |
| US5646830A (en) * | 1990-12-20 | 1997-07-08 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board |
| US5715147A (en) * | 1990-12-20 | 1998-02-03 | Kabushiki Kaisha Toshiba | Semiconductor device having an interconnecting circuit board |
| EP0620593A1 (en) * | 1993-04-16 | 1994-10-19 | Kabushiki Kaisha Toshiba | Semiconductor device with smaller package |
| US5592020A (en) * | 1993-04-16 | 1997-01-07 | Kabushiki Kaisha Toshiba | Semiconductor device with smaller package having leads with alternating offset projections |
| US5801433A (en) * | 1993-04-16 | 1998-09-01 | Kabushiki Kaisha Toshiba | Semiconductor device with smaller package |
| JP2009032899A (en) * | 2007-07-27 | 2009-02-12 | Renesas Technology Corp | Semiconductor device |
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