JPH0436115Y2 - - Google Patents
Info
- Publication number
- JPH0436115Y2 JPH0436115Y2 JP1986154185U JP15418586U JPH0436115Y2 JP H0436115 Y2 JPH0436115 Y2 JP H0436115Y2 JP 1986154185 U JP1986154185 U JP 1986154185U JP 15418586 U JP15418586 U JP 15418586U JP H0436115 Y2 JPH0436115 Y2 JP H0436115Y2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- bumps
- wiring board
- metal bumps
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010931 gold Substances 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 description 10
- 239000000758 substrate Substances 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986154185U JPH0436115Y2 (de) | 1986-10-07 | 1986-10-07 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986154185U JPH0436115Y2 (de) | 1986-10-07 | 1986-10-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6359326U JPS6359326U (de) | 1988-04-20 |
JPH0436115Y2 true JPH0436115Y2 (de) | 1992-08-26 |
Family
ID=31073750
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986154185U Expired JPH0436115Y2 (de) | 1986-10-07 | 1986-10-07 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0436115Y2 (de) |
-
1986
- 1986-10-07 JP JP1986154185U patent/JPH0436115Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6359326U (de) | 1988-04-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5942795A (en) | Leaded substrate carrier for integrated circuit device and leaded substrate carrier device assembly | |
JP3704864B2 (ja) | 半導体素子の実装構造 | |
US6303992B1 (en) | Interposer for mounting semiconductor dice on substrates | |
TW501208B (en) | Semiconductor device and manufacturing method of the same | |
JP3481444B2 (ja) | 半導体装置及びその製造方法 | |
US20060192294A1 (en) | Chip scale package having flip chip interconnect on die paddle | |
JPS58101493A (ja) | 基板 | |
JPH0332914B2 (de) | ||
US6420787B1 (en) | Semiconductor device and process of producing same | |
US5243497A (en) | Chip on board assembly | |
JPH0432541B2 (de) | ||
JPH0864635A (ja) | 半導体装置 | |
JPH0436115Y2 (de) | ||
JPH05326817A (ja) | マルチチップパッケージ | |
JP2986661B2 (ja) | 半導体装置の製造方法 | |
JPS63168028A (ja) | 微細接続構造 | |
JP2974840B2 (ja) | 半導体素子の実装方法 | |
JP3006957B2 (ja) | 半導体装置の実装体 | |
JP2000252320A (ja) | 半導体装置およびその製造方法 | |
JP2830221B2 (ja) | ハイブリッド集積回路のマウント構造 | |
JP2652222B2 (ja) | 電子部品搭載用基板 | |
JPH11204565A (ja) | 半導体装置 | |
JPH0583186B2 (de) | ||
JPS6057957A (ja) | 接続構造 | |
JPS63185035A (ja) | 半導体装置 |