JPH04360550A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04360550A JPH04360550A JP3136429A JP13642991A JPH04360550A JP H04360550 A JPH04360550 A JP H04360550A JP 3136429 A JP3136429 A JP 3136429A JP 13642991 A JP13642991 A JP 13642991A JP H04360550 A JPH04360550 A JP H04360550A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- electrodes
- semiconductor device
- chip
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000012360 testing method Methods 0.000 claims abstract description 28
- 238000007689 inspection Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置に関し、特に
、半導体チップの特性検査における精度の向上を可能と
する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device that enables improved accuracy in testing the characteristics of semiconductor chips.
【０００２】0002
【従来の技術】従来の半導体装置は、図３に平面図が示
されるように、ウェハー状態において、各ボンディング
用電極６４〜７５に対して、それぞれ対応する針状電極
７６〜８７が接続され、半導体チップ６２の特性検査が
実施されて、良品の半導体チップが選出される。その後
、ダイシング工程を経て、個々の半導体チップに分離さ
れ、マウント工程、ボンディング工程および封入工程等
の組立て工程を経過して、製品の特性検査が実施されて
良品が選択され、最終的に商品としての半導体装置が完
成される。2. Description of the Related Art In a conventional semiconductor device, as shown in a plan view in FIG. 3, in a wafer state, corresponding needle electrodes 76 to 87 are connected to bonding electrodes 64 to 75, respectively. A characteristic test of the semiconductor chips 62 is performed, and non-defective semiconductor chips are selected. After that, it goes through a dicing process, is separated into individual semiconductor chips, goes through assembly processes such as mounting process, bonding process, and encapsulation process, and then the product characteristics are inspected to select non-defective products, and finally as a product. A semiconductor device is completed.
【０００３】0003
【発明が解決しようとする課題】上述した従来の半導体
装置においては、半導体素子の配線電極と接続されてい
るボンディング用電極の数により、検査することのでき
る特性検査項目の内容が限定されてしまうために、結果
的に特性検査の精度が悪いという欠点があり、また、特
性検査項目の内容を充実させるために、ボンディング用
電極を追加すると、半導体チップの面積が大きくなって
しまうという欠点がある。[Problem to be Solved by the Invention] In the above-mentioned conventional semiconductor device, the content of characteristic inspection items that can be inspected is limited depending on the number of bonding electrodes connected to the wiring electrodes of the semiconductor element. Therefore, there is a drawback that the accuracy of the characteristic test is poor as a result, and there is also a drawback that the area of the semiconductor chip increases when bonding electrodes are added to enrich the contents of the characteristic test items. .
【０００４】0004
【課題を解決するための手段】第１の発明の半導体装置
は、ウェハー状態において形成される半導体装置におい
て、半導体チップの半導体素子の周辺に設けられるボン
ディング用電極と、前記半導体装置のダイシング・ライ
ン部分に、前記半導体素子内の任意の配線電極に接続し
て設けられる少なくとも一つ以上の検査用電極と、を備
えて構成される。[Means for Solving the Problems] A semiconductor device of a first aspect of the invention is a semiconductor device formed in a wafer state, which includes a bonding electrode provided around a semiconductor element of a semiconductor chip, and a dicing line of the semiconductor device. The semiconductor device is configured to include at least one inspection electrode connected to an arbitrary wiring electrode in the semiconductor element.
【０００５】また、第２の発明の半導体装置は、ウェハ
ー状態において形成される半導体装置において、半導体
チップの半導体素子の周辺に設けられるボンディング用
電極と、前記半導体装置のダイシング・ライン部分に、
前記半導体素子内の任意の配線電極ならびに前記半導体
チップ上の単体デバイスの配線電極に接続して設けられ
る少なくとも一つ以上の検査用電極と、を備えて構成さ
れる。Further, in a semiconductor device of a second aspect of the invention, in a semiconductor device formed in a wafer state, a bonding electrode provided around a semiconductor element of a semiconductor chip, and a dicing line portion of the semiconductor device,
The semiconductor device is configured to include an arbitrary wiring electrode within the semiconductor element and at least one inspection electrode connected to a wiring electrode of a single device on the semiconductor chip.
【０００６】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.
【０００７】図１は本発明の第１の実施例を示す平面図
である。図１に示されるように、本実施例においては、
半導体チップ１の半導体素子の周辺には、ボンディング
用電極３〜１０が設けられており、ダイシング・ライン
２には、半導体チップ１上の任意の配線電極に接続され
ている検査用電極１１〜１４が設けられている。FIG. 1 is a plan view showing a first embodiment of the present invention. As shown in FIG. 1, in this example,
Bonding electrodes 3 to 10 are provided around the semiconductor element of the semiconductor chip 1, and testing electrodes 11 to 14 connected to arbitrary wiring electrodes on the semiconductor chip 1 are provided on the dicing line 2. is provided.
【０００８】半導体チップ１を、ウェハー状態において
特性検査を実施する際には、ボンディング用電極３〜１
０および検査用電極１１〜１４に対して、対応する針状
電極１５〜２６を接続して特性検査を行うことにより、
半導体チップ１に対する特性検査項目の内容の充実を図
ることができ、より一層精度よく半導体チップ１の良否
を判定することが可能となる。また、半導体チップ１に
対するボンディング用電極３〜１０の一辺を１００μｍ
とし、図３に示されるような従来の半導体チップ６２の
面積と比較すると、約４４．７％（１−３３６４［μｍ
］２ ／６０８４［μｍ］２ ）のチップ面積の縮小化
を図ることができ、且つ同等の特性検査項目の検査を実
施するこができるという特徴がある。When testing the characteristics of the semiconductor chip 1 in a wafer state, the bonding electrodes 3 to 1 are
By connecting the corresponding needle electrodes 15 to 26 to the test electrodes 11 to 14 and testing the characteristics,
It is possible to enrich the contents of the characteristic inspection items for the semiconductor chip 1, and it becomes possible to determine the quality of the semiconductor chip 1 with even higher accuracy. Also, one side of the bonding electrodes 3 to 10 for the semiconductor chip 1 is 100 μm.
When compared with the area of the conventional semiconductor chip 62 as shown in FIG.
] 2 /6084 [μm] 2 ), and it is possible to perform tests for the same characteristic test items.
【０００９】次に、本発明の第２の実施例について説明
する。図２は本発明の第２の実施例を示す平面図である
。図２に示されるように、本実施例においては、半導体
チップ２７の半導体素子の周辺には、ボンディング用電
極２９〜３６が設けられており、また、半導体チップ１
上の検査用トランジスタ５９、検査用抵抗６０および検
査用コンデンサ６１の配線電極に接続されている検査用
電極３７〜４３がダイシング・ライン２８に設けられて
る。Next, a second embodiment of the present invention will be described. FIG. 2 is a plan view showing a second embodiment of the invention. As shown in FIG. 2, in this embodiment, bonding electrodes 29 to 36 are provided around the semiconductor element of the semiconductor chip 27.
Test electrodes 37 to 43 connected to the wiring electrodes of the test transistor 59, test resistor 60, and test capacitor 61 are provided on the dicing line 28.
【００１０】この半導体チップ２７を、ウェハー状態に
おいて特性検査を実施する際には、ボンディング用電極
２９〜３６に対して、対応する針状電極４４〜５１を接
続して、半導体チップ２７の特性検査を実施すると同時
に、検査用電極３７〜４３に対し、対応する針状電極５
２〜５８を接続し、検査用トランジスタ５９、検査用抵
抗６０および検査用コンデンサ６１等の単体デバイスの
特性検査をも同時に実施することができる。これにより
、各半導体チップ対応の単体デバイスの諸特性のデータ
をも得ることが可能となり、不良品解析の有効な手段の
一つを提供することができる。When testing the characteristics of the semiconductor chip 27 in a wafer state, the corresponding needle electrodes 44 to 51 are connected to the bonding electrodes 29 to 36, and the characteristics of the semiconductor chip 27 are tested. At the same time, the corresponding needle electrodes 5 are attached to the test electrodes 37 to 43.
By connecting the transistors 2 to 58, characteristics of individual devices such as the test transistor 59, the test resistor 60, and the test capacitor 61 can be tested at the same time. This makes it possible to obtain data on various characteristics of individual devices corresponding to each semiconductor chip, and provides one of the effective means for defective product analysis.
【００１１】[0011]
【発明の効果】以上説明したように、本発明は、半導体
素子の周辺にボンディング用電極を設けるとともに、ダ
イシング・ライン部分に、前記半導体素子内の任意の配
線電極に接続されている検査用電極を少なくとも一つ以
上設けることにより、半導体チップの占有面積を必要最
低限のチップ面積に抑制しつつ半導体チップの特性検査
項目を増すことが可能となり、より精度の高い特性検査
を通じて、より良品度の高い半導体チップを選出するこ
とができるという効果がある。As explained above, the present invention provides a bonding electrode around a semiconductor element, and a test electrode connected to an arbitrary wiring electrode in the semiconductor element at a dicing line portion. By providing at least one of This has the effect that high-quality semiconductor chips can be selected.
【図１】本発明の第１の実施例を示す平面図である。FIG. 1 is a plan view showing a first embodiment of the present invention.
【図２】本発明の第２の実施例を示す平面図である。FIG. 2 is a plan view showing a second embodiment of the invention.
【図３】従来例を示す平面図である。FIG. 3 is a plan view showing a conventional example.
１、２７、６２ 半導体チップ
２、２８、６３ ダイシング・ライン３〜１０、
２９〜３６、６４〜７５ ボンディング用電極
１１〜１４、３７〜４３ 検査用電極１５〜２６
、４４〜５８、７６〜８７ 針状電極５９
検査用トランジスタ
６０ 検査用抵抗
６１ 検査用コンデンサ1, 27, 62 semiconductor chips 2, 28, 63 dicing lines 3 to 10,
29-36, 64-75 Bonding electrodes 11-14, 37-43 Inspection electrodes 15-26
, 44-58, 76-87 needle electrode 59
Testing transistor 60 Testing resistor 61 Testing capacitor
Claims (2)
体装置において、半導体チップの半導体素子の周辺に設
けられるボンディング用電極と、前記半導体装置のダイ
シング・ライン部分に、前記半導体素子内の任意の配線
電極に接続して設けられる少なくとも一つ以上の検査用
電極と、を備えることを特徴とする半導体装置。1. In a semiconductor device formed in a wafer state, a bonding electrode provided around a semiconductor element of a semiconductor chip, a dicing line portion of the semiconductor device, and an arbitrary wiring electrode within the semiconductor element. 1. A semiconductor device comprising: at least one testing electrode that is connected and provided.
体装置において、半導体チップの半導体素子の周辺に設
けられるボンディング用電極と、前記半導体装置のダイ
シング・ライン部分に、前記半導体素子内の任意の配線
電極ならびに前記半導体チップ上の単体デバイスの配線
電極に接続して設けられる少なくとも一つ以上の検査用
電極と、を備えることを特徴とする半導体装置。2. In a semiconductor device formed in a wafer state, a bonding electrode provided around a semiconductor element of a semiconductor chip and a dicing line portion of the semiconductor device are provided with arbitrary wiring electrodes in the semiconductor element and a bonding electrode provided around the semiconductor element of the semiconductor chip. A semiconductor device comprising: at least one inspection electrode connected to a wiring electrode of a single device on the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3136429A JPH04360550A (en) | 1991-06-07 | 1991-06-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3136429A JPH04360550A (en) | 1991-06-07 | 1991-06-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04360550A true JPH04360550A (en) | 1992-12-14 |
Family
ID=15174940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3136429A Pending JPH04360550A (en) | 1991-06-07 | 1991-06-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04360550A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007042967A (en) * | 2005-08-05 | 2007-02-15 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| US7372072B2 (en) * | 2004-12-15 | 2008-05-13 | Infineon Technologies Ag | Semiconductor wafer with test structure |
-
1991
- 1991-06-07 JP JP3136429A patent/JPH04360550A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7372072B2 (en) * | 2004-12-15 | 2008-05-13 | Infineon Technologies Ag | Semiconductor wafer with test structure |
| JP2007042967A (en) * | 2005-08-05 | 2007-02-15 | Matsushita Electric Ind Co Ltd | Semiconductor device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19990810 |