JPH04359545A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To expand the substantial electrical contact area of the title device by a method wherein the film thickness of an interlayer insulating film is set in such a way that the film thickness in the vertical direction with reference to a substrate is larger than the film thickness in the horizontal direction. CONSTITUTION:A prescribed treatment is executed to a silicon substrate 1; a gate oxide film 2, a gate electrode 3 and an n-type impurity diffusion layer 4 are formed. Then, an interlayer insulating film 5 in which its film thickness F in the vertical direction with reference to the silicon substrate 1 is larger than its film thickness G in the horizontal direction (F>=G) is deposited on the silicon substrate 1. After the interlayer insulating film 5 has been formed in this manner, a patterning operation is executed so that the gate electrode 3 and the n-type impurity diffusion layer 4 can be connected electrically. Then, an anisotropically reactive ion etching operation is executed; the width I of an insulating-film residue 6 in the n-type impurity diffusion layer 4 is reduced. Thereby, the substantial electrical contact area of the title device can be expanded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that enables good electrical connection even between two conductive layers with a large step difference.

0002

2. Description of the Related Art Conventionally, in semiconductor devices such as LSIs, when connecting two conductive layers that are in a stepped state, a conductive thin film is deposited on top of them for wiring. FIG. 3 is a plan view showing an electrical connection between two conductive layers connected by a conventional semiconductor device manufacturing method. In particular, FIG. 3A is a plan view of the electrical connection, and FIG. ) is a diagram showing the A1-A2 cross section in FIG. 3(a). In the figure, 1 is a p-type silicon substrate, 2 is a gate oxide film,
3 is a gate electrode, 4 is an n-type impurity diffusion layer, 5 is an interlayer insulating film, 6 is an insulator residue, 7 is a polycrystalline silicon wiring that electrically connects the gate electrode 3 and the n-type impurity diffusion layer 4 at the same time, 8 is a resist.

Next, a method of manufacturing a semiconductor device having the above structure will be explained with reference to FIGS. 4(a) to 4(d). First, as shown in FIG. 4(a), a silicon substrate 1 is prepared in advance.
By applying a field effect transistor formation process to
For example, a 200 angstrom gate oxide film 2, 2,
A gate electrode 3 with a thickness of 0.000 angstroms and an n-type impurity diffusion layer 4 are formed. Next, as shown in FIG. 4B, an interlayer insulating film 5 having good step coverage is deposited to a thickness of, for example, 2,000 angstroms by CVD. At this time, the interlayer insulating film 5 is formed so that the film thickness B in the vertical direction and the film thickness C in the horizontal direction relative to the silicon substrate 1 are equal (B=C). Next, as shown in FIG. 4(c), a resist 8 is used so that the gate electrode 3 and the n-type impurity diffusion layer 4 can be electrically connected at the same time by a polycrystalline silicon wiring 7 (see FIG. 3(b)). After patterning, the interlayer insulating film 5 is etched by anisotropic reactive etching. At this time, as shown in FIG. 4(c), the interlayer insulation film thickness D at the stepped portion is approximately 2.2 times larger than the interlayer insulation film thickness B at the flat portion.
Since the thickness is 0.00 angstroms, an insulating residue 6 having a width E of about 2,000 angstroms is formed on the n-type impurity diffusion layer 4 as shown in FIG. 4(d). and,
By forming conductive polycrystalline silicon wiring 7, two stepped conductor layers can be electrically connected and wired.

FIG. 5 is a cross-sectional view showing an electrical connection at a stepped portion where two conductive layers are connected by a conventional semiconductor device manufacturing method. In the figure, 9 is a first interlayer insulating film;
10 is a first layer wiring, 11 is a second interlayer insulating film, 12 is an insulating film residue, and 13 is a second layer wiring. Next, a method for manufacturing a semiconductor device having the above configuration will be described in FIGS.
Similar to the manufacturing method shown in (d), insulating film residue 12 is generated at the stepped portion of the electrical connection portion. To further explain this conventional example, after performing a process for forming a field effect transistor, a first interlayer insulating film 9 having good step coverage is formed. After a first layer wiring 10 of polycrystalline silicon is deposited to have a low resistance, patterning is performed using photolithography. After depositing the second interlayer insulating film 11, it is patterned and anisotropically etched to form desired holes. At this time, insulating film residue 12 is generated at the step portion. Then, the second layer wiring 13 is connected to the first layer wiring 10.

[0005]

[Problems to be Solved by the Invention] As described above, in the conventional manufacturing method of semiconductor devices, the electrical contact surface has a step difference.
When electrical connections are made in that area, even after anisotropic reactive ion etching, even if normal patterning is achieved in the photolithography process, the thickness of the interlayer insulating film remains An insulating film corresponding to the area remains, and no connection is made in that part, reducing the actual electrical contact area. Further, if patterning misalignment occurs in the photolithography process, good electrical connection cannot be achieved as shown in FIG. 6(b). Moreover, since miniaturization will progress further in the future, there is a problem that this insulating film residue cannot be ignored.

This invention was made to solve the above-mentioned problems, and its purpose is to widen the substantial contact area even when the electrical contact surface is stepped. .

[0007]

[Means for Solving the Problems] In the method of manufacturing a semiconductor device according to the present invention, the film thickness of the interlayer insulating film is such that the film thickness F in the direction perpendicular to the substrate is larger than the film thickness G in the horizontal direction (F ≧
G) It was made so that it would become.

[0008]

According to the present invention, when the interlayer insulating film is subjected to anisotropic ion etching, the residue of the insulating film caused by the step difference is reduced, and the substantial electrical contact area can be expanded.

[0009]

[Embodiment] FIG. 1 is a sectional view showing an embodiment of the method for manufacturing a semiconductor device according to the present invention, and the manufacturing process is illustrated in FIG.
This will be explained with reference to a) to FIG. 1(d). First, Figure 1 (a
), the silicon substrate 1 is subjected to a predetermined treatment,
Gate oxide film 2 with a film thickness of 200 angstroms, film thickness 2
,000 angstroms of gate electrode 3 and n-type impurity diffusion layer 4 are formed. Next, as shown in FIG. 1(b), a film thickness F in a direction perpendicular to the silicon substrate (hereinafter simply referred to as on-substrate film thickness) is formed on this silicon substrate 1 under the following processing conditions A or B. An interlayer insulating film 5 whose thickness in the horizontal direction (hereinafter simply referred to as sidewall thickness) is larger than G (F≧G) is deposited by CVD. Note that, regarding processing condition A, the interlayer insulating film is formed at a deposition temperature of 500 degrees Celsius or less. When the deposition temperature is 500 degrees C, film thickness G/film thickness F = 0
．． 8, so when the film thickness F on the substrate is 2,000 angstroms, the sidewall film thickness G is 1,600 angstroms. When the deposition temperature is 400 degrees Celsius, the film thickness G/film thickness F=0.6, so the film thickness F on the substrate is 2.0
00 angstroms, the sidewall thickness G is 1,2
00 angstroms. Regarding processing condition B, the interlayer insulating film contains about 2% to 7% of phosphorus as an impurity. The relationship is film thickness G/film thickness F=0.5, so if the film thickness F on the substrate is 2,000 angstroms, the sidewall film thickness G will be 1,000 angstroms. Furthermore, it goes without saying that the same effect can be obtained even if arsenic is used as the impurity.

After forming the interlayer insulating film 5 under the above-mentioned processing conditions, as shown in FIG. Apply patterning. Next, as shown in FIG. 1D, by performing anisotropic reactive ion etching, the width I of the insulating film residue 6 on the n-type impurity diffusion layer 4 can be reduced. The width I of the insulating film residue 6 depends on the amount of overetching, but when the interlayer insulating film is formed under processing conditions A and the deposition temperature is 500 angstroms, the width I of the insulating film residue 6 is 1,600 angstroms. about angstrom, deposition temperature 4
If the temperature is 00 degrees Celsius, the width I of the insulating film residue 6 will be about 1,200 angstroms. Further, when the interlayer insulating film is formed under processing condition B, and 2% to 7% of phosphorus is included as an impurity, the width I of the insulating film residue becomes about 1,000 angstroms. In addition, FIG. 2 is a cross-sectional view when an electrical connection is made at a step portion where two conductive layers are connected, and an insulating film may be deposited on the interlayer insulating film under the processing conditions shown in FIG. Of course. If a conductive thin film is formed after such treatment, the effective area of the pores will increase, so that a good electrical connection can be obtained.

[0011]

As described above, according to the present invention, the interlayer insulating film is formed so that the thickness in the horizontal direction to the substrate is smaller than the thickness in the vertical direction to the substrate. When anisotropic reactive ion etching is performed, it is possible to reduce the amount of insulating film residue that is generated due to the step difference, which has the effect of expanding the substantial electrical contact area.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view of a stepped portion processed by the method for manufacturing the semiconductor device shown in FIG. 1;

FIG. 3 is a diagram showing a conventional method for manufacturing a semiconductor device.

FIG. 4 is a cross-sectional view showing each manufacturing process of a conventional semiconductor device manufacturing method.

FIG. 5 is a cross-sectional view of a stepped portion processed by a conventional semiconductor device manufacturing method.

FIG. 6 is a cross-sectional view of a semiconductor device for explaining a conventional semiconductor device manufacturing method.

[Explanation of symbols]

1 P-type silicon substrate 2 Gate oxide film 3 Gate electrode 4 N-type impurity diffusion layer 5 Interlayer insulation film 6 Insulating film residue 8 Resist I Width of insulating film residue F Film thickness perpendicular to the substrate G Film thickness in the horizontal direction to the substrate

Claims (1)

[Claims] Claim 1: In a semiconductor device in which the electrical contact surface is stepped, an interlayer insulating film is deposited where the film thickness F in the vertical direction with respect to the substrate is thicker than the film thickness G in the horizontal direction (F≧G). a step of forming an electrical connection hole by anisotropic reactive ion etching on the interlayer insulating film in the stepped portion, and a step of depositing a conductive thin film in the electrical connection hole to form the step condition. 1. A method for manufacturing a semiconductor device, comprising the step of electrically connecting two certain conductive layers.