JPH0435936B2 - - Google Patents

Info

Publication number
JPH0435936B2
JPH0435936B2 JP11443582A JP11443582A JPH0435936B2 JP H0435936 B2 JPH0435936 B2 JP H0435936B2 JP 11443582 A JP11443582 A JP 11443582A JP 11443582 A JP11443582 A JP 11443582A JP H0435936 B2 JPH0435936 B2 JP H0435936B2
Authority
JP
Japan
Prior art keywords
data
time slot
station
master station
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11443582A
Other languages
English (en)
Japanese (ja)
Other versions
JPS595761A (ja
Inventor
Osamu Nakamura
Teruyoshi Mita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11443582A priority Critical patent/JPS595761A/ja
Publication of JPS595761A publication Critical patent/JPS595761A/ja
Publication of JPH0435936B2 publication Critical patent/JPH0435936B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/427—Loop networks with decentralised control
    • H04L12/43—Loop networks with decentralised control with synchronous transmission, e.g. time division multiplex [TDM], slotted rings

Landscapes

  • Small-Scale Networks (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
JP11443582A 1982-06-30 1982-06-30 マルチドロツプ時の速度調整方式 Granted JPS595761A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11443582A JPS595761A (ja) 1982-06-30 1982-06-30 マルチドロツプ時の速度調整方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11443582A JPS595761A (ja) 1982-06-30 1982-06-30 マルチドロツプ時の速度調整方式

Publications (2)

Publication Number Publication Date
JPS595761A JPS595761A (ja) 1984-01-12
JPH0435936B2 true JPH0435936B2 (enrdf_load_stackoverflow) 1992-06-12

Family

ID=14637649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11443582A Granted JPS595761A (ja) 1982-06-30 1982-06-30 マルチドロツプ時の速度調整方式

Country Status (1)

Country Link
JP (1) JPS595761A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6374344A (ja) * 1986-09-18 1988-04-04 Tech Res & Dev Inst Of Japan Def Agency アナログ信号伝達装置
JPS6374345A (ja) * 1986-09-18 1988-04-04 Tech Res & Dev Inst Of Japan Def Agency アナログ信号伝達装置

Also Published As

Publication number Publication date
JPS595761A (ja) 1984-01-12

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