JPH04359187A - Computer clock system - Google Patents
Computer clock systemInfo
- Publication number
- JPH04359187A JPH04359187A JP3133130A JP13313091A JPH04359187A JP H04359187 A JPH04359187 A JP H04359187A JP 3133130 A JP3133130 A JP 3133130A JP 13313091 A JP13313091 A JP 13313091A JP H04359187 A JPH04359187 A JP H04359187A
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- Prior art keywords
- time
- clock
- computer
- common clock
- common
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- 238000012790 confirmation Methods 0.000 claims abstract description 7
- 230000002159 abnormal effect Effects 0.000 abstract description 4
- 230000036449 good health Effects 0.000 abstract 2
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000002131 composite material Substances 0.000 description 2
- 101000582320 Homo sapiens Neurogenic differentiation factor 6 Proteins 0.000 description 1
- 102100030589 Neurogenic differentiation factor 6 Human genes 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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Abstract
Description
[発明の目的] [Purpose of the invention]
【0001】0001
【産業上の利用分野】本発明は、複合系計算機システム
における計算機の時刻を合わせる計算機時計システムに
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer clock system for adjusting the time of computers in a complex computer system.
【0002】0002
【従来の技術】一般に、複合系計算機システムでは、各
々の計算機が内部時計を備え、各々の計算機は自計算機
の内部時計の時刻を正として動作している。この場合、
各々の計算機の内部時計の時刻を合わせるために複数の
計算機から読み出し可能な共通時計が設置され、操作員
の要求により共通時計の時刻を各々の計算機の内部時計
に設定する。2. Description of the Related Art Generally, in a complex computer system, each computer is equipped with an internal clock, and each computer operates with the time of its own internal clock as positive. in this case,
A common clock that can be read from a plurality of computers is installed to synchronize the internal clocks of each computer, and the time of the common clock is set to the internal clock of each computer at the request of an operator.
【0003】図3に、従来の複合系計算機システムにお
ける計算機時計システムを示す。FIG. 3 shows a computer clock system in a conventional complex computer system.
【0004】この計算機時計システムは、計算機1(1
)および計算機1(2)に共通時計2が接続されている
。各計算機1は、計算機内部時計3および計算機内部時
計時刻設定部4とを備えている。[0004] This computer clock system has a computer 1 (1
) and the computer 1 (2) are connected to a common clock 2. Each computer 1 includes a computer internal clock 3 and a computer internal clock time setting section 4.
【0005】計算機1(1)について、操作員が時刻修
正指令を入力すると、計算機内部時計時刻設定部4では
、共通時計2より時刻を読み出し、計算機内部時計3に
時刻を設定する。さらに、同様に計算機1(2)につい
て、操作員の時刻修正指令の入力により計算機内部時計
時刻設定部4が共通時計2より計算機内部時計3に時刻
を設定する。このように複合系計算機システムでは同様
の処理を各計算機に実施して全ての計算機の内部時計の
時刻を共通時計の時刻に一致させる。When the operator inputs a time adjustment command to the computer 1 ( 1 ), the computer internal clock time setting section 4 reads the time from the common clock 2 and sets the time in the computer internal clock 3 . Furthermore, in the same way, regarding the computer 1 (2), the computer internal clock time setting section 4 sets the time in the computer internal clock 3 from the common clock 2 in response to the input of the operator's time adjustment command. In this way, in a composite computer system, similar processing is performed on each computer to make the time on the internal clocks of all the computers coincide with the time on the common clock.
【0006】[0006]
【発明が解決しようとする課題】しかしながら、上記し
た従来のシステムでは、操作員が気付いたときに手動に
より時刻修正指令を入力するために計算機1(1)と計
算機1(2)の計算機内部時計3の時刻ずれが生じてい
る場合がある。[Problems to be Solved by the Invention] However, in the above-mentioned conventional system, in order to manually input a time adjustment command when the operator notices it, the internal clocks of the computers 1 (1) and 1 (2) are There may be a time difference of 3.
【0007】各計算機1の計算機内部時計3に時刻ずれ
が生じると、プラントデータ等の値が刻々と変化する処
理では、各計算機1の出力における時刻とプラントデー
タの関係がずれ、データの統一性が取れず、さらにデー
タの信頼性の低下を招くという問題がある。[0007] If a time lag occurs in the computer internal clock 3 of each computer 1, the relationship between the time and plant data in the output of each computer 1 will deviate in a process where the values of plant data etc. change moment by moment, and the consistency of the data will be affected. There is a problem in that it is not possible to obtain the required data, and the reliability of the data further deteriorates.
【0008】この場合、共通時計2の時刻を計算機内部
時計3に定期的に自動で設定して、上記した時刻ずれを
なくすことは可能である。ところが、共通時計2の時刻
が狂っていれば、全ての計算機の時刻が狂うため実施で
きなかった。In this case, it is possible to automatically set the time of the common clock 2 to the computer's internal clock 3 on a regular basis to eliminate the above-mentioned time deviation. However, if the time on the common clock 2 was incorrect, the time on all computers would be incorrect, so this could not be carried out.
【0009】そこで、本発明は、共通時計の健全性を確
認しながら計算機内部時計に共通時計の時刻を定期的に
自動設定する計算機時計システムを提供することを目的
とする。
[発明の構成]SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a computer clock system that automatically sets the time of a common clock in a computer's internal clock periodically while checking the soundness of the common clock. [Structure of the invention]
【0010】0010
【課題を解決するための手段】本発明は、複数の計算機
と、これら複数の計算機の各々の計算機内部時計を同じ
時刻に合わせるための共通時計と、前記各々の計算機に
は時刻修正指令により前記共通時計の時刻を読み出し、
かつ、前記計算機内部時計に前記共通時計の時刻を設定
するための計算機内部時計時刻設定部を有する計算機時
計システムにおいて、前記共通時計の時刻と前記各計算
機内部時計との時刻を定期的に読み出しこの両時刻の時
刻差を演算する前記各々の計算機に設けられた時刻比較
部と、これらの時刻比較部により演算された前記各時刻
差を記憶する記憶装置と、この記憶装置に記憶された前
記各時刻差と予め前記記憶装置に記憶された規定値とを
定期的に読み出して順次比較し、前記時刻差のいずれか
が前記規定値以内のとき前記計算機内部時計時刻設定部
に時刻修正指令を出力する前記各々の計算機に設けられ
た共通時計健全性確認部とを設けるようにしたものであ
る。[Means for Solving the Problems] The present invention provides a plurality of computers, a common clock for setting the internal clocks of each of the plurality of computers to the same time, and a time adjustment command for each of the computers to adjust the time to the same time. Read the time of the common clock,
and a computer clock system having a computer internal clock time setting unit for setting the time of the common clock in the computer internal clock, which periodically reads out the time of the common clock and the time of each of the computer internal clocks. a time comparison unit provided in each of the computers that calculates the time difference between both times; a storage device that stores each of the time differences calculated by these time comparison units; The time difference and a specified value stored in advance in the storage device are periodically read and compared in sequence, and when any of the time differences is within the specified value, a time correction command is output to the computer internal clock time setting section. A common clock health confirmation section provided in each of the computers is provided.
【0011】[0011]
【作用】上記構成により、共通時計健全性確認部は、共
通時計の時刻と計算機内部時計との各時刻差のいずれか
が予め記憶装置に記憶された規定値以内のとき共通時計
の時刻は正常と判定する。計算機内部時計時刻設定部は
、時刻修正指令により共通時計の時刻を読み出し、この
時刻を計算機内部時計に設定する。これにより、複数の
計算機システムの各計算機内部時計が共通時計の時刻に
合わせられ、全ての計算機内部時計の時刻を一致させる
ことができる。[Operation] With the above configuration, the common clock health confirmation unit determines that the common clock time is normal when any of the time differences between the common clock time and the computer internal clock is within the specified value stored in advance in the storage device. It is determined that The computer internal clock time setting section reads out the time of the common clock according to the time adjustment command, and sets this time in the computer internal clock. Thereby, each computer internal clock of the plurality of computer systems is synchronized with the time of the common clock, and the times of all the computer internal clocks can be made to match.
【0012】0012
【実施例】以下、本発明の実施例を図面を参照して説明
する。Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.
【0013】図1は、本発明の一実施例を示す計算機時
計システムのブロック構成図である。図中、図3と同一
符号は同一または相当部分を示す。図3と異なる点は、
記憶装置5を備えて計算機1(1)と計算機1(2)に
接続する一方、各計算機1に時刻比較部6および共通時
計健全性確認部7を備えた点である。FIG. 1 is a block diagram of a computer clock system showing one embodiment of the present invention. In the figure, the same reference numerals as in FIG. 3 indicate the same or corresponding parts. The difference from Figure 3 is that
The computer 1 is provided with a storage device 5 and is connected to the computers 1 (1) and 1 (2), while each computer 1 is provided with a time comparison section 6 and a common clock health confirmation section 7.
【0014】記憶装置5は、共通時計2と計算機内部時
計3の時刻差および所定の規定値を書き込む。The storage device 5 writes the time difference between the common clock 2 and the computer internal clock 3 and a predetermined specified value.
【0015】時刻比較部6は、共通時計2の時刻と計算
機内部時計3の時刻との時刻差を演算して、その時刻差
を記憶装置5へ書き込む。The time comparator 6 calculates the time difference between the time of the common clock 2 and the time of the computer internal clock 3, and writes the time difference to the storage device 5.
【0016】共通時計健全性確認部7は、記憶装置5に
書き込まれた時刻差が規定値以内であるか否か判定し、
規定値以内であれば共通時計2は正常であるとして、計
算機内部時計時刻設定部4時刻修正指令を出力する。The common clock health checking unit 7 determines whether the time difference written in the storage device 5 is within a specified value,
If it is within the specified value, the common clock 2 is considered normal and the computer internal clock time setting section 4 outputs a time correction command.
【0017】次に、図2に示す処理手順に沿って作用を
説明する。Next, the operation will be explained along the processing procedure shown in FIG.
【0018】最初に、計算機1(1)について処理がさ
れるとする。まず、時刻比較部6が共通時計2の時刻を
読み込む(101)。続いて、時刻比較部6が計算機内
部時計3の時刻を読み込む(102)。さらに、時刻比
較部6は上記時刻比較部6が読み込んだ共通時計2の時
刻と計算機内部時計3の時刻との差を演算してその時刻
差をε1として記憶装置5の共有メモリに書き込む(1
03)。First, it is assumed that processing is performed on computer 1 (1). First, the time comparator 6 reads the time of the common clock 2 (101). Subsequently, the time comparator 6 reads the time of the computer internal clock 3 (102). Further, the time comparator 6 calculates the difference between the time of the common clock 2 read by the time comparator 6 and the time of the computer internal clock 3, and writes the time difference as ε1 to the shared memory of the storage device 5 (1
03).
【0019】共通時計健全性確認部7では、時刻比較部
6が演算して記憶装置5に書き込んだ時刻差ε1を読み
出し、時刻差ε1が規定値ε以内か否か判定する(10
4)。The common clock health checking unit 7 reads out the time difference ε1 calculated by the time comparison unit 6 and written into the storage device 5, and determines whether the time difference ε1 is within the specified value ε (10
4).
【0020】即ち、次の条件式(1)が成立するか否か
判定する。That is, it is determined whether the following conditional expression (1) holds.
【0021】[0021]
【数1】 ε1<(|α1|+|α2|)×T=ε……(1)[Math 1] ε1<(|α1|+|α2|)×T=ε……(1)
【0
022】ここで、α1:共通時計2の精度α2:計算機
内部時計3の精度
T:時刻合わせの周期0
[022] Here, α1: Accuracy of the common clock 2 α2: Accuracy of the computer internal clock 3 T: Period of time adjustment
【0023】上記の条件式(1)の条件が成立する場合
、共通時計2は正常として共通時計健全性確認部7が計
算機内部時計時刻設定部4へ時刻修正指令を出力する。
計算機内部時計時刻設定部4では、時刻修正指令により
共通時計2から時刻を読み出し、これを計算機内部時計
3に設定する(105)(106)。If the above conditional expression (1) is satisfied, the common clock 2 is considered to be normal and the common clock health check section 7 outputs a time adjustment command to the computer internal clock time setting section 4. The computer internal clock time setting section 4 reads the time from the common clock 2 according to the time correction command and sets it in the computer internal clock 3 (105) (106).
【0024】一方、上記の条件式(1)の条件が成立し
ない場合、共通時計2または計算機1(1)の計算機内
部時計3の時刻が異常として次の処理がされる。On the other hand, if the above conditional expression (1) is not satisfied, the time of the common clock 2 or the computer internal clock 3 of the computer 1 (1) is determined to be abnormal and the following processing is performed.
【0025】まず、次の計算機1(2)について上記計
算機1(1)と同様に処理された共通時計2の時刻と計
算機1(2)の計算機内部時計3の時刻との差、つまり
、記憶装置5に書き込まれた時刻差ε2の読み出しを計
算機1(1)の共通時計健全性確認部7がする(107
)。次に、計算機1(1)の共通時計健全性確認部7は
、次の条件式(2)の条件が成立するか否かを判定をす
る(108)。First, regarding the next computer 1 (2), the difference between the time of the common clock 2 and the time of the computer internal clock 3 of the computer 1 (2), which has been processed in the same manner as the above computer 1 (1), that is, the memory The common clock health confirmation unit 7 of the computer 1 (1) reads out the time difference ε2 written in the device 5 (107
). Next, the common clock health check unit 7 of the computer 1 (1) determines whether the following conditional expression (2) is satisfied (108).
【0026】[0026]
【数2】ε2<ε……(2)[Math 2] ε2<ε...(2)
【0027】この判定で上記式(2)の条件が成立する
場合、計算機1(1)の共通時計健全性確認部7は計算
機内部時計時刻設定部4へ時刻修正指令を出力する。こ
れにより、計算機内部時計時刻設定部4が共通時計2の
時刻を読み出す(105)。そして、計算機1(1)の
計算機内部時計3に共通時計2の時刻を設定する(10
6)。If the condition of the above equation (2) is satisfied in this judgment, the common clock health check section 7 of the computer 1 (1) outputs a time adjustment command to the computer internal clock time setting section 4. As a result, the computer internal clock time setting unit 4 reads the time of the common clock 2 (105). Then, the time of the common clock 2 is set in the computer internal clock 3 of the computer 1 (1) (10
6).
【0028】計算機1(2)についても同様の処理によ
り計算機内部時計時刻設定部4が共通時計2の時刻を読
み出す。そして、計算機1(2)の計算機内部時計3に
共通時計2の時刻を設定する。以上の処理は、一定の周
期で繰り返し実施される。また、上記の条件式(2)の
条件が成立しない場合、共通時計2が異常として時刻の
設定をしない。このような場合、例えば、警報を出力す
る。Regarding the computer 1 (2), the computer internal clock time setting section 4 reads the time of the common clock 2 through the same process. Then, the time of the common clock 2 is set in the computer internal clock 3 of the computer 1 (2). The above processing is repeatedly performed at regular intervals. Further, if the above conditional expression (2) is not satisfied, the common clock 2 is considered to be abnormal and does not set the time. In such a case, for example, a warning is output.
【0029】なお、共通時計2の健全性を判定するため
の上記規定値εは、予め演算され記憶装置5の共有メモ
リに書き込まれている。The specified value ε for determining the health of the common clock 2 is calculated in advance and written in the shared memory of the storage device 5.
【0030】このように、操作員の操作を必要としない
で共通時計の健全性を確認しながら計算機内部時計の時
刻を共通時計に合わせて2台の計算機時計システムの時
刻を一致させることができる。[0030] In this way, it is possible to synchronize the times of two computer clock systems by adjusting the time of the computer internal clock to the common clock while checking the soundness of the common clock without requiring any operation by an operator. .
【0031】なお、上記した実施例では、2台の構成の
計算機時計システムについて説明したが、計算機の台数
が増加しても時刻差を比較する計算機の台数を増加して
いずれかが正常であれば共通時計は正常であるとして時
刻合わせを実施して複合系計算機システムの各計算機の
時刻を一致させることができる。[0031] In the above embodiment, a computer clock system having a configuration of two computers was explained. However, even if the number of computers increases, it is possible to increase the number of computers for comparing time differences and to check whether one of them is normal. For example, it is possible to perform time adjustment assuming that the common clock is normal so that the times of each computer in the complex computer system match.
【0032】[0032]
【発明の効果】以上説明したように本実施例によれば、
共通時計の健全性を確認しながら計算機内部時計の時刻
を共通時計に合わせることができる。従って、複合系計
算機システムにおける各計算機の時刻のずれが正確に修
正される。[Effects of the Invention] As explained above, according to this embodiment,
The time of the computer's internal clock can be adjusted to the common clock while checking the health of the common clock. Therefore, the time difference between each computer in the composite computer system can be corrected accurately.
【図1】本発明の一実施例を示す計算機時計システムの
ブロック構成図である。FIG. 1 is a block diagram of a computer clock system showing one embodiment of the present invention.
【図2】同装置の処理手順を示すフローチャートである
。FIG. 2 is a flowchart showing the processing procedure of the device.
【図3】従来例を示す計算機時計システムのブロック構
成図である。FIG. 3 is a block configuration diagram of a computer clock system showing a conventional example.
1(1),1(2) 計算機 2 共通時計 3 計算機内部時計 4 計算機内部時計時刻設定部 5 記憶装置 6 時刻比較部 7 共通時計健全性確認部 1(1), 1(2) Calculator 2 Common clock 3. Computer internal clock 4. Computer internal clock time setting section 5. Storage device 6 Time comparison section 7 Common clock health confirmation section
Claims (1)
の各々の計算機内部時計を同じ時刻に合わせるための共
通時計と、前記各々の計算機には時刻修正指令により前
記共通時計の時刻を読み出し、かつ、前記計算機内部時
計に前記共通時計の時刻を設定するための計算機内部時
計時刻設定部を有する計算機時計システムにおいて、前
記共通時計の時刻と前記各計算機内部時計との時刻を定
期的に読み出しこの両時刻の時刻差を演算する前記各々
の計算機に設けられた時刻比較部と、これらの時刻比較
部により演算された前記各時刻差を記憶する記憶装置と
、この記憶装置に記憶された前記各時刻差と予め前記記
憶装置に記憶された規定値とを定期的に読み出して順次
比較し、前記時刻差のいずれかが前記規定値以内のとき
前記計算機内部時計時刻設定部に時刻修正指令を出力す
る前記各々の計算機に設けられた共通時計健全性確認部
とからなることを特徴とする計算機時計システム。1. A plurality of computers, a common clock for setting the internal clocks of each of the plurality of computers to the same time, and a time correction command for each of the computers to read the time of the common clock, and , in a computer clock system having a computer internal clock time setting unit for setting the time of the common clock in the computer internal clock, periodically reading out the time of the common clock and the time of each of the computer internal clocks; a time comparison unit provided in each of the computers that calculates a time difference; a storage device that stores each of the time differences calculated by these time comparison units; and each of the times stored in this storage device. The difference and a specified value stored in advance in the storage device are periodically read out and compared in sequence, and when any of the time differences is within the specified value, a time correction command is output to the computer internal clock time setting section. A computer clock system comprising: a common clock health confirmation section provided in each of the computers.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3133130A JPH04359187A (en) | 1991-06-05 | 1991-06-05 | Computer clock system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3133130A JPH04359187A (en) | 1991-06-05 | 1991-06-05 | Computer clock system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04359187A true JPH04359187A (en) | 1992-12-11 |
Family
ID=15097485
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3133130A Pending JPH04359187A (en) | 1991-06-05 | 1991-06-05 | Computer clock system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04359187A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2012234275A (en) * | 2011-04-28 | 2012-11-29 | Nec System Technologies Ltd | Real time clock correction circuit and real time clock correction method |
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1991
- 1991-06-05 JP JP3133130A patent/JPH04359187A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012234275A (en) * | 2011-04-28 | 2012-11-29 | Nec System Technologies Ltd | Real time clock correction circuit and real time clock correction method |
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