JPS62221723A - Disk controller - Google Patents

Abstract

PURPOSE:To simplify the control system for channel device by outputting continuously the request signals from a disk controller regardless of the field boundaries and controlling the answer signals received from the channel device after dividing them by the disk controller for each field. CONSTITUTION:A request control circuit 18 outputs the prescribed number of request signals 21 decided by the number of data bytes of each of plural fields as well as the request bus validity display signals 22a and 22b showing the validity of those data outputted synchronously with the signals 21 continuously to a channel device via a bus of plural bytes. An answer control circuit 17 receives the prescribed number of series of answer signals 23 outputted from the channel device as well as the answer bus validity display signals 24a and 24b via a bus of plural bytes. Then the circuit 17 divides the data supplied synchronously with those signals 23 for each field with reference to the prescribed number of signals 23. A padding control circuit 12 gives the padding process to those divided data.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a disk control device that is located between a channel device and a disk device and performs multi-byte width data transfer with the channel device. The present invention relates to a disk control device suitable for standardizing control methods.

[Conventional technology]

In the input/output subsystem of a computer system, which consists of a channel device, a disk device, and a disk control device that controls the operation of the disk device, the disk device stores data consisting of a multiple of a predetermined even number of bytes (hereinafter referred to as a cell). When writing and reading data in one format, conventionally data was transferred between a channel device, a disk controller, and a disk controller in the following manner.

Field C shown in Figure 2 (a), (b), (c)
,,D.

Assume that K is written to a disk device. In this case, an instruction (for example, WRT
TE CKD) is output. In response to this command, the disk controller sends a series of request signals to fields C and I according to the number of data bytes in fields C and D.
) Divide into units and output. As shown in FIG. 2(a), the channel device continuously manages fields C, D, and the series of request signals indicated in field C.
, is input from the disk controller divided into D units, so a series of response signals to a series of request signals are inputted in field C, in D units, as shown in FIG. 2(b). Divide and output. The disk controller receives a series of response signals divided into D units in field C, and
For each field C, it is determined whether the number of bytes of the D response signal is a multiple of the number of cells, and if it is determined that the number of bytes is not a multiple of the number of cells, the number of bytes shown in FIG. ``0'' data is added to the missing data, and then the data is transferred to the disk device. 1] The addition of the LL OI+data is referred to as padding processing.

As related prior art, Japanese Patent Application Laid-Open No. 59-1368
There is an invention disclosed in Publication No. 33.

[Problem that the invention seeks to solve]

In the data transfer between the disk control device and the channel device described above, a plurality of PIs are used as a bus to connect both devices.
When using a bus with a width of . That is, in the examples shown in FIGS. 2(a), (b), and (c), for example, when the number of response signals to the field is not divisible by the number of bytes (number of lines) of the bus, the signals are output at the last timing. The data in the field will be transmitted on some lines of the bus, and the other lines that make up the bus will not transmit valid data. In this case, if the configuration is such that the channel device creates a response bus valid display signal indicating which line is transmitting valid data among the buses connecting the channel device and the disk control device, and outputs it to the disk control device. The disk controller recognizes valid data from among the data input via a multi-byte wide bus and performs a pup process, etc.

However, if a conventional channel device is used to form the response bus valid indication signal, the response bus valid indication signal will be outputted continuously to fields C and D without being interrupted at each boundary. As a result, valid data is being transmitted even on lines that do not transmit valid data on the bus connecting the channel device and the disk control device, causing the disk control circuit to incorrectly recognize input data. A situation arises.

The present invention was made in view of the problems of the prior art described above, and even if the bus connecting the disk control device and the channel device is made into multiple bytes, the input data can be correctly recognized.
It is an object of the present invention to provide a disk control device that enables correct padding processing at field boundaries.

[Means for solving problems]

The disk control device of the present invention includes a predetermined number of request signals determined based on the number of data bytes of each of a plurality of fields, and a request bus valid display indicating that data output in synchronization with the request signal = 4- is valid. a first means for successively outputting a signal to the channel device via the buses of the plurality of pies 1 to 1; A predetermined number of response signals output and a response bus valid indication signal output in synchronization with the response signals are received via a multi-byte bus, and the response signal and the response bus valid indication signal are -1 - A second means for dividing the data inputted in synchronization with the series of response signals into each field unit by referring to the predetermined number of responses; The third means for padding data is provided.

[For production]

According to the disk control device of the present invention, a predetermined number of request signals determined by the number of data bytes of each of a plurality of fields are successively output to the channel device. The channel device outputs a series of response signals in response to the series of request signals. In this case, the request signals are input continuously regardless of field boundaries. Further, response signals are also continuously inputted regardless of the field. At this time, the disk control device determines the field boundary of the response signal by referring to the response bus valid indication signal input in synchronization with the response signal and a predetermined number determined by the number of data bytes of each of the plurality of fields. Then, based on the determination result, the series of data input in synchronization with the response signal is divided into fields,
Padding processing is performed.

〔Example〕

Hereinafter, the present invention will be explained in more detail with reference to embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and is an example in which data is transferred via a channel device (not shown) and a 2-byte wide bus. In the figure, the CPUI stores the number of bytes of one cell in the register 16. Next, processor 1 stores the number of bytes of data in the first field in register 2. Now, Figure 2 (a), (b
), (C), if we consider the case where data of D is transferred to field C, the number of bytes of data of field C will be stored. When the number of bytes of data in the first field is stored in register 2.

The CPUI sets flag 3 to indicate that data has been set in register 2. Flag 3 is set to 11
1'', the contents of register 2 are automatically set in request counter 6 and response counter 10.

Further, the contents of register 2 and the contents of register 16 are input to the arithmetic circuit 15, and the arithmetic circuit 15 calculates the number of padding bytes for the data in the first field. Considering the example shown in Figures 2(a), (b), and (c), register 2 currently stores the number of bytes of field C, and as is clear from Figure 2(c), The number of bytes in field C is an integral multiple of the number of bytes in one cell. Therefore, the output of the arithmetic circuit 15 becomes zero. The output of the arithmetic circuit 15 is set in the pap ink counter 13 at the same time as the flag 3 is set. When the above-described request counter 6, response counter 10, and padding counter 13 are each set, the flag 3 is reset.

When processor 1 recognizes that flag 3 has been reset, it stores in register 2 the number of bytes of data in the next field. Figure 2 (a), (b).

In the example shown in (c), the number of bytes of data is stored in the field. When the number of bytes of data is stored in register 2, flag 3 is set again.

Thereafter, when the processor 1 instructs the start of data transfer, the request control circuit 18 indicates that the request signal 21 and the 2-byte data output in synchronization with the request signal 21 are valid data. Request bus valid display signal 22a
, 22b are sequentially output to the channel device. The request control circuit outputs two pulses to the request counter 6 every time it outputs the request bus valid display signals 22a, 22b. Since the request counter 6 is a down counter, it counts down by two.

When the content of the request counter 6 becomes 110'' or 1, the gate 20 outputs 111'', and the AND circuit 8
“1” is sent to the set terminal S of the request counter 6 via
is input. by this.

The contents of the register 2 are newly set in the request counter 6. At this time, if the decoder 7 that decodes the output of the request counter 6 is outputting It I II, the output of the adder 4 that adds LL I II to the contents of the register 2 is selected by the selector 5,
The request counter 6 is set. Figure 2(a)
, (b) and (c), the number of bytes in field C initially set in request counter 6 is an integral multiple of one cell (even number of bytes), so it is counted down by two, and the final number is It becomes II OII.

Therefore, in this case, the contents of the register 2 (the number of bytes in the field), rather than the output of the adder 4, are set in the request counter 6 via the selector 5.

The contents of the request counter 6 are counted down by 2, and when it finally reaches "1", the value obtained by adding "1" to the contents of register 2, which is the number of bytes of the next field, is added to the request counter 6. The reason for setting ′ is as follows. That is, this is to make the total value of each field stored in the counter 6 equal to the total value of the actual number of bytes of each field.

The number of bytes of data corresponding to each field is sequentially set in the request counter 6, and the request signal 21 and request bus valid display signals 22a and 22b are sequentially output, and as a result, the content of the request counter 6 finally becomes 1''. In this case, the operation is as follows. That is, when the request control circuit 18 detects that the content of the request counter 6 becomes 111" while outputting the request signal of the last field, , and outputs only the request bus valid indication signal 22a in synchronization with the request signal 21. At this time, the request control circuit 18 outputs only one pulse to the request counter. As a result, request counter 6
The content of is now II OII, which means that the request signal 21 corresponding to all fields has been output.

As described above, the disk control device of this embodiment is configured to output the series of response signals 21 of a plurality of fields continuously, rather than dividing them into individual fields. When the response signal finally becomes one byte output from the disk control device, the configuration is such that only the request bus valid indication signal 22a is output in synchronization with the response signal 21, and the request bus valid indication signal 22b is not output. ing.

The channel device receives the above-described series of response signals 21 and request bus response signals 22a, 22b, and responds to each request signal 2.
A series of response signals 23 corresponding to 1 and response bus valid display signals 24a and 24b are continuously output. At this time, if the response signal 21 is not accompanied by the request bus validity indication signal 22b, the configuration is such that the response bus validity indication signal 24b, which is output in synchronization with the response signal 23, is not output.

The above series of response signals 23 and response bus valid display signal 24a
, 24b are input to the response control circuit 7 of the disk control device, as shown in FIG. The response control circuit 17 is
Response bus valid indication signal 24a for each response signal 23
, 24b and outputs two pulses to the response counter 10. Response bus valid display signal 24a, 2
If 4b cannot be confirmed, the number of pulses that can be confirmed is outputted. Therefore, the response counter 10 normally counts down by two.

Now, a series of response signals 23 corresponding to a series of request signals 'i+21 of one field are input, and the contents of the response counter 10 are counted down, and finally, 17
When it becomes 0'', the decoder 11 detects this and outputs 1''. As a result, 1'' is input to the set terminal S of the response counter 10 via the AND circuit 9, and the contents of the register 2 indicating the number of data bytes of the next field are set in the response counter 10. can also be executed between the two responses generated by the one response signal 23 and the pulses to the response counter 10. Therefore, the response counter 10 can be executed as follows.
Response signal 23 where the next field is the same as the previous field
Field boundaries can be detected even if input by

Further, when "1" is output from the decoder 11, padding processing is performed as follows. The padding control circuit 12 outputs 1111+ from the decoder 11.
The padding process is started in response to this.

That is, the final response bus valid indication signal 2 in the field is synchronized with the final response signal 23 in the input field.
Data of 60" is added after the input data (not shown) determined by 4a and 24b. The padding counter 13 is counted down by 1 each time 0" data is added. When the content of the padding counter 13 becomes "0υ", the number of data bytes in the field becomes equal to a multiple of 1-the number of bytes constituting a cell, and the padding process ends.

As described above, padding processing is performed for each field, and a series of response signals 23 for the final field are input, and as a result, the contents of the response counter 10 are counted down by 2 and finally reach "1". do. In this case, the response signal 23 input at the next timing
Among the response bus valid display signals 24a and 24b, only the response bus valid display signal 24b is not input. Therefore, the response control circuit 7 detects that the data corresponding to the response bus valid display signal 24b among the input 2-byte data is invalid, and outputs only one pulse to the response counter 10. As a result, response counter 1
The content of 0 becomes tL OI+, and the decoder 11 sends LL
i I+ is output, and padding processing is performed as described in -1].

According to the embodiment described above, the request signals 2]a, 2], and b output from the disk control device to the channel device are as follows:
Output is continuous without interruption between fields.

In addition, a 2-byte response signal 23a is output from the channel device in response to continuous request signals.

23b is processed field by field by the response counter 1o and padding counter 13.

Furthermore, all of the processing described above is performed on hardware, and has the advantage of not adding any overhead to the microprogram.

In addition, -■- In the second embodiment, the request signal and the response signal are transmitted using a 2-byte wide bus, but the present invention can be applied in exactly the same way even in the case of a multiple-byte width such as 3-byte width. I can do it.

〔Effect of the invention〕

According to the present invention, the request signal output from the disk control device is output continuously regardless of field boundaries;
In addition, the response signal from the channel device can be divided into fields and managed on the disk control device side. Therefore, the channel device has the effect of being able to perform control without being aware of field boundaries. the result,
It is possible to simplify the control method of the channel device and standardize the channel device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 (
3A, 3B, and 3C are diagrams showing examples of data transferred from a channel device to a disk control device/disk device. 1...Processor, 2,16...Register, 3...
Flag, 4... Adder, 5... Selector, 6. Request counter, 7. ]1.19...decoder, 8,9
．． 14...AND circuit, 10...Response counter, 12...Padding control circuit, 13...Padding counter, 15...Arithmetic circuit, 17...Response control circuit, 18...Request control circuit , C, to D... field.

Claims (1)

[Claims] 1. A predetermined number of request signals determined based on the number of data bytes of each multiple field, and a request bus valid indication signal indicating that the data output in synchronization with the request signal is valid, are transmitted over a multiple-byte bus. a series of response signals output from the channel device in response to the continuously output request signal and the request bus valid indication signal; Receives a response bus valid indication signal indicating that the synchronously output data is valid via a multi-byte bus, and refers to the response signal, the response bus valid indication signal, and the predetermined number; a second means for dividing the data input in synchronization with the series of response signals into field units; and a third means for performing padding processing on the data input in synchronization with the response signal by the division. A disk control device comprising: