JPS59136843A - Working check method for error correcting function in serial data transfer - Google Patents

Abstract

PURPOSE:To check automatically an error correcting function by producing artificially an abnormal transfer data, and reading it after outputting it temporarily to an external device. CONSTITUTION:A data transfers system is provided with an FIFO10, a parallel/ series converting circuit 20, redundant bit adding circuit 30, error correcting circuit 40, arithmetic circuit 50 which obtains an exclusive OR between two data, and an external device 70 such as a disk memory, etc. Then an abnormal transfer data is artificially produced and sent to the device 70. This transfer data is read and applied to the circuit 40, and the function of an error detecting circuit is checked by the presence or absence of a data error. Then the function of the circuit 40 is checked by whether the data can be corrected to a prescribed pattern or not. In such a way, an abnormal transfer data is artificially produced and read after outputting it temporarily to the device 70. This ensures an automatic check of the error correcting function. In this case, the checking is more facilitated with an actual device since no special request is given to the remote side.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for checking the operation of an error correction function or an error detection function in serial data transfer.

Conventionally, in systems that perform serial data transfer, redundant bits are added to the transferred data so that it can be determined from the data whether or not the data has been transferred accurately. Sometimes it has only a function).

However, at present, the above function itself has not been checked very much, and if you dare to do so, you should create a simulated amount of data on the other side that receives serial data transfer, and check the data that requires an error correction function. A method is used to generate and check data in which the contents of the column and redundant bits do not match. However, this method has the disadvantage that it is necessary to prepare a simulated quantity ζ, and that it is only a simulation and cannot be checked on an actual device.

The present invention was made in consideration of the points mentioned above, and its purpose is to facilitate the error correction function or error detection function without installing the simulated quantity. The purpose of this invention is to provide a method for checking functional operation.

The present invention will be described in detail below using the drawings. FIG. 1 is a block diagram of the main parts of a system for implementing the method of the present invention. In the same figure, 101 reads the data given from the upper intelligence, etc., and outputs the data in the order read.
20 is a parallel/serial conversion circuit that converts parallel data into serial data, and 30 is a redundant bit signal that is added after a series of data to check the transferred data, as shown in FIG. A redundant bit addition row 40 is an error detection and correction circuit capable of detecting and correcting errors in the transferred data, 5
0 is an arithmetic circuit (usually a central processing unit [the function B is included in the CPU) that calculates the exclusive OR of two given data; 60 is a data bus connected to the central processing unit CPU (not shown); 70 indicates an external device such as a disk memory.

The operation in such a configuration will be explained next.

During a normal write command, the same data is given from the CPU to the parallel/serial circuit 20 and the redundant bit addition circuit 30, but when checking the operation of the error correction function, the operation is as follows.

(1) For n bits from the beginning, the same data (D
o -Dn-1).

(2) Regarding error location numbers n to m (y), data Dn' to Dm' are given to the parallel/series circuit 20 ((a) in FIG. 2), while data Dn is given to the redundant pit addition circuit 30. ' ~ Dm ' and error pattern P
The output data Dn-Dm of the arithmetic circuit 5 obtained by exclusive ORing with n-Pm ((c) in FIG. 2) is given (second
Figure (b)).

(3) From the following m+1 words, data is given in the same way as in (1) above. (4) In the redundant bit addition time @30, data Do
~Dn-1p Dn -Dmt 0m+1~Dk-1(
Redundant bit data is calculated based on the data length k), and this redundant bit data is added after the data string of bits ((a) in FIG. 2).

In this way, transfer data as shown in (a) in Figure 2 is created and sent to an external device, and then the transferred data is read and applied to an error correction circuit to detect errors based on whether or not a data error occurs. You can check the functionality of the circuit,
The function of the error correction circuit can be checked depending on whether the data can be corrected to the data pattern (b). That is, if a data error occurs and the data string given to the redundant bit adding circuit can be corrected, it can be determined that the function is normal.

As described above, according to the present invention, it is possible to automatically check the error correction function by creating artificially abnormal transfer data, outputting it to an external device, and then reading it.

According to the present invention, since no special request is made to the data transfer partner, it is possible to easily check the error correction function on the actual device, and the effect is great in practical use.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of a system for implementing the method of the present invention, and FIG. 2 is a diagram for explaining how transfer data is created. 20... Parallel/serial conversion circuit, 30... Redundant bit addition circuit, 40... Error detection and correction circuit, 50... Arithmetic circuit.

Claims (1)

[Claims] A parallel/serial conversion circuit that converts given parallel data into serial data and sends it out, a redundant bit addition circuit that adds error detection data to the transferred data, and a redundant bit addition circuit that detects or corrects errors in the transferred data. A serial data transfer system having an error correction circuit includes an arithmetic circuit that obtains an exclusive OR of a predetermined error pattern and the transfer data, and a parallel/serial conversion circuit and redundant bit addition for the first n bits of data. The data is supplied to the circuit in parallel, and the desired data is supplied to the parallel/serial conversion circuit for m-''n+i bits of data for error location identification, and this desired data is supplied to the redundant bit addition circuit. Data for transfer with redundant bits created by giving data that is exclusive ORed with an error pattern is given to an external device, and the data is read back from the external device again, thereby artificially causing a data error. 1. A method for checking the operation of an error correction function in serial data transfer, characterized in that the operation of the error correction function is checked in such a manner as to