WO2006090089A1

WO2006090089A1 - Emulating/simulating a logic circuit

Info

Publication number: WO2006090089A1
Application number: PCT/FR2006/050164
Authority: WO
Inventors: Michaël NICOLAIDIS
Original assignee: Iroc Technologies
Priority date: 2005-02-25
Filing date: 2006-02-24
Publication date: 2006-08-31
Also published as: FR2882601B1; FR2882601A1

Abstract

The invention concerns a method for emulating or simulating the operation in the presence of disturbances of a circuit capable of executing a sequence of instructions, the circuit comprising logic elements and first storage elements, including the following steps: placing the circuit in an incorrect state, wherein the value of at least one storage element is modified relative to a correct state of the circuit; initiating execution of a sequence of instructions; providing in second storage elements, the normal values that the first storage elements would contain after executing each instruction if the circuit had been placed in the correct state; comparing after each executed instruction and by means of simultaneously activated comparators, all the values contained in the first and second storage elements; and stopping execution of instructions if the values contained in the first and second storage elements have become identical.

Description

EMULATION / SIMULATION OF A LOGIC CIRCUIT

The present invention relates to the emulation and the simulation of the operation of an integrated circuit in the presence of disturbances likely to modify the state of the circuit.

The present invention relates more particularly to integrated circuits comprising logic elements, for example combinatorial logic gates OR, AND, and synchronous storage elements such as flip-flop registers, static memories (SRAM), dynamic memories (DRAM), not volatile (OTP, FLASH or others). When an integrated circuit receives an external disturbance, for example natural radiation, an electric pulse is likely to be created in the affected element. If the affected element is a logic element, then the pulse propagates through the following logical elements to one or more registers. On the clock stroke following the disturbance, the values stored in these registers may have errors. If the touched item is a storage item, the value it contains can be changed.

Integrated circuits generally execute a sequence of commands that can be stored in a memory, or provided by an external device through the input / output terminals of the circuit. When a disturbance arrives, values contained in one or more storage elements may be rendered incorrect. When executing commands according to the incidence of the disturbance, the circuit can return to a normal state corresponding to a state that it would have had in the absence of disturbances. However, in this case, the number of cycles necessary for the circuit to return to a normal state is very variable.

Figure 1 is a diagram of a known emulation device using a programmable logic array (FPGA, Field Programmable Gate Array). The emulated circuit comprises two synchronous logic circuits 1 and 2 connected to two memories Mem1 and Mem2 by a bus 3. The two synchronous logic circuits 1 and 2 are shown schematically in the form of combinational logic blocks 10, 11 and 20 respectively connected to the inputs register data 12, 13 and 21. The logic block 10 receives external signals. The logic blocks 11 and 20 respectively receive the data provided by the registers 12 and 13. The register 21 provides output signals.

In order to be able to position the registers in a predetermined state, the circuits 1 and 2 comprise multiplexers 14, 15 and 22 and shift registers 16, 17 and 23 respectively connected to the registers 12, 13 and 21. Each multiplexer receives on first inputs data from a logic block and on second inputs the outputs of a shift register and connects the first or second inputs to the data inputs of a register whose outputs are connected to a shift register. Each shift register 16, 17 and 23 receives or provides serial data on an access terminal respectively 18, 19 and 24. The data in memory can be read or written via an access terminal 4 connected to the bus 3.

In normal operation, the circuit storage elements are put in an initial state adapted to a sequence of commands to be executed. In order to emulate the operation of the circuit having received a disturbance, it is necessary to In the execution of the command sequence, the circuit in a modified initial state introduces one or more errors with respect to the normal initial state.

The values that the registers 12, 13, 21 must contain in the modified initial state, are introduced in series in the shift registers 16, 17, 23, at the rate of a clock, then written in the registers 12, 13, 21 in parallel on a clock stroke. Similarly, we write one after the other, the values that must contain each of the memories. The circuit then executes the command sequence. At the end of the execution, the data stored in the registers 12, 13, 21 are written in parallel in the shift registers 16, 17, 23 and provided in series for analysis. The values contained in the memories Mem1 and Mem2 are likewise read. A disadvantage of this conventional emulation circuit is that, each time we want to perform a test, we run a complete sequence of commands and it is only at the end of the execution of this sequence of commands that it is possible to know, by reading serially the contents of registers 16, 17 and 23, and memories Mem1 and Mem2 if errors remain or if the circuit has found a normal state.

The present invention aims to allow simply to interrupt a test as soon as one realizes that there are no more errors in the circuit after the execution of a command of the current command sequence.

To achieve this object, the present invention provides for comparing in parallel and during the execution of the command sequence, the contents of the registers of a circuit in which an error has been injected to the contents of registers containing the result that would be provided. by an error-free circuit running in parallel the same sequence of commands.

Note that this would not be possible with the emulated circuits of the prior art since, if one wanted, after each command to determine whether or not the registers contain an error, it would be necessary to read these registers. after each order in serial form. In fact, since the number of access terminals to the emulated circuit is limited, the shift registers must currently contain between one hundred and one thousand elementary registers of a bit. Since the serial read time of the shift registers is proportional to the number of elementary registers to be read, and the read time of the memories being substantially proportional to their size, the playing time can become very long. If we realized a reading after each command, in most cases, one would arrive at an extremely long run time and prohibi ^¬ tive.

During the simulation of a circuit, it is possible to ask the simulator to indicate after each cycle what are the values contained in the registers and the memories and to compare them with the normal values which they should contain if the circuit does not was not disturbed. However, "dropping" the values after each cycle greatly slows the simulation of the circuit.

More particularly, the present invention provides a method of emulation or simulation of the function ^¬ nement in the presence of disturbances of a circuit capable of executing a sequence of commands, the circuit having logic elements and first storage elements the method comprising the steps of: putting the circuit in an incorrect state, wherein the value of at least one storage element is changed with respect to a correct state of the circuit; start execution of a command sequence; providing in second storage elements the normal values that the first memory elements would contain after the execution of each command if the circuit had been put in the correct state; comparing, after each command executed and by means of comparators activated simultaneously, all the values contained in the first and second storage elements; and stop the execution of commands if the values contained in the first and second storage elements become identical.

The present invention further provides a device for emulating operation in the presence of disturbances of a circuit capable of executing a sequence of commands, the device comprising: a test circuit identical to said circuit and comprising logic elements and first elements of memorization; means for putting the circuit in an incorrect state in which the value of at least a first storage element is changed with respect to a correct state of the circuit; means for initiating execution of a command sequence; second storage elements loaded by the normal values that would contain the first storage elements after each command if the circuit had been in the correct state before the execution of the commands; compara ^¬ tors to establish after each command executed if the values contained in the first and second storage elements differ; and interrupt means controlled by said comparators. According to a variant of the device previously described, the device comprises a second identical circuit to said test circuit, the second storage elements being the storage elements of the second circuit, and comprises means for putting the second circuit in a correct state, said means for start the execution of a sequence of commands acting on both circuits.

According to a variant of the device previously described, the first storage elements comprise registers placed between the logic elements. According to a variant of the device described above, the first storage elements of said test circuit comprise at least one memory storing data words each consisting of at least one bit. According to a variant of the device described above, some or all of the comparators compare the contents of the registers of each of the circuits.

According to a variant of the device previously described, the device comprises for each memory of said test circuit, an additional storage means comprising an error bit for each address of the memory, one or more comparators analyzing the signals addressed to a given memory of said circuit. test and the signals addressed to the memory of the second identical circuit to the given memory, in order to activate or deactivate an error bit at a given address when a difference between the data words stored in the two memories at this address determined appears or disappears, an error detection circuit indicating the means of interruption if at least one error bit is activated.

According to a variant of the device previously described, the device comprises for each memory of said test circuit, a content addressing memory consisting of words intended to each store at least one address and an error bit, one or more comparators analyzing the signals. addressed to a given test said memory circuit and the signals sent to the memory of the second identical circuit to the data memory in order to detect the appearance or disappearance of a consis error ^¬ both a difference between the data words stored in the two memories at a given address, the occurrence of an error resulting in a statement of the address determined in a word of the address memory by the content associated with the memory in question, and an activation of the error bit of this word , the disappearance of an error resulting in the deactivation of the error bit of the word storing the determined address, an earth detection circuit ur indicating the means of interruption if at least one error bit is activated.

According to a variant of the device previously described, a memory of said test circuit is a virtual memory replaced by the association of a memory addressed by the content CAM and a pilot device connected to said test circuit and to the "associated" memory of the second circuit corresponding to the virtual memory, a word of the memory CAM being provided for storing at least one data word, an address and an error bit , only the words of the virtual memory which differ from the words of the associated memory being stored with their addresses in a word of the memory CAM by activating its error bit, the reading of a data word in the virtual memory to a consistent data address for the pilot device to look at whether an erroneous data word corresponding to the given address is stored in a word of the CAM memory whose error bit is activated and otherwise to request a reading at this address in the associated memory, the writing of a word in the virtual memory to a given address consisting for the pilot device to compare this word with the word written at the given address in the associated memory , and if there is a difference in storing this word in a word of the memory CAM by activating its error bit, the pilot device detecting the differences between the signals exchanged between the associated memory and the second circuit and the signals exchanged between the memory virtual and the test circuit to identify situations that lead to differences between the data words stored in the virtual memory and those stored in the associated memory, the erroneous data words of the virtual memory being stored in words of the memory CAM by activating their error bits.

According to a variant of the device previously described, the device comprises for each memory of said test circuit, an identical memory called initialization comprising the correct values of the memories of the test circuit corresponding to the initial state of the test circuit before the execution of a sequence of commands, and comprising for each memory of the test circuit and the second circuit, an additional storage means comprising a validation bit for each address of the corresponding memory, and in which a word read by the test circuit or the second circuit to a given address of a memory either from the initialization memory when the validation bit corresponding to this address is not activated, or from this memory when the validation bit corresponding to this address is activated following a previous write to this address when executing the sequence of commands.

According to a variant of the device previously described, the memories of the test circuit and their associated memories of the second circuit are virtual memories each replaced by the association of a memory addressed by the content CAM and a pilot device connected to the memory of initialization, to the test circuit and to the second circuit, the words of the memories CAM being provided for each memorizing a data word, an address, a validation bit and in the case of the CAM memories replacing the memories of the test circuit, a bit of error, a data word and its write address in a virtual memory being stored in a word of the memory CAM replacing this virtual memory by activating its validation bit, a data word provided during a reading of a virtual memory at a given address, coming from the memory CAM replacing this virtual memory or the initialization memory according to whether the given address is or not m morisée in a word in the CAM having a valid bit set, the erroneous data words in a memory of the test circuit are stored in words of the CAM replacing the memory by activating their enable bits and error.

According to a variant of the device described above, the test circuit, the second circuit and the comparators are physical elements that can be realized in a programmable logic array. The present invention further provides a computer file comprising a description of a device previously described, and intended to be simulated by a circuit computer simulator to execute said sequence of commands. These and other objects, features, and advantages of the present invention will be set forth in detail in the following description of particular embodiments given in a non-limiting manner with reference to the accompanying drawings in which: FIG. , previously described, of a logic circuit emulated according to the prior art; Fig. 2 is a diagram of an emulation device according to the present invention; Figure 3 is a more detailed diagram of the comparator circuit of the device of Figure 2; Fig. 4 is a storage / error detection scheme according to an embodiment of the present invention; Fig. 5 is a diagram of a CAM memory used in an embodiment of the present invention; and Fig. 6 is a diagram of an alternative embodiment of the emulation device of the present invention.

In a first part, the structure and operation of the basic elements of the emulation device of the present invention will be described.

In a second part, memory variants and detection of errors in memory will be described.

In a third part, we will describe a way to reduce the size of the emulation device.

In a fourth part, there will be described a means for rapidly restoring the errors present in a memory of the circuit under test.

In a fifth part, means will be described for accelerating the initialization phase of the memories of the tested circuit prior to the execution of a new command sequence.

In a sixth part, we will describe a way to reduce the size of the emulation device and accelerate the phase of initialization of the circuit before the execution of a new sequence of commands. 1. Basic Elements of the Emulation Device 1.1 General Structure Figure 2 is a diagram of an emulation device

100 according to the present invention. The emulation device comprises a test platform 101 and software control and analysis elements. The test platform 101 comprises a set of logic circuits and memories made in a programmable logic network 101 (FPGA, Field Programmable Gate Array). More specifically, the test platform 101 comprises two identical logic circuits EC and CC each connected to a memory EMem and CMem respectively. The circuits EC and CC are made from a functional description, for example of the type RTL (English Register Transfer Level), a circuit whose operation one wishes to know when it is subjected to a disturbance. Each logic circuit EC and CC is shown schematically, as in FIG. 1, in the form of combinational logic blocks interposed between registers. Each register is associated with an offset register and a multiplexer for loading and possibly discharging the register in series.

For example, the circuits EC and CC each comprise three logic blocks respectively L _E] _, L _E 2, L _E 3 and LQ] _, Lc2 'Lc3' connected to three registers respectively R _E ] _, ^R E2 ' ^R E3 and Rcir RC2' ^R C3 controlled by a clock CLK. The data outputs of a register R _E j_ or RQI _? i being between 1 and 3, are connected to the data inputs of a shift register RD _E j_ or RDQJ_. Data from a logic block L _E j_ or LQJ_ arrive on first inputs of a multiplexer M _E j_ or Mçj_.

Each multiplexer M _E j_ or MQJ_ receives on second inputs, the data outputs of the shift register RD _E j_ or RDQJ_. The outputs of each multiplexer M _E j_ or Mj_ are connected to the data inputs of the register R _E j_ or Rj_. The logic circuit EC is connected to a writing device 102, and the logic circuit CC is connected to a writing device 103. The devices 102 and 103 are part of the software of the emulation device and are optionally implemented in software form. . The writing device 102 is connected to the shift registers RD _E] _, RD _E 2, P ^ar RDE3 the interme diary ^¬ three terminals respectively access B _E] _, B _E B _E 2 and 3. The series write circuit 103 is connected to the shift registers RDQ] _, RDQ2? R ⁰ CS P ^ar three access terminals BQ] _, BQ2 and ^B Q3. Similarly, the memory EMem is connected to the writing device 102 via an access terminal B _E 5. The memory CMem is connected to the writing device 103 via a terminal of BQ5 access.

Furthermore, according to the invention, the circuit 101 includes comparators _C] _, C2 and C3. Each comparator Cj_ receives and compares in pairs the set of data outputs of the registers R _E j_ and RQI- An OR gate 106 receives each of the outputs of comparators C _] _, C2 and C3 and indicates whether at least one of the bits of the set of registers of the circuits CC and EC differs. The output of the OR gate 106 is connected to a detection device 107 via an access terminal Bg. In addition, a comparison circuit (COMP) 110 compares the address, data and control signals sent by the circuits CC and EC respectively to the memories CMem and EMem. The memory EMem contains additional memory bits relative to the memory CMem. At each address of the memory EMem is associated an error bit E. The comparison circuit 110 is connected to a counter (COUNT) 111 whose output is connected to the detection device 107 via a terminal of access B7. The detection device is preferably an element of the software of the emulation device.

A control device 104 forming part of the software of the emulation device, is connected to the inputs of the logic blocks L _E] _ and LQ] _ via two access terminals respectively B _E 4 and BQ4. During an initialization phase, the circuit CC, called "correct circuit", and its memory CMem are positioned in an initial state said normal prior to the execution of a sequence of commands. The values which the registers RQ] _ to RQ3 in the normal initial state must contain are supplied in series by the writing device 103 to the shift registers RDQ] _ to RDQ3 at the rate of a clock CLKg. MC _{multiplexers]} _ to MQ3 are then positioned to load into the RQ records] _ to _Rc3? the values written in the registers RDQ] _ to RDQ3, in a clock stroke CLK. Likewise, the normal initial values which the memory CMem must contain are supplied one after the other by the writing device 103 and written in the memory CMem. Simultaneously, the circuit EC said "error circuit" is put in a modified initial state for which one or more values stored in the registers ^R El to R-E3 and in the EMem memory are modified compared to the values in the state initial initial of the registers RQ] _ to RQ3 and the memory CMem.

Note that in the case where one can have a large number of base stations between the test platform 101 and the control elements and analysis software may be provided to directly load the registers _R] _ to R _E 3 and RQ] _ to RQ3 without using shift registers RD _E] _ to RD _E 3 and RDQ] _ to

RDC3- During the emulation phase, each DC and EC circuit receives similar commands from the controller 104. The control device 104 may, for example, activate an initialization signal of an instruction sequence stored in each of the memories CMem and EMem. This will be the case, for example, when the emulated circuit is a microprocessor, a microcontroller or any other device intended to execute a stored instruction sequence. The controller 104 may also directly provide a succession of commands that the DC and EC circuits execute at the rate of the CLK clock. In this case, the emulated circuit may for example be a circuit an interface, an adder or any circuit performing a given function on command of external signals.

During the emulation phase when a given incor rect ^¬ was written at an address of the memory EMEM, the comparison circuit 110 sets the error E bit associated with this page to a given value, for example "1" . Each time a new error bit E is set to 1, the comparison circuit increments the counter 111. In the case where an error is initially introduced into the memory EMem, the error bit E corresponding to the address erroneous values are set to 1. When executing the command sequence, it is possible for a write to modify the values contained in an address whose error bit is at 1. In the case only where the written values are correct, the comparison circuit 110 resets the error bit E corresponding to 0 and decrements the counter 111.

The function of the detection device 107 is to monitor the comparators C1 to C3 and the counter 111. When the counter 111 and the comparators C1 to C3 are all at 0, which means that the error introduced has disappeared after the execution of a number of commands, the detection device 107 requests the stop execution of the commands and the emulation device is available for a new test. Optionally, the number of clock cycles CLK executed prior to stopping the command sequence is recorded. It will also be possible to stop the execution of commands when errors remain after a predetermined number of CLK clock cycles executed.

During each test, the circuit CC is set in a selected initial state, and the circuit EC is positioned in a modified initial state with respect to the chosen initial state. The choice of the initial state and the command sequence executed depends on the analyzed circuit. In the case where the analyzed circuit is a circuit performing a sequence of commands determined, it will obviously be chosen to perform this sequence of commands. In the case where the analyzed circuit is a generic circuit that can execute all kinds of programs, it will be possible to use random command sequences.

In addition, it will be possible to analyze during the execution of the control sequence certain output signals having an important function in order to know if the circuit can, when it is subjected to a disturbance, have output signals which exhibit dangerous behavior.

An advantage of the emulation device of the present invention is that it allows compared to the known emulation device to achieve in a given time, more different simulations. Indeed, each test is stopped as soon as it is found that the errors introduced have disappeared. 1.2 Example of Implementation of the Comparison Circuit FIG. 3 is a more detailed diagram of an example of the signals exchanged between the logic circuits CC and EC, the memories CMem and EMem and the comparison circuit 110. The circuits CC and EC provide write / read control signals respectively WRQ and WR _E , address signals respectively @Q and @g and memory select signals CSQ and CS ^. The circuits CC and EC to provide or receive data signals _Q and ^ that are written or read in the EMMC and emem memories. The comparison circuit 110 receives the write / read control signals WR _E , WRQ, the address signals @g and @Q, the selection signals CSQ and

CS ^ and the data signals dg and d _Q. Six switches 120, 121, 122, 123, 124 and 125 allow the address signals @E, @Q, the control signals WR _E and WRQ and the selection signals CSQ and CSg supplied to the memories CMem and EMem to be controlled by the comparison circuit 110 and not by the logic circuits CC and EC.

When the signal CS ^ (CSQ) is active, the memory EMem (CMem) provides data on the data signal d ^ (d _Q ) when the signal WR _E (WRQ) controls a reading at an address indicated by the signal d @g address. No data is written on the signal _E (dc) when the signal CS _E (CSQ) is inactive. When the signal WR _E (WRQ) commands a write to an address @ _E (@Q), the memory EMem (CMem) does so only if the signal CS _E (CS _C ) is active. When the comparison circuit 110 wishes to read or write data to a given address of the EMem memory, it controls the switches 120, 121 and 125 in order to be able to control the signals @ _E , WR _E and CS _E. Similarly, when the comparison circuit 110 wishes to read data at a given address of the memory CMem, it controls the switches 122, 123 and 124 in order to be able to control the signals @Q, WRQ and

CSQ.

The comparison circuit 110 switches the driver 120, 121 and 125 so as to access the _E @ signals, WR and CS _E _E when it wishes to read or write a bit error E. The dif ^¬ ence between the read / write an error bit E and a data item is optionally indicated by means of a signal not shown.

Prior to the execution of a command by the circuits EC and CC, the comparison circuit 110 controls the switches 120 to 125 so that they connect the memories CMem and EMem to the circuits CC and EC. During the execution of the command, the comparison circuit 110 analyzes the signals emitted by the circuits CC and EC and performs various actions described hereinafter.

1.2.1 Active CSQ and CS _E selection signals

When the EC circuit controls a write and the DC circuit controls a read through write / read control signals WR _E and WRQ, it is unlikely that the data written in the EMem at @ _{E will} be identical to the data currently stored in the CMem at @ _E. The comparison circuit 110 interrupts the sequence of commands executed by the circuits CC and EC.

According to a simplified version of the comparison circuit 110, the comparison circuit 110 controls the switches 120 and 121 to read the error bit E corresponding to the address @ E- If the error bit is equal to 0, it sets it to "1" and it increments the counter 111.

According to a more sophisticated version of the comparison circuit 110, the comparison circuit 110 drives the commu ^¬ torters 122 and 123 to perform a reading of the CMem memory at the address @g. In the case where the addresses @g and @Q are identical, this reading may not be performed. The read data is compared to the data written in the EMem memory at the address @g. In parallel or subsequently, the comparison circuit 110 reads the bit E corresponding to the address @g by controlling the switches 120 and 121 in order to be able to read in the memory EMem. The action then performed by the comparison circuit is a function of the difference or not the data and the value of the bit E read at the address @g. In the case where the data differs and the bit E read at the address @g is zero, the new error is raised by setting the bit E to the address @g at "1" and incrementing the counter 111. In the case where the data are identical and the bit E read at address @E is set to "1", there are no more errors at the address @g. The bit E is then set to "0" and the counter 111 is decremented. In other cases, the comparison circuit 110 does not modify the bit E or increment or decrement the counter 111. The possible actions are summarized in the following table (1).

Once the comparison circuit 110 has performed all of these operations, the execution of the command sequence resumes.

When the EC circuit controls a read and the DC circuit controls a write through the write / read signals WRg and WRQ, it is there also unlikely that the data written in the CMem memory at the address @Q are identical to those currently stored in the EMem memory at the address

@Q. The comparison circuit 110 interrupts the sequence of commands executed by the circuits CC and EC.

According to a simplified version of the comparison circuit

110, the comparison circuit 110 drives the switches 120 and 121 to read the error bit E corresponding to the address

@Q. If this bit is equal to 0, it sets it to "1" and increments counter 111.

According to a more sophisticated version of the comparison circuit 110, the comparison circuit 110 controls the switches 120 and 121 in order to read the EMem memory at the address @Q. In the case where the addresses @E and @c are identical, this reading may not be performed. The read data is compared to the data written in the CMem at @Q. The comparison circuit 110 performs a reading of the bit E corresponding to the @Q address. The Possible actions of the comparison circuit are summarized in the following table (2).

When the EC and CC circuits both control a write, it is necessary to compare the addresses @E and

@C as well as the data dg and ÔQ. As before, the comparison circuit 110 interrupts the command sequence executed and, if necessary, controls the switches 120 to 123.

In the case where the addresses are identical, the operations performed by the comparison circuit are simpler and fewer. In a simplified version, the comparison circuit 110 sets the error bit E corresponding to the address @E if the data are different to "1" and it increments the counter 111. In a more refined version, the circuit the comparison of the bit E corresponding to the address @ E- In the case where the data differ and the bit E read at the address @E is zero, the new error is raised by setting to "1" the bit E and incrementing the counter 111. In the case where the data are identical and the bit E read at address @E is set to "1", there are no more errors at the address @ E- The bit E is then set to "0" and the counter 111 is decremented. In other cases, the comparison circuit 110 does not perform any modification of the bit E, nor of incrementation or decrementation of the counter 111.

In the case where the addresses differ, it is unlikely that the data written to the @Q address in the CMem memory will be identical to the data present in the EMem memory at the @Q address. Similarly, it is unlikely that the dg data written at the @g address in the EMem memory will be identical to the data present in the CMem at @g. In a simplified version of the comparison circuit 110, the error bits E corresponding to the addresses @E and @Q are set to 1. In a more perfec ^¬ ed version of the comparison circuit 110, the comparison circuit 110 reads the data present at the address @Q in the EMem memory. The comparison circuit reads the bit E corresponding to the @Q address. The possible actions of the comparison circuit 110 are summarized in the table (2) above. Similarly, the comparison circuit 110 reads the data present at the address @E in the memory CMem and reads the bit E corresponding to the address @g. The possible actions of the comparison circuit 110 are summarized in Table (1).

When the EC and CC circuits both control a read, the comparison circuit does not intervene and the command sequence executed is not interrupted. 1.2.2 At least one selection signal CSg and CSg is inactive

In the case where the two signals CSQ and CS ^ are inactive, the two memories CMem and EMem are inactive. No writing or reading can be done. The comparison circuit 110 is inactive. In case the CSQ signal is active and the signal

CS ^ inactive, the CMem memory can be written or read. The EMem memory is inactive. A difference between the two memories can be introduced or possibly deleted when the circuit CC makes a write in the memory CMem at the address @Q. In this case, the comparison circuit 110 stops the execution of the command sequence and controls the switches 120, 121 and 125 to access the EMem memory. The comparison circuit 110 modifies the state of the selection signal CS ^ so as to activate the memory EMem. In a simplified version of the comparison circuit, the error bit E corresponding to the address @ _Q is set to 1. In a more sophisticated version of the comparison circuit 110, the comparison circuit 110 reads the data present at the address @ _Q in the EMem memory. The read data is compared to the data written in the CMem at @ _Q. The comparison circuit reads the bit E corresponding to the address @ _Q. The possi ^¬ ble actions of the comparison circuit 110 are summarized in Table (2).

In the case where the signal CS ^ is active and the signal CS _Q inactive, a sequence of steps similar to that described above is implemented when the circuit performs a write in the EMem memory, the role of the memories being reversed. . The possible actions of the comparison circuit 110 are summarized in Table (1). In the remainder of the description, only the cases where the selection signals CS 1 and CS _Q are active are considered. Those skilled in the art will easily define the function ^¬ ment of the various components of the emulation device depending on whether or not the selection signals CS and CS ^ _Q. 2. Variations of memory / error detection in memory

2.1 Detection variant

In one embodiment of the emulation device of the present invention, the counter 111 is deleted. A simple OR gate receiving each of the error bits E is connected to the detection device 107.

The use of an OR gate simplifies works ^¬ the comparison circuit 110 previously described because it is no longer necessary to provide an increment control or decrementation of the counter 111. The comparator 110 performs circuit against by all the other operations described above for each case. When a write is made in one or more memories, a comparison is made between the data written in a memory at a given address and the data present in the other memory at the same address. If the data is different, the bit E is set to one if not zero. The OR gate gives the minimum information to know, whether or not there are errors in memory. 2.2 Memory dedicated to memorizing errors

The storage of the error bits E can be performed in a specific memory, independent of the EMem memory.

2.2.1 Adapted standard memory

FIG. 4 is an example of a memory dedicated to the storage of errors comprising a DECODER address decoder 130 making it possible to select a particular error bit E in an error bit memory 131. The memory 131 can be manufactured specifically or be performed in a programmable logic network. Each of the error bits of the memory 131 is connected to an input of an OR gate 132. The output of the OR gate 132 is connected to the detection circuit 107. Instead of writing and reading error bits in the EMem memory, the comparison circuit 110 makes writes and reads in the memory 131. The "0" or "1" positioning of the error bits is performed according to the same criteria as those described previously in relation to FIG. the figure

3.

2.2.2 CAM Memory

Figure 5 is another example of memory specific to error storage. The memory is of the content addressing type (CAM). The memory comprises a set of words W1 to Wn, where n is a positive integer. Each word Wi, i being between 0 and n, consists of an error bit Ei and an address value @i. The memory further includes an INTERFACE interface block, an address lookup module (@?) 136 and an error tracking module (E = O?) 137. Each address of the EMem memory containing erroneous data is stored in a "pointer" word of the CAM memory whose error bit is set to "1". The other words of the CAM memory are said to be "free", their error bit being set to "0".

The INTERFACE interface block receives Ctrl commands from the comparison circuit 110 and exchanges error bit values E and address @ with it.

When the comparison circuit 110 wishes to know if a datum of the memory EMem stored at a given address is erroneous, it indicates this address to the memory CAM. The address search module (@?) 136 then compares all the addresses of the pointer words to the indicated address. The memory CAM then specifies the comparison circuit whether or not there is a pointer word which contains the indicated address.

Moreover, when the comparison circuit wishes to store the address of an erroneous data item of the memory EMem, it indicates this address to the memory CAM. The error tracking module 137 determines whether there remains a free word. If this is the case, the address of the erroneous data is stored in this word and its error bit is set to "1". This word then becomes a pointer word.

The error tracking module 137 can be realized in various ways. This is, for example, a counter which is incremented each time a free word becomes a pointer word, the erroneous addresses then being recorded in the CAM memory of the word W1 at the word Wn. It can also be a module capable of analyzing all the error bits E in order to find a possible free word. The general operation of the emulation device comprising such a CAM memory is as follows.

During the initialization phase of the emulation device, as previously described, the registers

RQ] _ to RQ3 of the circuit CC and the memory CMem are set in a "normal" initial state and the registers R ^ i to R ^ 3 of the circuit EC and / or EMem are set in a modified initial state with respect to the normal initial state. Error bits El to En of the CAM memory are all reset to "0". In the case where errors have been introduced into the EMem memory during the initialization phase, the addresses of these errors are written in words of the CAM memory and the error bits of these words are set to "1". .

During the emulation phase, the comparison circuit 110 performs, as previously, a comparison between the signals exchanged between the circuit CC and the memory CMem and the signals exchanged between the circuit EC and the memory EMem. The comparison circuit has to carry out verifi ^¬ tions each time a write is performed in EMEM memory and / or in the memory CMEM, interrupting, if necessary, the sequence of commands executed by the DC and EC circuits.

In the case where the circuit EC controls a writing of the memory EMem and the circuit CC controls a reading or an inactivity of the memory CMem, the comparison circuit 10 interrupts the sequence of commands and performs a reading of the memory CMem to the @g address. The data read in the CMem memory is compared with the data d ^. Depending on whether the data are different or not, the 110 performs respective comparison circuit ^¬ tively validation or invalidation of the address @g, the concepts of validation or invalidation address being defined below. We then resume the sequence of commands.

In general, the validation of a given address consists in querying the search module @? 136 of the CAM memory to know if a pointer word references this address and otherwise to query the error tracking module 137 to obtain a word in which to record the given address and set to "1" its bit error. The inva ^¬ lidation of a given address consists of interrogating the search module 136 to know if a pointer word references this address and, if necessary, to reset the error bit E of this word to "0" which then becomes a word "free". In the case where a counter 111 is used, the counter is incremented when a new address is stored ^¬ tred during an address validation, and the counter is decremented when an error bit E of a word pointer is reset to "0" during an address invalidation.

In the case where the circuit CC controls a writing of the memory CMem and the circuit EC controls a reading or an inactivity of the memory EMem, the comparison circuit 110 interrupts the sequence of commands and performs a reading of the memory EMem to the @Q address. The data read in the EMem memory is compared with the data <! Q. Depending on whether data different or not, the comparison circuit 110 performs respec tively ^¬ validation or invalidation of the address @Q. We then resume the sequence of commands. In the case where the circuits CC and EC both control a write and the addresses @Q and @g differ, then two sets of operations are performed after the interruption of the command sequence. The first is to read the EMem memory at the @Q address and to compare the data read with the data Ô _Q. Depending on whether the data is different or different, the comparison circuit 110 respectively performs a validation or invalidation of the @Q address. The second is to read the CMem memory at the address @g and compare the data read to the data d ^. Depending on whether the data is different or different, the comparison circuit 110 respectively performs a validation or invalidation of the @g address. We then resume the sequence of commands.

In the case where the circuits CC and EC both control a write and the addresses @Q and @g are identical, depending on whether the data differ or not, the address @ E- is respectively validated or invalidated. This validation or invalidation can be performed without interrupting the sequence of commands.

In order to limit the duration of interruption of the sequence of commands, the first step of the validation or the address invalidation, namely the search for a pointer word containing this address, can advantageously be performed simultaneously with a reading or writing memories CMem and EMem. In addition, the possible second step of the validation or invalidation, consisting in setting to "1" or "0" an error bit and in the case of the validation to record an address, can be performed simultaneously. at a write / read step in the memories CMem and EMem can be controlled during the resumption of the command sequence. In the embodiment shown in FIG. 5, the error bits El to En are connected to an OR gate 135 whose output is connected to the detection circuit 107. This makes it possible to quickly detect whether or not there are errors. in the EMem memory. Furthermore, it is possible to connect all the error bits El to En to an AND type logic gate, not shown. Thus, when all the words of the memory CAM memorize addresses containing erroneous data, the AND gate delivers a "fill" signal. Such a filling signal may optionally be provided by the error tracking module 137 when it no longer finds free words. When such a filling signal is emitted, it is possible to stop the execution of the command sequence by the circuits EC and CC. It will be noted that the memory CAM can contain a restricted number of words W1 to Wn, much lower than the number of words of the memory EMem. The number of words in the memory CAM corresponds for example to the maximum number of "acceptable" faults when executing a sequence of commands. When the emulation is stopped and the CAM memory includes pointer words referencing erroneous data in the EMem memory, it may be useful to know these erroneous data for example to compare them to the correct data stored in the CMem memory. To do this, we can read the addresses of the pointer words of the CAM memory then read the EMem memory and possibly the CMem memory for each of these addresses. It is also possible to add an additional field of data to each word of the CAM memory. In this case, when an address validation is performed in the CAM memory in an existing pointer word or in a new pointer word, the value of the data stored in the EMEM memory at the given pointer word field is recorded in the given field of the pointer word. the address stored in this pointer word.

In addition, in order to quickly browse the CAM memory to "unload" the addresses and possibly the data stored in the pointer words, we can provide a scanning device, known as the English "priority encoder". This device runs through the words Wl to Wn. If the error bit E of the word W1 is at "1", it reads the word W1 and returns "0" its error bit E. Then it looks if the error bit of the word W2 is at "1 "and if necessary it reads the word W2 and returns" 0 "its error bit and so on to the word Wn. 3. Deleting the EMem memory

According to an alternative embodiment of the emulation device according to the present invention, the EMem memory is deleted. The signals @g, WR _E and CS ^ supplied by the circuit EC are only transmitted to the comparison circuit 110. The function of the comparison circuit 110 is firstly to compare the signals supplied by the circuit EC with the signals supplied. by the DC circuit, and secondly to supply and process the data of _E when the EC circuit controls respectively a reading and a writing. In order to perform this new function, the comparison circuit 110 is connected to a memory CAM which comprises all the elements described above in relation to FIG. 5 and which furthermore comprises for each word Wi a datum di as represented in FIG. dotted in FIG. 5. The association of the CAM memory and the new functionality of the comparison circuit 110 constitutes a virtual EMem memory. The EC circuit reads and writes in virtual EMem memory in the same way than with real EMem memory. The memory CAM stores only the erroneous data of the memory EMem, that is to say the data of the memory EMem which differs from the data of the memory CMem. Each erroneous data is stored with its address in a word of the CAM memory. The correct or non-erroneous data of the EMem memory are read from the CMem memory.

During the initialization phase, the error bits E of the words of the memory CAM are reset to "0". In the case where the modified initial state includes errors in the EMem memory, each error is stored in the CAM memory. The erroneous data and their addresses are written in a set of words and the error bits of these words are set to "1". The interactions between the comparison circuit 110, the CAM memory, the CMem memory and the CC and CE circuits are described below.

3.1 The EC circuit reads

When the EC circuit reads, the comparison circuit 110 performs a series of operations described below. The comparison circuit interrogates the search module (@?) 136 of the memory CAM in order to know if a pointer word stores the read address @g. If this is the case, the data stored in this pointer word is read. Otherwise, the comparison circuit looks at whether the DC circuit reads at an @ _Q address identical to the @g address. If this is the case, the data read from the memory CMem is copied back to the data signal d1. In other cases, the command sequence is interrupted and the comparison circuit 110 controls a reading in the CMem memory at the address @g. The read data is provided on the data signal d1.

It is then interested in read or write command requested by the circuit CC simultaneously with the read command requested by the EC circuit before the interrup ^¬ of the command sequence. In the case where the DC circuit controls a reading in the memory CMem, this one is carried out normally.

In the case where the circuit CC commands a write in the memory CMem, the search module (@?) 136 of the memory CAM is interrogated in order to know if a pointer word stores the address @Q. If this is the case, the data stored in this pointer word is compared with the data d that the circuit CC wishes to write to the memory CMem and if the data are identical, it is reset to "0" the error bit E of that memory. pointer word and if the counter 111 is used it is decremented. Otherwise, that is, if no word from the CAM memory stores the @Q address, a reading is read in the CMem memory at the @Q address and the data read is compared to the data as soon as the we want to write in the memory CMem. If the data is identical, then this writing is inconsequential. If the data differs, the error tracking module 137 of the CAM memory is interrogated in order to know if there remains a free word. If this is the case, the @Q address and the data read in the CMem memory are stored at this address. The data d is then written in the memory CMem.

3.2 The EC circuit performs a write

When the EC circuit makes a write, the comparison circuit also performs a series of operations described below. In the case where the circuit CC controls a reading, or inactivity of the memory CMem, the control circuit 110 performs the following operations. It looks for the @Q and @E addresses to differ, and if so it interrupts the command sequence and commands a read in the CMem at @g. The comparison circuit then see if the data in the memory at EMMC @g are dif ^¬ ferent data from ^ that the EC system wants to write in EMEM virtual memory. Depending on whether the data differs or not, the address is validated or invalidated @ E- The reading of the memory CMem is then carried out and the execution of the sequence of commands is resumed.

The validation of the @g address consists in inter ^¬ rogating the search module @? 136 of the CAM memory to know if a pointer word references this address and if so, to write the data d ^ in this pointer word, and otherwise to query the error tracking module 137 in order to obtain a word in which to record the given address, the data item and set to "1" its error bit E. The invalidation of the @g address consists of interrogating the search module 136 to find out if a pointer word references the @E address and if necessary, to reset the error bit E of this word to "0", which then becomes a "free" word.

In the case where the circuit CC commands a write in the memory CMem, the comparison circuit 110 performs the following operations. It looks first if the @g and @Q write addresses are identical. If so, it looks at whether the data d ^ and d ^ differ. Depending on whether the data differs or not, it performs a validation or invalidation of the @g address according to the method described above. In the case of a validation of the address @g, the data d ^ are stored in the memory CAM. In the case where the write addresses @g and @Q differ, the comparison circuit 110 interrupts the execution of the commands. It then reads in the CMem memory at the address @g and compares the read data with the data dg. Depending on whether or not the data differs, it carries out a validation or invalidation of the @ E-address. In the case of a validation of the @g address, the data of ^ are stored in the CAM memory. It then reads in the CMem memory at the @Q address and then compares the read data with the data that the DC circuit wishes to write to the DC memory. Depending on whether the data differs or not, it performs a validation or invalidation of the @Q address. In the case of a validation of the @Q address, the data read from the memory CMem are stored in the memory CAM. We then performs the writing of the data d ^ in the memory CMem and resumes the execution of the sequence of commands. 4. Restoring errors in memory

When the memory EMem does not find after a certain time a normal state corresponding to that of the memory CMem, it can be interesting to be able to analyze quickly which are the differences. A complete reading of the memories is possible but very expensive in time, especially since the size of the memories can be important. In the case where the emulation circuit of the present invention comprises a memory CAM, as described above in relation to FIG. 5, used for storing errors, it is possible to know the errors present more quickly.

In order to quickly establish a list of addresses of the EMem memory, real or virtual, for which the stored values differ from the values stored at these same addresses in the memory CMem, it is possible to provide the memory CAM with a scanning circuit, commonly called "priority encoder" in English, which identifies one by one the words of the CAM having an error bit of 1.

At the moment when it is desired to identify the errors in memory, the command sequence is interrupted. In the case where at least one error has been stored in the CAM memory, one or more error bits are set to one. The scanning circuit successively selects the corresponding words. With each selected word, the address written in this word and possibly the data are emitted by the memory CAM.

In the case where the "erroneous" data are not written in the memory CAM, successive readings are made in the memory EMem to recover the data corresponding to the sequence of addresses issued by the memory CAM.

An advantage of such a CAM memory is that it makes it possible to identify very quickly what are the errors present in the EMem memory, virtual or real. 5. Deleting part of the initialization phase

When the integrated circuit operates under condi tions ^¬ actual, a disturbance is likely to arrive on any other unknown logic element or n 'any storage element (register or memory). When a disturbance occurs on a storage element, in the majority of cases, only the value of an elementary register or a memory point can be modified. When a disturbance occurs on a logic element, the electrical pulse produced at the output of the logic element can propagate and affect several storage elements.

In addition, the synchronous integrated circuits are provided for executing at least one determined command sequence at the rate of a clock signal and an external disturbance may occur when executing any command, on any clock cycle of the command sequence. During a cycle following a disturbance, the values set in the registers can be erroneous. The circuit is then in an incorrect state. Certain values of the registers or memories differ from the values normally present in the circuit when it is in a "correct" state.

In actual use of the circuit, the probabi ^¬ ity as several disturbances happen when running a command sequence is very low. It will therefore be considered later that no disturbance occurs during the emulation of the circuit.

The emulation device of the present invention provides for positioning the DC circuit and the CMem memory in a "correct" state corresponding to the normal state of the circuit during a given cycle of the command sequence and to position the EC circuit and the CMem in an "incorrect" state having one or more errors with respect to this correct state. The emulation device then performs the remaining cycles of the command sequence after the given cycle of the command sequence. The emulation is stopped when the errors have disappeared or when a predetermined number of cycles has been executed. Once emulation complete, repositions the DC circuit and the memory CMEM in an "okay" ^¬ corre sponding to one cycle of the same sequence of commands or different from that of the previous and the EC emulation circuit and the memory EMEM in an "incorrect" state with respect to this correct state, then a new emulation is performed and so on.

Each cycle of the command sequence corresponds to a correct state of the circuit. In addition, for each correct state of the circuit obtained in a given cycle, there is a large number of possible incorrect states corresponding to the arrival of a disturbance in various parts of the circuit. Positioning the EC and DC circuits as well as the EMem and CMem memories in a correct or incorrect state requires a large number of serial writes and therefore takes time. In order to suppress the writing time of the storage elements, the device emulates ^¬ of the present invention provides to add items to the device as described in relation to Figure 2.

Fig. 6 is a diagram of an emulation device comprising the elements of the emulation device described above as well as new elements. As shown in FIG. 3, the logic circuit CC supplies the read / write control signal WRc and the address signal @Q to the memory CMem. The circuit CC supplies and receives data from / to the memory CMem. Likewise, the circuit EC supplies the write / read control signal WR _E and the address signal @g to the memory EMem. The circuit EC supplies or receives data dg to / from the memory EMem. The selection signals CS 1 and CS 2 are not provided in this circuit, however those skilled in the art will be able to adapt the circuit to the presence of such signals. An IMem memory that can be accessed only for reading is added. Each EMMC memory EMEM and contains additional memory bits with respect to the memories precedesM ^¬ used. Each memory includes for each address a validation bit V initially set to 0 in this example. A Control circuit (CNT) 140 receives the address signals @g and @Q as well as write / read signals WR _E and WRQ. The control circuit (CNT) 140 can read or write the validation bits V associated with each of the memories CMem and EMem through devices not shown. Two commuta ^¬ tors 141 and 142 allow the data _E and ^ are provided by the memory IMEM CBS and DC circuits respectively.

When the circuit is positioned for the first time in a correct "pseudo-initial" state, corresponding to a correct state of the circuit obtained during a given cycle of the command sequence, instead of writing the correct values in the CMem memory, the correct values are written in the IMem memory. In the case where the selected incorrect state includes errors in the EMem memory, the erroneous data are written in the EMem memory and the validation V and error E bits corresponding to the addresses of these data are set to "1".

When the DC and EC circuits write to their respective memories, the data is written to the requested address and the validation bit V corresponding to this address is set to 1.

When a DC or EC circuit controls a reading, the CNT control circuit 140 looks in the memories CMem or EMem what is the value of the validation bit V corresponding to the read address. If the validation bit V is equal to 1, the read data are those present in the CMem or EMem memory at this address. If the validation bit V of the memory CMem or EMem is at 0, the control circuit 140 controls the switches 141 or 142 in order to supply data to the circuit

CC or EC, the data stored in the IMem memory at the corresponding address.

In the case where the circuits CC and EC both control a reading but at different addresses @g and @Q, it is possible that two readings in the memory IMem are necessary if the validation bits V corresponding to addresses @g and @ _Q are both at "0". It is therefore necessary to interrupt the execution of the command sequence in order to perform the two successive reads in the IMem memory. One way to avoid such interruptions is that the IMem memory is a dual access memory in which it is possible to perform two simultaneous readings.

An advantage of an emulation device comprising a specific memory for maintaining the pseudo-initial state of the memories EMem and CMem, is that it makes it possible to save time. Indeed, it is no longer necessary, before making a new emulation of the circuit, to rewrite the set of memories CMem and EMem in order to put the memory CMem in the correct pseudo-initial state and the memory EMem in a state possibly incorrect compared to the pseudo-initial state of the memory CMem. It suffices to reset the validation bits V of the memories CMem and EMem to "0" and possibly to introduce errors into the memory EMem, by setting to "1" the validation bits V and of the error E associated with the erroneous data. . In addition, at the end of a series of emulations all starting from the same pseudo-initial correct state stored in IMem, it is possible to perform a new series of emulations from another correct state. pseudo-initial stored in IMem memory by changing only one or possibly some data IMem memory. The data modification (s) for example correspond to the modifica ^¬ tions of the CMem memory normally controlled by the circuit CC during the execution of one or more cycles of the command sequence. Thus, it is possible to successively carry out several series of emulation starting from pseudo-initial states corresponding to the correct states succes ^¬ sifs of the circuit during the execution of the sequence of commands. 6. Removing CMem and EMem memories

In the case where the emulation device comprises an IMem memory memory of a pseudo-initial correct state memories associated with the circuits CC and EC, it will be possible to delete the memories EMem and CMem and instead use two content addressing memories (CAM) respectively called CAM-E and CAM-C. In this case, the words of the CAM memories each include an address field and a data field. The words of the memory CAM-E further comprise an error bit E. The words of the memory CAM-C further comprise a validation bit V.

The memory CAM-C stores "write" data corresponding to the data written by the circuit CC in the virtual memory CMem during the execution of the sequence of commands.

The memory CAM-C includes a search module whose function is to search, among the set of words having a validation bit V to "1", a word storing a given address, and a tracking module listing the words free and indicating on request a free word CAM-C memory, that is to say a word whose validation bit V is "0". The validation bits V are reset to "0" before each emulation.

When the DC circuit controls a read at an @ _Q address, the CNT control circuit interrogates the search module of the CAM-C memory in order to know if the @ _Q address is stored in a word having a validation bit V to "1". If this is the case, the data memorized in this word is supplied to the circuit CC. Otherwise the data is read in the IMem memory.

When the DC circuit commands a write to an @ _Q address, the CNT circuit asks the search module if the @ _Q address is stored in a word of the CAM-C having a validation bit V at "1". If this is the case, the d data are written in this word. Otherwise, the circuit CNT asks the tracking module of the memory CAM-C to find a free word in order to memorize in this word the address @ _Q and the data d ^ and to set to 1 its validation bit V. When the EC circuit controls a read or a write, the comparison circuit performs the operations described in chapter 3 by ordering if necessary readings in the virtual CMem memory. According to a variant of the emulation device precedesM ^¬ described, the words of the CAM-E memory further comprise a validation bit V. The E-CAM memory is used for storing two types of data: data "write "corresponding to the data written by the EC circuit, in the virtual EMem memory, during the execution of the command sequence, and the" erroneous "data corresponding to the data of the virtual EMem memory which differs from those of the virtual CMem memory . The validation bits V of the words containing write data are set to "1". When the EC circuit controls a read or write in the EMem memory, the CNT circuit performs substantially the same operations as those described for the DC circuit and the CMem memory.

Of course, the present invention is susceptible of various variations and modifications which will be apparent to those skilled in the art. In particular, the analyzed circuit described above comprises a single memory but the emulation device applies similarly to a circuit comprising one or more memories, possibly of different types. In addition, it will be possible to eliminate the correct circuit CE and replace it with storage elements providing for each command executed by the error circuit EC, the values that would contain the registers Rgi to Rg3 and the memory CMem, if the EC circuit and EMEM memory had been in the "correct" state prior to emulation of the circuit.

In addition, the composition of the test platform 101 comprising all the logic circuits and memories previously described is particularly suitable to be performed in a programmable logic array. However, such a test platform can also be performed in a software, the set of logic circuits and memories then being described in a computer file. The execution of a command sequence by such a software test platform is then performed by means of a circuit computer simulator.

Claims

A method for emulating or simulating the operation in the presence of disturbances of a circuit capable of executing a sequence of commands, the circuit comprising logic elements (L _E ], L _E 2, ^L _E 3) and first storage elements (REI ' ^R E2' ^R E3 'EMem), characterized in that it comprises the following steps:

- put the circuit in an incorrect state, in which the value of at least one storage element is changed with respect to a correct state of the circuit; - start the execution of a sequence of commands;

- provide in second storage elements (RQ] _, RC2 'RC3' CMem), the normal values that would contain the first storage elements after the execution of each command if the circuit had been put in the correct state;

comparing, after each command executed and by means of comparators (C1, C2, C3, 110) activated simultaneously, all the values contained in the first and second storage elements; and - stop the execution of the commands if the values contained in the first and second storage elements become identical.

2. Device for emulating the operation in pre ^¬ ence of disturbances of a circuit capable of executing a sequence of commands, the device comprising:

a test circuit identical to said circuit and comprising logic elements (L _E ] _, L _E 2, LE 3) and first storage elements (R _E ] _, RE2 ' ^R E3' ^EMem ) '

means (102, 103) for putting the circuit in an incorrect state in which the value of at least a first storage element is changed with respect to a correct state of the circuit;

means (104) for initiating execution of a command sequence; second storage elements (RcI '^ C2' RC3, CMem) loaded by the normal values that would contain the first storage elements after each command if the circuit had been in the correct state before the execution of the commands;

- comparators _(C] _, C2, C3, 110) for providing after each command executed if the values in the first and second different storage elements; and

interruption means (107) controlled by said comparators.

3. Device according to claim 2, comprising a second circuit (CC) identical to said test circuit (EC), the second storage elements being the storage elements of the second circuit, and comprising means for putting the second circuit in a correct state. , said means for initiating the execution of a sequence of commands acting on the two circuits.

4. Device according to claim 2, wherein the first storage elements comprise registers (REI ' ^R E2' ^R E3) placed between the logic elements (L _E ] _, L _E 2,

L _E 3) -

5. Device according to claim 2, wherein the first storage elements of said test circuit comprise at least one memory (EMem) storing data words each consisting of at least one bit.

6. Device according to claims 3 and 4, wherein some or all comparators (C _] _, C2, C3) compare the contents of the registers of each of the circuits.

7. Device according to claims 3 and 5, comprising for each memory of said test circuit, an additional storage means comprising an error bit (E) for each address of the memory, one or more comparators (110) analyzing the addressed signals. to a given memory of said test circuit and the signals addressed to the memory of the second identical circuit to the given memory, in order to activate or deactivating an error bit at a given address when a difference between the data words stored in the two memories at that determined address appears or disappears, an error detection circuit (111, 122, 123) indicating to the means of interrupt if at least one error bit is activated.

8. Device according to claims 3 and 5, comprising for each memory of said test circuit, a content addressing memory consisting of words intended to each store at least one address and an error bit, one or more comparators (110). analyzing the signals sent to a given test said memory circuit and the signals sent to the memory of the second identical circuit to the data memory in order to detect the appearance or disappearance of a consis error ^¬ both a difference between the data words stored in the two memories at a given address, the occurrence of an error causing a statement of the address determined in a word of the address memory by the content associated with the memory in question, and an activation of the error bit of this word, the disappearance of an error causing the deactivation of the error bit of the word storing the determined address, an error detection circuit (111) indicated nt to the interrupt means if at least one error bit is activated.

9. Device according to claim 7, wherein a memory of said test circuit is a virtual memory replaced by the association of a memory addressed by the content CAM and a pilot device connected to said test circuit and the associated memory of the second circuit corresponding to the virtual memory, a word of the memory CAM being provided for storing at least one data word, an address and an error bit, only the words of the virtual memory which differ from the words of the memory associated with being stored with their addresses in a word of the memory CAM by activating its error bit, reading a data word in the virtual memory at a given address consisting for the device pilot to see if an erroneous data word corresponding to the given address is stored in a word of the CAM memory whose error bit is activated and if not to request a reading at this address in the associated memory, writing a word in the virtual memory to a given address consisting for the pilot device to compare this word to the word written to the address given in the associated memory, and if there is a difference to memorize this word in a word of the CAM memory by activating its error bit, the pilot device detecting the differences between the signals exchanged between the associated memory and the second circuit and the signals exchanged between the virtual memory and the test circuit in order to identify the situations that lead to differences between the data words stored in the virtual memory and those stored in the associated memory, the erroneous data words of the virtual memory being m morisés in the words of the CAM by activating their error bits.

10. Device according to claims 7 or 8, comprising for each memory (EMem) of said test circuit, an identical memory called initialization (IMem) comprising the correct values of the test circuit memories corresponding to the initial state of the test circuit before the execution of a sequence of commands, and comprising for each memory of the test circuit

(EMem) and the second circuit (CMem), an additional storage means comprising a validation bit (V) for each address of the corresponding memory, and wherein a word read by the test circuit or the second circuit at a given address a memory comes either from the initialization memory when the validation bit corresponding to this address is not activated, or from this memory when the validation bit corresponding to this address is activated following a previous write to this address when the execution of the command sequence.

11. Device according to claim 10, wherein the memories of the test circuit (EMem) and their associated memories (CMem) of the second circuit are virtual memories each replaced by the association of a memory addressed by the content CAM (CAM-E, CAM-C) and a pilot device connected to the initialization memory, the circuit and the second circuit, the words of the CAM memories being provided to each store a data word (d), an address (@), a validation bit (V) and in the case of CAM memories replacing the circuit memories test, an error bit (E), a data word and its write address in a virtual memory being stored in a word of the memory CAM replacing this virtual memory by activating are validation bit, a data word provided during a reading of a virtual memory at a given address, coming from the memory CAM replacing this virtual memory or of the initialization memory according to whether the given address is stored in a word of the memory CAM having a enable bit enabled, l the erroneous data words of a memory of the test circuit being stored in words of the memory CAM replacing this memory by activating their validation and error bits.

Device according to claim 2, wherein the test circuit (EC), the second circuit (EC) and the comparators (C _] , C2, C3, 110) are physical elements that can be realized in a programmable logic array ( 101).