EP1573541A2

EP1573541A2 - Data storage method with error correction

Info

Publication number: EP1573541A2
Application number: EP02793205A
Authority: EP
Inventors: Micha[L Nicolaidis
Original assignee: Iroc Technologies SA
Current assignee: Iroc Technologies SA
Priority date: 2001-11-02
Filing date: 2002-10-31
Publication date: 2005-09-14
Also published as: WO2003038620A2; FR2831971A3; US7124348B2; FR2831971A1; WO2003038620A3; US20050028061A1

Abstract

The invention concerns a data storage method enabling error detection and correction in an organized storage for reading and writing words of a first number (m) of bits and optionally for modifying only part of such a word, comprising the following steps which consist in: associating an error detection and correction code with a group of a second number (k>/=1) of words; and at each partial writing in the group of words, calculating a new code of the modified group of words; performing a verification operation and, if an error occurs, carrying out an error correction of the modified word and/or of the new code.

Description

DATA STORAGE METHOD WITH ERROR CORRECTION

The present invention relates to the organization of a memory associated with error correction means.

Given the current miniaturization of integrated circuits and in particular memory circuits, the memory points ensure the storage of data bits by acting on an increasingly small number of charge carriers. Consequently, each memory point is more and more likely to be affected by an error, that is to say by an inversion of the memorized data (passage from 0 to 1 or from 1 to 0), in particular as a result of particle irradiation. To overcome this drawback, error correction codes have been developed, each memory word being associated with an error correction code. When reading the content of a word and the associated error correction code, and calculating a syndrome between the stored word and the error correction code, this syndrome makes it possible to determine whether the word is affected of an error or not, to determine the location of the error and to correct this error.

Examples of known error correction codes are the Hamming code and the Reed-Solomon code. It will be noted that a distinction is made between simple error detection codes, for example the association with a word of a parity bit, which allow to detect the existence of an error, error correction codes which make it possible to determine the location of the error and therefore to correct it.

An obvious disadvantage of using error correction codes is the amount of bits they require. For example, for words longer than four bits, a Hamming code requires n + 1 bits to allow the correction of an error, and only of an error, in a word of 2 ⁿ bits. This means that for an eight (2 ³ ) bit word, four bits of code will be required, and even five bits if a parity code is added to the error correction code. For a 64 (2 ⁵ ) bit word, five or six bits of error correction code will be required. It is clear that the relative area occupied by the part of the memory allocated to the error correction code depends on the length of the stored words and decreases when this length increases.

On the other hand, numerous memories are provided for making operations on relatively short words.

On the other hand, it is often used in the memories of organizations in which it is possible to change only a portion of a word. This is what is called maskable operations, that is to say that a mask is provided during a write operation in order to affect only some of the bits of a word. There is then a problem which is that the error correction code of the modified word no longer corresponds to this word.

This leads to associating an error correction code with each bit of a word, which requires, as we have seen above, the use of extremely long code words compared to the stored words. It is therefore an object of the present invention to provide a memory organization associated with an error correction system in which short words can be used while using a reasonable number of bits of error correction code, without excessively increasing the complexity or consumption of the circuit. Another object of the present invention is to provide a memory organization in which it is possible to carry out maskable operations and to use in a simple manner an error correction system. To achieve these objects, the present invention provides a data storage method allowing error detections and corrections in a memory organized to read and write words of a first number (m) of bits and possibly to modify only part of such a word, comprising the following steps: associating an error detection and correction code with a group of a second number (≥l) of words; and at each partial writing in the group of words: - calculate a new code of the modified group of words, - carry out a verification operation and, if an error appears, carry out an error correction of the modified word and / or of the new code .

The present invention also relates to a memory for the implementation of the method. The present invention also provides a method of memorizing data allowing detections and error corrections in a memory whose words are divided into several fields, the writing operations being able to be carried out on all of the bits of one or several fields, comprising the following steps: associate an error correction code, said field code, with each field of a word, and when writing in one or more fields of a word, activate a writing in the corresponding field code or codes, the values to be written in each field code being calculated from the values of the bits to be written in the corresponding field.

These objects, characteristics and advantages, as well as others of the present invention will be explained in detail in the following description of particular embodiments made without limitation in relation to the appended figures among which: FIGS. 1 to 3 illustrate structures of memory blocks according to the present invention. As shown in FIG. 1, given a memory provided for normally reading and writing words of m bits, the present invention provides for associating with a group of k words, that is to say a set of km bits, a unique EC error correction code. Thus, an error correction code is used for a set of km bits and no longer k error correction codes each of which corresponds to a set of m bits. As will be deduced from the numerical examples given above, this greatly reduces the size occupied in memory for error correction. Of course, this is done at the cost of a slight increase in the area occupied by the means for calculating the error correction code. However, this increase is negligible since the same calculation means are used and determine the correction codes for all the memory blocks. Furthermore, according to an embodiment of the present invention, an error detection code ED is added to each word of m bits, for example, in the case where there cannot be more than one error per word, a single bit of parity.

According to a variant of the present invention, illustrated in FIG. 2, in the case of short words, for example words of 4 bits (m = 4), the short words will preferably be grouped into long words of rm = M bits (by example 64 bits) and we will associate an error detection code, for example a parity code, ED, only with each long word, k long words will then be assembled into a group of words of kM bits with which is associated a code of EC error correction.

In the remainder of this description, unless specifically indicated, the term "word" may be interpreted as designating a short word or a long word. For example, if in a system we are supposed to use a memory whose word is 4 bits, we must provide 3 additional bits per word to implement the Hamming code. To reduce this cost, it is advantageous to introduce long words and to maximize their size to minimize the cost of the code, but one does not want to use long words of very large size to avoid a very high consumption during a reading. One can choose for example long words of 64 bits (r = 16). Then, we can choose groups of an even larger size (for example groups of 4 long words). In this case, we will associate a parity bit per long word, and a Hamming code (9 bits) per group of words. This gives a cost equal to 1/64 + 9/256 = 9.75% instead of 75% for a Hamming code per word of 4 bits. The number of bits of a word in a memory is generally determined according to functional constraints and operating speed of the system in which the memory is inserted. For the implementation of the present invention, we will modify the memory to increase the size of the word that we will be able to read during a reading cycle. Long words are thus obtained composed of r words of m bits which can be read in a single cycle. Thus, when the system activates a read cycle intended for a word of m bits, we will read a long word of rm bits which contains the short word for which the reading is intended, we will supply the system with this word of m bits, and we will locally use the long word of rm bits for the purposes of detection and / or correction of errors.

A memory normally provided for words of m bits cannot make readings on r words of m bits, which is necessary if one wants to use long words. It is therefore necessary to modify the memory which normally results in an extension of the system design time. Nevertheless, we find more and more, in known memory generators, memories with maskable operations. We can then choose such a memory using words of rm bits, so that we can do the reading on the long word, as well as maskable writing operations which will make it possible to write on the m bits of a short word or on a subset of these bits in the case where the original memory makes it possible to make maskable operations on a subset of the m bits of the word.

READING A WORD

To read a word (short or long), we proceed in the usual way, namely that we start by analyzing its error detection code. In most cases, there will be no error and the word will be read normally. If there is an error, all the words in the group of words are read and the position of the error is identified by calculating the syndrome with the error correction code. The error is then corrected at the position indicated. This avoids reading a whole group on each reading and, in normal times, a reading is no longer than with a conventional memory organization.

We may prefer not to add an error detection bit to each word in order to save memory space and we will systematically read a group of words and the error correction code each time we read them.

WRITING A WORD

The problem is a little more complex when writing. Indeed, each time a new word is written, the error correction code of the word group must be modified to adapt this error correction code to the modified word in the word group. Two embodiments of the invention will be proposed below to solve this problem.

First embodiment of a writing

Before each writing, we start by reading the word considered, and we examine whether its detection code ED indicates an error or not. If there is an error, we start by correcting the word read using the error correction code of the group of the as indicated above in relation to the read operation. Then, the initial read word or the corrected read word having been temporarily stored in a register, the new error correction code is calculated. A first way of calculating the new error correction code consists in taking into account the comparison between each bit of the initial word or of the corrected word and each bit of the newly written word as well as the old value of the code. This can be done in a conventional way by exclusive OR gate networks (XOR). It will be noted that this method is suitable for rewriting a complete word in place of the preexisting word or for rewriting only a few bits of a word (masked writing).

In the case where the group contains a single short or long word, and where the write operation is performed on a subset of bits of the word (maskable operation) or of the long word (maskable or non-maskable operation), you can only use the error correction code which then also serves as an error detection code. Still in the case where the group contains a single word, the calculation of the new code is done in a second way, directly from the values of the written bits and the values of the bits not affected by writing (unwritten). In this case, the unwritten bits of the word read must be corrected, if necessary. The correction will be made using the word read and its code. This correction is carried out in order to calculate the new code using correct values in the unwritten bits of the word read.

The operation to modify the error correction code in this second way requires that a reading (of a word or of an unwritten part of a word) be carried out before each writing.

In practice the use of a read cycle before writing is in many cases not a penalty because many memories systematically provide for the realization of a read before a write or use a dead cycle after or before each write.

Thus, certain memories, for example cache memories, use in a standard manner a read cycle before a write cycle. In this case, the techniques presented do not introduce a reduction in system performance. On the other hand, reading several words before writing is interesting because we can store these words in a buffer and, if we have just read one of these words, we can read very quickly by reading the word in the buffer. We can also write several words in the buffer before writing the entire long word in memory. This technique is often used to increase the speed of read or write operations. Thus, the imperatives of reducing the cost of the code combine with the imperatives of increasing the speed.

In certain memories, for example DRAM memories, the cycle comprising a reading followed by a writing exists in a standard manner for reasons specific to the operation of the memory. In other memories, it is necessary to add a read cycle before each write.

According to one aspect of the present invention, the operation of the memory is modified in order to be able to read and write sequentially a word or a part of it in the same memory access cycle. This is possible, because, the word being selected at the start of the cycle, the read amplifiers are first activated in order to be able to read the word, and then the write amplifiers are activated for all the bits of the word or of a part thereof. of these, to perform a non-maskable or maskable writing. This modification eliminates the read cycle which must precede a write cycle, but the cycle time will be extended.

According to a variant of this first embodiment of the present invention, in the case where it is assumed that there cannot be more than one word affected by errors in a group of k words of m bits, rather than using an error correction code associated with the km bits, we can calculate an error correction code for each word of m bits, and take as error correction code from the group of words the Exclusive OR function (XOR) of the k calculated codes. The indication of the words in which the possible error will exist will be given by the error detection code (ED) associated with each word. Of course, in this case, if more than one error detection code associated with more than one word indicates an error, it will be known that there is an uncorrectable error.

Optimization of the read-write synchronization of the first embodiment

The present invention also aims to optimize the speed of reading / writing. In the foregoing, it has been indicated that to perform a write operation in certain bits of a word, the actions in the following list are carried out.

1) read the existing word, (it will be recalled that in the present text the term "word" designates a short word or a long word),

2) read the error correction code, by abbreviation "code", of this word,

3) correct the errors of the word read, if there are any,

4) modify the word read by replacing the values of the bits in writing positions with new values,

5) calculate the code of the modified word (new code), 6) write the new values in the writing bits of the word, or write the modified word in full, 7) write the new code.

We see that the word is read, modified and written (actions 1, 4 and 6). As the modification consists in substituting, for a part of the word read, data already ready, there is no delay induced by the modification. However, the word read must be checked by its code and corrected if an error is detected. These operations require time to be completed and may introduce an additional delay between the operation reading and writing. This is particularly true if reading and writing are performed in the same cycle, since the data is written immediately after reading. On the other hand, when the reading and writing are accomplished in two successive cycles, there may be a certain time available between the instant of reading the data and the instant of writing (for example the data may be available before the end of the reading cycle). However, depending on the type of memory, this time can be very short, or even zero. For example, in certain types of memories, the data to be written must be placed at the inputs of the memory for a certain period of time, before the start of the writing cycle (set-up time).

According to one aspect of the present invention, in order to eliminate the additional delay induced by the correction of the data, the modified word (or the values of the modified bits) will be written before the end of the verification and correction of the data read. This verification will be carried out in parallel with the writing and in the event of error detection, the corrected read data is rewritten. Obviously, during this new writing, the values of the bits in writing positions are replaced in the corrected word by the new values to be written in these positions. In this way, in most cases, that is to say when there is no error, the successive read and write operations will be carried out without additional delay, and an additional cycle d 'writing is only added when an error is detected. We can then generate a signal to indicate to the system that the memory is not accessible. The system can react to this signal by putting itself, for example, in a waiting cycle. Note however that writing the correct word is not essential because the error will be detected and corrected the next time we read the word, as long as we have correctly calculated and memorized the new correction code.

There is also a delay introduced for calculating the code of the modified word. This calculation must be done systematically. tick, i.e. at each read / write cycle. We have seen that for each write in the memory, the code must be read followed by a write of the new code (actions 2 and 7). The time available between reading the code and writing it may be insufficient to calculate the new code. In order to avoid degrading the operating speed, the new code must be prepared in advance, that is to say before reading the previous code. This constraint leads to using the second way of calculating the code, that is to say to calculating the new code from the value of the bits to be written in the write positions of the word read and the value of the other positions of the word read. In fact, the first way of calculating the new code uses the code read to calculate the code to be written, and introduces a delay between the moment when the code is read and the moment when the new code is ready for writing. On the other hand, the second way of calculating the new code calculates the code to be written from the bits to be written in the word and the bits read in the unwritten positions of the word. You can then read the word and start calculating the new code before reading the old word code.

Separate memories (ie independently controllable in read / write) are used for the data words and for the corresponding error correction codes. In the code memory, the operations will be shifted in time with respect to the operations in the word memory. In this way, there is time to calculate the new code beforehand and to write the new code, without introducing any delay between reading the old code and writing the new one. In this way, the duration of the code memory cycle will not be affected. On the other hand, this offset between the cycles of the two memories can delay the correction of errors in the word and in its code, because the code is read with a delay compared to the reading of the corresponding word. Note however that the delay in reading the code will not be entirely added to the time required to correct the word. Indeed, the calculations required for the correction of the word read can begin before reading the code, because the first part of these calculations uses only the word read. In fact, the correction usually begins with the calculation of the code of the word read in order to then compare it with the code of this word stored in the code memory. However, the correction of the word can introduce a delay in reading.

We have two types of reading: the readings introduced before a writing to allow the calculation of the new code, and the readings carried out in a normal reading cycle. In the first case, the delay introduced by the error correction can be avoided by using the technique described above to avoid the delay in writing the word. Using this technique, we will calculate the code before correcting a possible error in the word read, and we will write it in the memory of the code without waiting for the word to be corrected. We correct the word read in parallel, and only in the rare situation where we have detected and corrected an error, we recalculate the code using correct data and rewrite it in the code memory. In this case, a signal is activated which indicates to the system that the memory is not accessible. In a cycle nor ^¬ bad read, this delay can be avoided by using the tech ^¬ nique disclosed in the French patent application No. 01/10735. According to this technique, the data read is immediately used by the system, without waiting for the correction of any errors. In parallel, control is carried out and corrections ^¬ read data and only if an error is detected, stops the operation of the system and the read data is propagated to the corrected parts of the system contaminated by the erroneous read data.

According to another variant of the first embodiment realized ^¬, a memory using dual-port: the first port to take readings and the second of writes. If the cycle i of the memory is a read cycle, the read operation will be performed by the first access. If cycle i is a writing cycle, we will read by the first access the word or the long word concerned by writing during cycle i, then we will perform 1 writing during cycle i + 1 by the second access, leaving the first access available to do the normal operation corresponding to the cycle i + 1. This operation must be read, because even if the normal operation of the cycle i + 1 is a writing, we have seen that the writing will be carried out at the following cycle (i + 2), while during the cycle i + 1 we will read the word concerned by the writing.

Usually in two-access memories, it is forbidden to read and write in the same word during the same cycle. Thus, there will be a problem, if the reading and writing carried out during the cycle i + 1 affect the same word. However, in this case, the data requested by the reading is at the input of the second access. We will then use this data to provide the data requested by the reading. Since the writing can be done on only part of the word, the input data of the second access may not understand all the bits requested by the reading. To avoid this problem, the bits of the word read are stored at the end of cycle i, and some of these bits are replaced by the write bits found at the input of the second access during cycle i + 1. This will provide all the bits that can be requested by reading the i + 1 cycle.

The techniques described above to avoid the increase in the duration of the memory cycle, caused by the calculation of the code and the correction of the data, can also be used in the case of this variant of the first embodiment. For example, we will use separate memories for the data words and for the corresponding error correction codes. In the code memory, the operations will be shifted in time with respect to the operations in the word memory. However, dual access memories allow usually to use independent clocks for both accesses. In this case, the access used for the writes can be clocked using a clock offset from the clock used to clock the access used for the readings. By choosing this offset adequately, there can be between a reading and the following writing sufficient time to calculate the new code, which could in this case be carried out in the first or the second way. Using a two-port memory instead of a single-access memory will have a cost. However, in certain situations, two-access memories are available for making single-access memories. Thus, certain families of FPGAs include on-board memories with two accesses, in order to cover the needs of users needing a memory with single access and those who need a memory with two accesses. Thus, the user needing a single access memory can advantageously carry out the present variant of the first embodiment.

Second embodiment of a writing According to a second embodiment of the present invention, it is sought to avoid reading bits at bit positions where one must then write to avoid the abovementioned drawbacks of the first embodiment. For this, each time we want to make a masked writing in a short word, or a masked or non-masked writing in a word of a long word, we simultaneously write the writing positions and read the other word positions (short or long). Many existing memories can be adapted to the implementation of the present invention. For example, it is relatively simple to modify an existing memory so that, each time you address a word, connect the bit positions in which you want to write to a write amplifier and the other bit positions of the same word. to a sense amplifier. According to this second embodiment, the new error correcting code (and the new error detecting code if applicable) is calculated, using the value of the bits to be written and the value of the other bits of the word, or of the word long according to the second variant of code calculation implementation presented above. The invention also provides for detecting and correcting an error in the bits read before using them to calculate the new code.

According to one aspect of the second embodiment, the code associated with the word (short or long) is capable of detecting and correcting an error in the unwritten positions of the word read without knowing the value of the written positions.

This second embodiment applies more particularly in the case where the words are short and / or where a masked writing is made, that is to say where a writing is made only in certain bits of a word. For example, as illustrated in FIG. 3, we want to write in the two bit positions marked with a cross of the second word, or in a "short word" constituting an element of a "long word".

According to a first variant of this second embodiment, the bits read are considered and all the possible values are given to the bits modified by the write operation. For each of these values, the word syndrome (short or long) is determined using its error correction code. It is clear that, among all the possible values, there is the value of the initial bits. Then, for this value, if there is no error in any of the bits read from the word, the syndrome will indicate a zero error. It will then be known that the new error correction code can be validly calculated from the newly written bits and the read bits. If the minimum of the number of errors detected is not zero, we will know that there is an error in the unwritten bits of the word or long word, and for this minimum value, we will correct an error before proceed with the calculation of the new code as indicated above.

According to one aspect of the second embodiment, the code associated with the word (short or long) is capable of detecting an error in the bits read from the word, combined with any error in the bits targeted by the writing, of distinguishing the word which contains only the error in the bits read, words which contain the error in the bits read as well as any errors in the bits intended for writing, and to correct the error in this word.

If the error in the bits read of the word can affect at most t bits, if the maximum number of bits of the word affected by a writing is q, it is expected that the code associated with the word can detect any error of multiplicity less than or equal to q + t, and among any group of errors whose multiplicities are greater than 0 and less than or equal to q + t, can distinguish the error with the smallest multiplicity, and can correct in a word or long word any error whose the multiplicity does not exceed t. According to one aspect of the first variant of the second embodiment, during a writing on certain bits of a word (short or long), the word code is used to check all the words using all the possible values for the positions of the word targeted by the writing as well as the values read in the other positions of the word or long word. If this check indicates a word without error, then the bits read contain no error. The values of the bits read, the values of the bits written and the code read are therefore used to calculate the new code. If on the other hand this verification does not find a word without error, then there is an error in the bits read and it must be corrected before calculating the new code. Since the word containing errors only in the read positions is distinguished by the code, the code will be used to correct the error in this word and thus obtain the correct values in the bits read. In an embodiment of the first variant, memories are used such that at each writing cycle, one writes either on a single bit of the word (short or long) or on all the bits of the word (case of memories having one-bit words in which long words are formed comprising r one-bit words, r> l, or in the case of memories using m-bit words, comprising either writes operating on all the bits of the word, or maskable writes operating on a single bit of the word). The errors taken into account are errors affecting a single bit of the word or of the long word. According to this embodiment, the error correction code associated with the word or the long word is a simple error correction code capable of distinguishing double errors from simple errors (for example, Hamming code increased by the parity bit of the word or long word and its code). When writing on all the bits of the word or long word, the new code of the word or long word is calculated in a standard way. When we write on a single bit, we check with the code two words or long words, one is formed by associating the bits read with the value 0 for the bit to write, the other is formed by associating the bits read with the value 1 for the bit to write. If one of these checks does not detect an error, then the bits read are correct and can be used to calculate the code. If errors are detected on the two words thus formed, then the word for which a simple error has been detected contains the correct value for the bit targeted by the writing. We use the code to correct the error in this word. The bits read obtained in the corrected word, the values to be written in the bit targeted by the writing and the old code are then used to calculate the new code.

According to a second variant of the second embodiment of the present invention, the writes can be done on all the bits of a word with m bits of a long word, or on a subset of these bits (masked writing) . The errors taken into account can affect a single word of a long word. We associate for each long word a code called "calculation code", capable of calculating the values of the bits of a word, using the values of the bits of the other words of the long word, as well as a code called "correction code" capable detect and correct an error in a word of the long word combined with the error introduced into another word of the long word (the word to be written) when this word is calculated using the calculation code and the other words of the long word which then include the wrong word.

According to an embodiment of this second variant, it is provided that the calculation code can detect its own errors. If errors are detected in this code, we will consider that there is no error in the words read from the long word (since it is assumed that an error cannot affect two words of the long word nor a word and code). This avoids introducing an error in the bits read by trying to correct them with an incorrect calculation code.

We consider the case where the errors taken into account are errors capable of affecting a single bit of a long word. The calculation code has m bits. The position bit i of this code is equal to the parity of the position bits i of all the words of the long word. In order to be able to detect errors in this code, a bit is associated with it which calculates its parity (it can be observed that the parity of the calculation code is also the parity of the long word). The nature of the correction code will be specified later. During a masked or unmasked writing of a word, all the unwritten bits of the long word associated with the written word are read at the same time, as well as the calculation code with its parity and the correction code. We check the calculation code using its parity. If we detect an error, we consider that there are no other errors in the long word (assumption of a simple error), we then use the value of the bits read and the bits written to calculate the new code calculation with its parity and the new correction code. If no errors are detected in the calculation code, the bits of the word targeted by the writing are calculated, using the calculation code and the words of the word long not targeted by writing. We then have a complete long word and we can use the correction code to detect errors in this long word and correct them. The long word will be wrong if there is an error (by simple assumption) on a read word. As the value of the bits of the word targeted by the writing is calculated by using inter alia the wrong read word, there will also be an error on the word targeted by the writing at the same position as the error on the wrong read word. A double error correction code can be used as the correction code. This code makes it possible to detect a double error and if necessary to correct it. We will then use the correct read bits and the written bits to calculate the new codes. However, a double error correction code is much more expensive than the Hamming code. To reduce the cost, we will use the Hamming code. It detects a double error, but is in principle unable to correct it. Nevertheless, it is observed that the double errors considered affect a position of a known word (the word targeted by the writing) and the same position of an unknown word. It is possible for each word targeted by the writing to calculate beforehand the syndromes of the Hamming code for all double errors having this property. There are am (rl) pairs of errors and corresponding syndromes for each word targeted by the writing. We can then create an array and store for each syndrome the corresponding double error. Then, when correcting a double error, we calculate its syndrome and we look in the table for the double error corresponding to this syndrome. The positions of the word indicated by this double error are then corrected to correct it. Nevertheless, some of these double errors can have the same syndrome, the Hamming code is then increased by adding additional bits making it possible to differentiate the syndromes for these double errors. Often a single additional bit will suffice, but more bits may be required in some cases. A more economical way is to develop a dedicated code capable of detecting and correcting single errors as well as double errors above. A computer program can be developed to automatically generate this type of code.

Optimization of the read-write synchronization of the second embodiment To make a write according to the second embodiment, the actions in the list below are carried out.

1) write the new values in the writing positions of the word (short or long) and read at the same time the other positions of this word (hereinafter "read positions"), 2) read the error correction code of the word (hereinafter "code"),

3) use the values of the read positions of the word and the word code, to correct the values of these positions,

4) if an error is detected and corrected, rewrite the corrected values if necessary (this action is not necessary, as the error could be detected and corrected the next time the incorrect word is read),

5) use the values (possibly corrected) of the read positions of the word and the values written in the writing positions to calculate the code,

6) write the code thus calculated.

It is observed that in order to write on part of the word, a reading operation and a writing operation of the word code are carried out. Since there is only one cycle for these two operations, we will use a separate memory for the codes and we will adopt one of the following three techniques.

Since the code memory is smaller than the data memory, it will be faster. In this case, provision may be made to perform a read operation followed by a code write operation for the duration of a single write cycle of the data memory. These two operations can be done in a single cycle of the code memory (read-write cycle), or in two cycles of this memory. If this first approach is not possible, we will use a two-access memory for the code, making it possible to carry out in the same cycle a read operation from the first access and a write operation from the second access .

A third solution can be applied in the case where the word is composed of several fields and each partial writing operation is always carried out on all of the bits of different fields concerned by this writing. We will then add an error detector code to each field (for example a parity bit), and we will check with this code the fields read during a partial write operation. The error correction code will be stored in another memory, the operation of which is offset from the memory of the data and error detection codes. Thus, the fields read will be verified by the error detecting codes, and the new error correcting code will be calculated before starting the operation cycle in the memory of the error correcting codes. If no error is detected in the fields read, then the error correction code thus calculated is written into the code memory. On the other hand, in the rare case where we detect an error in the read fields, we read the error correction code, we will use it to correct the error in the read fields, we recalculate the new error correction code , and we write this code in the memory of the error correcting codes. Thus, in the rare case of detection of errors, we will have to make two operations in the memory of the error correcting codes and certain calculations. These operations and calculations could occupy the memory of the error correcting codes for several cycles. We will then activate a signal to indicate to the system that this memory is not accessible for a certain number of cycles. The system will be able to react to this signal by entering, for example, the waiting cycle. Techniques described previously, within the framework of the first embodiment, could also be used within the framework of the second embodiment in order to avoid increasing the time of the cycle of the memory or the system, because of the various calculations of the code and error correction.

These techniques have been presented in the context of error correction in memories used by an electronic system as single-access memories, but those skilled in the art can easily adapt them for memories used by an electronic system as memories with several accesses (multi-ports) by applying them to each access of such a memory.

The second embodiment of the present invention has the advantage over the first of not adding cycle time in the event that no error is detected. Of course, if an error is detected, it will be necessary to carry out the error correction but this also occurs in the case of a memory with conventional error correction code.

Third embodiment of a writing In the case of memories with maskable operations, that is to say memories in which it is possible to write in arbitrary bits of a word, the first two embodiments solve the problem of calculation of a new error correction code after writing at the cost of more complex operations. According to a third embodiment of the present invention, each word is partitioned into several fields, the writings being able to be made on all the bits of one or more fields of the word and a field code is associated with each field. Field codes can be stored in the same memory as the data fields or in a separate memory.

The memory or memories are organized so that, each time one or more data fields are selected for writing, the corresponding field code or codes are selected. Thus, with each writing, the values of the bits of the data to be used are used. write in the selected fields to calculate the values of the corresponding field codes.

The invention is susceptible to various variants and modifications which will appear to those skilled in the art. In particular, the present invention has advantages even if k = 1 for improving masked writing operations in memories with error correction code.

Claims

1. Data storage method allowing error detections and corrections in a memory organized to read and write words of a first number (m) of bits and possibly to modify only part of such a word, comprising the following steps: associate an error detection and correction code with a group of a second number (k≥l) of words; and at each partial writing in the group of words: - calculate a new code of the modified group of words, - carry out a verification operation and, if an error appears, carry out an error correction of the modified word and / or of the new code .

2. Method according to claim 1, in which each word is a long word of M bits comprising a third determined number r≥l of elementary words with m bits.

3. Method according to claim 1 or 2, in which: an error detection code is associated with each word; each write operation in a word is preceded by a reading of this word and its error detection code; and in the event of an error, the word group and the error correction code are read in order to correct the errors and modify the error correction code.

4. Method according to claim 2, in which each operation of writing part of a word and of its code is preceded by a reading of the word and of its code, and the new code of the word is calculated from values to be written in the writing part of the word and values read from the other parts of the word, and is written in the memory.

5. Method according to claim 4, in which the codes are read and written in a memory distinct from the data memory, and the cycle of the code memory is offset in time with respect to the cycle of the word memory.

6. Method according to claim 4 or 5, comprising the following steps: writing the new code and at least the modified part of the word without waiting for an error detection or correction in the other parts of the word, using the word read and the code read to detect and correct any errors in the word read, and, in case of detection and correction of errors in the word read:

- recalculate the code from the values to be written in one part of the word and the read values corrected from the other parts of the word, and

- rewrite the recalculated code and possibly the read values corrected for the other parts of the word.

7. The method of claim 1, wherein the storage system performs a write operation or a data read operation at each cycle and is carried out by a memory with two accesses, the first of which makes it possible to carry out at least read operations and the second makes it possible to carry out at least write operations, each read operation being carried out by one of the accesses and each write operation being replaced by a read operation carried out by an access and by a write operation performed by the other access.

8. The method of claim 2, wherein during each writing operation in a part of a word, the other parts of the word are read simultaneously, and the new code is calculated using the values written in the writing parts of the word and the values read in the other parts of the word.

9. The method of claim 8, wherein one proceeds successively to: writing a part to replace a word, reading the other bits of the word, reading the word code, writing the code of the new word, verification of the word read, the system being interrupted and writing of the word being resumed if the verification of the word read indicates an error.

10. The method of claim 8, in which a writing is carried out in only at least one bit of a word, comprising the following steps: reading simultaneously with the writing the other bits of the word, calculating the error correction codes for these other bits and for all the possible values of the bit positions in which one writes, and determining which of the possible values for which one obtains a minimum error; and

- if this minimum error is zero, consider that the writing was successful and calculate a new error correction code; - if this minimum error is not zero, correct the bits in error at positions other than those where one has written and calculate a new error correction code.

11. Method according to claim 3, characterized in that it comprises the following steps: reading, at the same time as the word in which one writes, the code of the group of words, and calculating the new code of the group of words by modifying the code read according to the values of the bits written in the word and the values of these bits read before writing.

12. The method of claim 1, wherein errors are likely to occur in a single word of a group of words, and wherein an error detection code is associated with each word, characterized in that the code error correction is calculated in the form of an Exclusive OR of the error correction codes for each word.

13. The method of claim 8, in which a writing is carried out in only at least one bit of a word, and in which a word is calculated associated with the word capable of reconstituting the bits of the word in which one writes from the values of the other bits of the word and a correction code capable of correcting possible errors in the reconstituted word, these possible errors comprising the errors affecting said other bits as well as the errors induced by these errors in the reconstituted bits of the word.

14. Data storage method allowing detections and error corrections in a memory whose words are divided into several fields, the writing operations being able to be carried out on all the bits of one or more fields, comprising the following steps: associate an error correction code, said field code, with each field of a word, and when writing in one or more fields of a word, activate writing in the code or codes corresponding fields, the values to be written in each field code being calculated from the values of the bits to be written in the corresponding field.