JPH04356961A - Semiconductor substrate and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a substrate of an SOI structure in which an adhesive strength of the substrate to a thin silicon film is high to be uniformly adhered and a method for manufacturing the same in the structure of an SOI substrate having a low resistance buried layer having a reduced thickness of the degree to be easily insulator-separated and the method therefor. CONSTITUTION:A thin semiconductor film 2 provided oppositely to a substrate 1, a low resistance layer 4 provided partly on the surface of the film 2 and made of high melting point metal containing one type of titanium, tantalum, zirconium and tungsten or silicide of the metal, and a space forming part 3 formed to protrude from part of a region of the surface of the film 2, not provided with the layer 4, are provided. The film 2 is so adhered on the substrate 1 as to provide a gap 5 between the layer 4 and the substrate 1 and to be adhered through the part 3.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to SOI (Silicon on Insulator) having a low resistance buried layer.
) The present invention relates to a structure of a substrate and a method for manufacturing the same.

With the recent increase in speed and density of semiconductor integrated circuits, SOI structures that can achieve complete isolation between elements are being used as substrates for semiconductor devices. However, S.O.
To achieve high speed and high density using the I structure, a buried layer with low resistance is required.

[0003] Therefore, there is a need for a substrate with an SOI structure that is thin enough to realize complete isolation between elements and has a buried layer with low resistance.

0004

[Prior Art] In a semiconductor device using a substrate with an SOI structure, if the buried layer is made thicker in order to lower the resistance of the buried layer, isolation bands between elements must be formed deep.
There is a problem that isolation between elements becomes difficult.

FIG. 6 is a sectional view of a conventional embodiment, showing the manufacturing process of a semiconductor substrate. In order to solve the above problem, as a method of making a thin and low-resistance buried layer, a metal layer 9 deposited on one surface of a silicon wafer 6 is replaced with a silicide layer 9a, as shown in FIGS. After doing that,
Referring to FIG. 6(c), the silicon wafer 6 is bonded to the substrate 1 at high temperature via the silicide layer 9a, and then, referring to FIG. 5(d), the silicon wafer 6 is polished to form the semiconductor thin film 2. A method of manufacturing a structural substrate has been devised.

According to this method, since the resistivity of metal silicide is low, even a thin silicide layer 9a can be made into a buried layer with sufficiently low resistance. Therefore, isolation between elements can also be facilitated.

[0007] However, the substrate manufactured by this method is
When bonding at high temperatures, unevenness occurs on the surface of the metal silicide layer, which deteriorates the adhesive strength of the bonded surfaces.

Furthermore, referring to FIG. 6(d), voids 13a or peeling 13b occur on the bonded surface, and therefore, when polishing the silicon wafer 6 or manufacturing semiconductor circuits on the semiconductor substrate, Chips 11 and cracks 12 occur in the semiconductor thin film 2.

In order to avoid the above-mentioned drawbacks, a metal layer is provided on the bonding surface of a silicon wafer, and then the silicon wafer is pressure-bonded to another silicon wafer through this metal layer at a high temperature to form a silicide between the metal and the silicon wafer. A method of bonding using a reaction was devised.

[0010] However, the substrate manufactured by this method is
As the metal diffuses into the silicon, voids are created on the bonding surface, making it impossible to bond the entire surface of the wafer uniformly.

[0011]

[Problems to be Solved by the Invention] In the method of manufacturing a substrate with an SOI structure by bonding a silicon wafer onto a substrate as described above, it is necessary to provide a low-resistance buried layer by providing a metal or its silicide layer on the back side of a silicon thin film. When doing so, conventional methods have a problem in that it is not possible to achieve uniform bonding with sufficient bonding strength.

The present invention provides a substrate with an SOI structure that has a thin, low-resistance buried layer to facilitate insulation separation, and has a high and uniform bonding strength between the substrate and a silicon thin film, and a method for manufacturing the same. Our goal is to provide the following.

[0013]

[Means for Solving the Problems] FIG. 1 is a structural diagram of a first embodiment of the present invention, in which FIG. 1(a) is a partial plan view of a substrate having an SOI structure, and FIG. 1(b) is a partial plan view of a substrate having an SOI structure. 'Represents a cross-sectional view. FIG. 5 is a process diagram of a second embodiment of the present invention, which shows the manufacturing process of a substrate having an SOI structure in cross section.

In order to solve the above problems, a first configuration of the present invention includes a substrate 1 and a semiconductor thin film provided opposite to the substrate 1 on which a semiconductor element is to be formed, as shown in FIG. 2, and a low resistance made of a high melting point metal containing one of titanium, tantalum, zirconium, and tungsten, or a silicide of the high melting point metal, provided on a part of the surface of the semiconductor thin film 2 facing the substrate 1. The semiconductor thin film 2 has a layer 4 and a space forming portion 3 formed in a protruding manner in a region of the surface of the semiconductor thin film 2 facing the substrate 1 where the low resistance layer 4 is not provided. On board 1,
A gap 5 is provided between the low resistance layer 4 and the substrate 1, and the low resistance layer 4 and the substrate 1 are bonded via the spacer forming portion 3, and the second structure is as shown in FIG. In the semiconductor substrate of the first configuration, the low resistance layer 4 and the substrate 1
and a polysilicon 14 that is in close contact with the semiconductor thin film 2 and is embedded in the gap 5 formed between the semiconductor thin film 2 and the substrate 1 with a space 5a between the polysilicon 14 and the substrate 1. Referring to FIG. 5, the configuration is a method for manufacturing a semiconductor substrate of the second configuration, in which a part of the insulating film formed on the silicon wafer 6 is removed by etching using the resist 7 pattern as a mask. , forming the remaining insulating film as the spacer forming portion 3; and then, after depositing the high melting point metal on the silicon wafer 6, removing the high melting point metal on the resist 7 by a lift-off method. After forming the low resistance layer 4, and then depositing polysilicon 14 on the silicon wafer 6, the spacer 3 is removed by polishing using the spacer forming portion 3 as a stopper.
A step of removing the polysilicon 14 on the low resistance layer 4 and forming the polysilicon on the low resistance layer 4 into a concave shape; After gluing, heating and laminating,
The method is characterized by the step of polishing the silicon wafer 6 from the surface opposite to the surface of the silicon wafer 6 that faces the substrate 1 to form the semiconductor thin film 2 of a desired thickness.

[0015]

FIG. 2 is a structural diagram of an applied example of the present invention, showing a cross section of a semiconductor substrate having an SOI structure on which a bipolar transistor is formed.

In the present invention, referring to FIGS. 1 and 2, a low resistance layer 4 made of a high melting point metal or its silicide is formed as a buried layer. Since the material forming the low resistance layer 4 has high electrical conductivity, even the thin low resistance layer 4 functions as a low resistance buried layer. Therefore, since the buried layer can be made thinner, insulation isolation can be facilitated.

On the other hand, in the present invention, the semiconductor thin film 2 and the substrate 1
The bonding with the substrate 1 is performed through the space forming portion 3, and the buried layer is not in contact with the substrate 1 or used for bonding. Therefore, the adhesive strength does not decrease due to irregularities or voids on the surface of the metal or silicide.

Further, since the space forming portion 3 can be formed using a material and a process independent of the low resistance layer 4, it can be formed with a uniform thickness over the entire surface of the semiconductor thin film 2, and with a uniform thickness over the entire surface of the semiconductor thin film 2.
The material can be formed by selecting a material suitable for adhesion to the material.

Therefore, a bonding surface with high adhesive strength can be uniformly formed over the entire surface of the semiconductor thin film 2. In the second configuration, as shown in FIG. 5, the low-resistance layer is backed and reinforced by arch-shaped polysilicon 14, so when forming an SOI structure or manufacturing a semiconductor circuit, The chance of damaging the thin film 2 is reduced.

Referring to FIGS. 5(d) and 5(e), such a structure is constructed by depositing polysilicon 14 after forming the space forming portion 3 and the low resistance layer 4, and then polishing the polysilicon as usual. It is easily formed by the structure of the invention. That is,
Since the space forming part 3 acts as a polishing stopper, by continuing polishing even after the polysilicon on the space forming part is removed, the polysilicon 14 in the center surrounded by the space forming part 14 is polished. However, since polishing of the polysilicon 14 near the space forming portion 3 progresses slowly, as a result, the polysilicon 14 is naturally formed into an arch shape in the shape of a plano-concave lens.

[0021]

EXAMPLES The present invention will be explained based on examples. FIG. 3 is a first manufacturing process diagram of an embodiment of the present invention, in which the SOI shown in FIG.
The manufacturing process of the structure is shown in cross section.

Referring to FIG. 3(a), an oxide film with a thickness of 1 μm is formed on one surface of a silicon wafer 6 with a thickness of 500 μm, a resist 7 is applied thereon, and then the oxide film is photo-etched. , is the space forming part of the required pattern.

Furthermore, an ion-implanted layer 8 is formed by ion-implanting an impurity element. Note that the ion implantation layer is for reducing the contact resistance with the metal thin film 9, and is not an essential element of the present invention.

Next, referring to FIG. 3(b), a thickness of 50
After depositing a 0 nm high melting point metal thin film 9, as shown in Fig. 3(c).
Referring to , the metal thin film 9 on the resist 7 is removed by lift-off.

Next, a silicon wafer 6 is heat bonded onto the silicon substrate 1 via the space forming portion 3. Next, referring to FIG. 3(e), the silicon wafer 6 is ground and polished to form a semiconductor thin film 2 having a thickness of, for example, 500 nm, thereby forming the SOI structure shown in FIG. 1.

Note that after the metal thin film 9 is vapor-deposited, it may be heat-treated to form silicide. The SOI structure semiconductor substrate manufactured by the above process can be applied to, for example, forming a bipolar transistor, as shown in FIG.

The transistor includes a collector lead-out region 22 from the low resistance layer 10, a base 24 made of an epitaxial layer, an emitter 23 made of doped polysilicon, an insulating separation band 21, a space forming part, and a gap 5. electrically isolated from the substrate 1 and other transistors.

The low resistance layer used to form such a transistor has a size of, for example, 5×10 μm. Insulating separation strip 21
can be formed by, for example, oxygen ion implantation. In the present invention, since the low-resistance layer 4 is made of metal or silicide with high electrical conductivity, the low-resistance layer 4 that acts as a buried layer can be made thin, and therefore the insulating separation band 4 can be easily formed.
1 can be formed.

Therefore, transistors with small collector capacitance and small collector resistance can be integrated and manufactured in a small area. FIG. 4 is a second manufacturing process diagram of the embodiment of the present invention, which shows another manufacturing process of the SOI structure shown in FIG. 1 in cross section.

Referring to FIG. 4A, one surface of the silicon wafer 6 is photo-etched using a pattern of a resist 7 provided on one surface of the silicon wafer 6 to create a space forming portion 3 made of silicon.

Next, referring to FIG. 4(b), a high melting point metal thin film 9 is deposited and then lifted off, and referring to FIG. 4(c), a metal thin film 9 is formed at a position where it is to become a buried layer. do.

Next, referring to FIG. 4(d), a silicon wafer 1b having an oxide film 1a on the surface is used as a substrate, and a silicon wafer 6 is placed on this substrate with the space forming part and the oxide film 1a in contact with each other and heat bonded. do.

Next, the silicon wafer 6 is polished to form the semiconductor thin film 2. According to this process, the oxide film forming step can be omitted, and since the semiconductor thin film 3 serving as the active layer and the oxide film of the space forming part 3 do not form an interface, the quality of the semiconductor thin film 2 can be prevented from deteriorating due to the interface. It can be prevented.

Next, an example of a semiconductor substrate according to the second configuration of the present invention will be described. With reference to FIGS. 5(a) to (c),
Space forming portion 3, ion implantation layer 8, and metal thin film 9 are formed in the same manner as in the above-described steps.

Next, referring to FIG. 5(d), polysilicon 14 is deposited. Next, referring to FIG. 5(e),
The silicon wafer 6 is polished using a urethane pad and a polishing agent containing colloidal silica until the protruding surface of the space forming part 3 is exposed, and then further polished for, for example, 10 minutes to process the polysilicon into a plano-concave lens shape.

Next, referring to FIG. 5(f), a silicon wafer 6 is heat-bonded onto the substrate 1 via the space forming part 3. FIG. 5(f-2) is an enlarged sectional view of section A in FIG. 5(f), and shows the bonded portion between the substrate 1 and the silicon wafer 6. The polysilicon 14 is formed in close contact with the metal thin film 9 with a space 5a between it and the substrate 1, and has an arch shape that becomes thicker near the space forming portion 3.

Next, referring to FIG. 5(g), the silicon wafer 6 is polished to form a semiconductor thin film. In addition, in the embodiment of the present invention, bonding can be performed under reduced pressure in order to prevent air in the gap 5 or space 5a from expanding and destroying the thin film during heat bonding. Furthermore, it is natural that a certain amount of gas can be enclosed to compensate for the pressure applied during polishing.

[0038]

[Effects of the Invention] According to the present invention, a semiconductor thin film having a thin buried layer with low resistance can be formed uniformly and with high adhesive strength on a substrate. A semiconductor substrate with a suitable SOI structure can be easily manufactured, which greatly contributes to improving the performance of semiconductor devices.

[Brief explanation of drawings]

[Figure 1] Structural diagram of the first embodiment of the present invention

[Figure 2] Structural diagram of an application example of the present invention

[Figure 3] Embodiment 1 manufacturing process diagram of the present invention

[Figure 4]
Example 2 manufacturing process diagram of the present invention

[Figure 5] Process diagram of the second embodiment of the present invention

[Figure 6] Cross-sectional view of a conventional embodiment

[Explanation of symbols]

1a Oxide film 1b, 6 Silicon wafer 1 Board 2 Semiconductor thin film 3 Space forming part 4 Low resistance layer 5 Gap 5a Space 7 Resist 8 Ion implantation layer 9 Metal thin film 9a Silicide 11 Chips 12 Crack 13a Void 13b Peeling 14 Polysilicon 21 Insulation separation band 22 Collector drawer area 23 Emitter 24 Base

Claims (3)

[Claims] Claim 1: A substrate (1) and a semiconductor thin film (on which a semiconductor element is to be formed) provided opposite to the substrate (1).
2) and a high melting point metal containing one of titanium, tantalum, zirconium and tungsten, or a high melting point metal provided on a part of the surface of the semiconductor thin film (2) facing the substrate (1). A low resistance layer (4) made of silicide and a space formed protruding in a region of the surface of the semiconductor thin film (2) facing the substrate (1) where the low resistance layer (4) is not provided. Part (3),
The semiconductor thin film (2) is placed on the substrate (1) with the low resistance layer (
4) A semiconductor substrate characterized in that a gap (5) is provided between the substrate (1) and the substrate (1), and the semiconductor substrate is bonded via the spacer forming portion (3). 2. In the semiconductor substrate according to claim 1, the semiconductor thin film (2) is in close contact with the gap (5) formed between the low resistance layer (4) and the substrate (1). A semiconductor substrate characterized by having polysilicon (14) embedded with a space (5a) between the substrate (1) and the substrate (1). 3. The method of manufacturing a semiconductor substrate according to claim 2, wherein a part of the insulating film formed on the silicon wafer (6) is removed by etching using the resist (7) pattern as a mask, and the remaining part of the insulating film is removed. After depositing the high melting point metal on the silicon wafer (6), the high melting point metal on the resist (7) is removed by a lift-off method. Next, after depositing polysilicon (14) on the silicon wafer (6), polishing is performed using the spacer forming portion (3) as a stopper. the polysilicon (14) on the spacer (3)
and forming the polysilicon on the low resistance layer (4) into a concave shape. 1) After adhering to the surface and heating and bonding, polish the silicon wafer (6) from the side opposite to the side of the silicon wafer (6) that faces the substrate (1),
A method for manufacturing a semiconductor substrate, comprising the step of forming a semiconductor thin film (2) with a desired thickness.