JPH04352282A - Method for dividing logic circuit - Google Patents

Abstract

PURPOSE:To improve the throughput of an automatic design system by decreasing the total quantity of circuits processed by dividing a large-scale logic circuit. CONSTITUTION:A 1st dividing means 11 temporarily deletes a circuit whose output is distributed to plural circuits and a 2nd dividing means 12 temporarily deletes a circuit at a control point part in the circuit. Then a circuit dividing means 13 generates a divisional circuit from an observation point in the circuit and a circuit merging means 14 merges plural divisional circuits when an input circuit is included in another divisional circuit. A circuit adding means 15 adds the circuits deleted by the 1st dividing means 11 and 2nd dividing means 12 to divide the logic circuit.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for dividing a logic circuit to facilitate testing of large-scale logic circuits.

0002

[Background Art] Conventionally, when applying the circuit partitioning method, which is one of the testability methods, to a circuit with a large logic function, the number of gates on the input side of a certain observation point is checked, and the number of gates is determined by the automatic design system. (hereinafter referred to as DA system), logic circuits were divided with emphasis on the number of gates, such as adding an input-side gate for the next observation point as long as it could be processed by the DA system.

0003

[Problem to be Solved by the Invention] In the conventional logic circuit division method described above, the number of gates in the circuit is small;
Since the characteristics of individual circuits, such as parts distributed to many parts within the circuit, are not considered, the overlap between divided circuits becomes large and the total amount of circuits handled by the DA system increases. The drawback was that it was less efficient.

0004

[Means for Solving the Problems] The present invention provides a first dividing means for temporarily deleting a circuit whose output is distributed to a plurality of circuits, and a first dividing means for temporarily deleting a circuit at a control point within the circuit. a second dividing means; a circuit dividing means for creating divided circuits from observation points in the circuit; a circuit merging means for merging these divided circuits when the input circuit is included in another divided circuit; and circuit adding means for adding the circuits deleted by the first and second dividing means.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a flowchart showing a process for implementing an embodiment of the present invention. In FIG. 1, the first deletion means 11 is a means for temporarily deleting a circuit whose output is distributed to a plurality of circuits, for example, by a clock distribution circuit, a test mode control circuit, an initialization circuit in the circuit, etc. This is processing to prevent division processing from becoming impossible. 2nd deletion 12
is a means of temporarily deleting circuits that overlap control points in a circuit. For example, in the output side circuit of a circuit control point such as an input terminal or register, a circuit with both the number of inputs and the number of outputs is 1. This process increases the number of control points in the apparent circuit by temporarily deleting them. The circuit dividing means 13 is a means for tracing in the input direction from an observation point in the circuit to identify an input circuit, and is, for example, a process for identifying input circuits such as output terminals and registers at each observation point. At this time, if the input circuit is an input circuit of another observation point, tracing is not performed. The circuit merging means 14 is a means for merging the input circuits of a certain observation point created by the circuit division means 13 when they are input circuits of another observation point. The circuit addition means 15 is a means for adding at least the circuits deleted by the first deletion means 11 and the second deletion means 12 by tracing in the input direction from the circuit cut portion.

Next, specific embodiments of the present invention will be explained.

FIG. 2 shows an embodiment of the first deletion means 11 shown in FIG. The circuit control point 21 is, for example, a clock terminal, a test mode control terminal, etc., and although the amount of circuitry is small, it is a control point of a circuit whose output is distributed to many circuits. Trace is performed from the circuit control point 21 to the output side, and circuits with one or less inputs are deleted. In this case, the circuit control point 21 and the logic circuit 22 are deleted. As a result, the logic circuit 23 and the logic circuit 24 having a plurality of inputs can be treated as pseudo control points of the logic circuit group 25 and the logic circuit group 26, respectively.

FIG. 3 shows an embodiment of the second deletion means 12 shown in FIG. The circuit control point 31 is, for example, a general input terminal and a register. Trace is performed from the circuit control point 31 to the output side, and logic circuits in which either the number of inputs or the number of outputs exceeds 1 are deleted. In this case, the circuit control point 31 and the logic circuit 32 are deleted. As a result, the logic circuit 33 and the logic circuit 34 can be treated as pseudo control points of the logic circuit group 35 and the logic circuit 36, respectively.

FIG. 4 shows an embodiment of the circuit merging means 14 of FIG. Since the input circuits of the circuit observation point 45 are the logic circuit 41, the logic circuit 42, and the logic circuit 42 are also the input circuits of the circuit observation point 46, the circuit observation point 46 and its input circuit, the logic circuit 44, The logic circuit group is the same as the logic circuits 41, 42, and 43 which are input circuits.

FIG. 5 shows an embodiment of the circuit addition means 15 shown in FIG. Tracing is performed in the input direction from the pseudo control point 54 created by the first deletion means 11 and the second deletion means 12, and logic circuits 52 and 53, which are input circuits, and the circuit control point 51 are added.

0012

As explained above, in the present invention, only the portions distributed within the circuit are overlapped between the divided circuits, so the total amount of circuits handled by the DA system is reduced compared to the conventional dividing method, and the divided circuits are This has the effect of improving the processing efficiency of the DA system.

[Brief explanation of drawings]

FIG. 1 is a flowchart for implementing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of division by the first dividing means 11 of FIG. 1;

3 is a diagram showing an example of division by the second division means 12 of FIG. 1. FIG.

FIG. 4 is a diagram showing an example of merging by circuit merging means 14 of FIG. 1;

FIG. 5 is a diagram showing an example of addition by circuit addition means 15 in FIG. 1;

[Explanation of symbols]

11 First dividing means 12 Second dividing means 13 Circuit dividing means 14 Circuit merging means 15. Circuit addition means 21 Circuit control point 22-24 Logic circuit 25, 26 Logic circuit group 31 Circuit control point 32-34 Logic circuit 35, 36 Logic circuit group 41-44 Logic circuit 45, 46 Circuit observation point 51 Circuit control point 52, 53 Logic circuit 54 Pseudo control point

Claims (1)

[Claims] 1. A first dividing means for temporarily deleting a circuit whose output is distributed to a plurality of circuits; a second dividing means for temporarily deleting a circuit at a control point within the circuit; circuit dividing means for creating divided circuits from observation points in the circuit;
When the input circuit is included in another divided circuit, it is characterized by comprising a circuit merging means for merging these divided circuits, and a circuit adding means for adding the circuit deleted by the first and second dividing means. How to divide a logic circuit.