JPH0822486A - Logic circuit simulation method - Google Patents

Abstract

PURPOSE:To accelerate a logic simulation processing without influencing the connection form of a logic circuit by changing an input signal value for respective assemblies, using a net expression table and a logic element expression table newly generated for the respective assemblies and propagating the signal value. CONSTITUTION:The connection relation of respective logic elements and a flip-flop or the input terminal of an object logic circuit and connection states among the respective logic elements are prepared (101,) the connection states are classified by adding the division section numbers of flip-flop logic elements based on the parameters of the control signal lines of clocks or the like (102) and the respective logic elements of the object logic circuit are divided into the assemblies of a control signal unit (103.) A logic element stage number until the output terminal of an object assembly is traced and a connection stage number until an output terminal point is set (104.) The ones for which the division section of the control signal unit and an element function are the same and an input number is the same further are gathered and the new table is prepared.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation used for logic verification of a processing circuit, and more particularly to an optimum logic integration method in a logic circuit to be logic verified.

[0002]

2. Description of the Related Art In the logic design of digital logic circuits,
As a means for verifying whether or not the logic function of the design target logic circuit is correct without creating it as hardware, operation confirmation using logic simulation is performed. As these logic simulation methods, as disclosed in Japanese Patent Laid-Open No. 63-211036 and Japanese Patent Laid-Open No. 3-42736, a logic circuit to be designed is edited with a logic element having a structure suitable for a logic circuit simulation, and a computer is used. There are methods to reduce the time and the amount of memory used.
Further, as a method for realizing parallel logic simulation by dividing the processing according to the gate type of the circuit, Japanese Patent Laid-Open No. 3-91
The technique disclosed in Japanese Unexamined Patent Publication No. 5-46694 is proposed as a logic circuit simulation method for handling logical elements having the same function as one aggregate. The method of reducing the number of signal change events, which is a means for propagating a signal change between the respective logic elements by combining the output terminals of one aggregate into one, is used for the logic elements other than the flip-flop. , They are not considered as an aggregate of these.

[0003]

In the conventional method, it is possible to delete and optimize each logic element of the target logic circuit. However, the signal change event of the logic element which is deeply related to the processing speed of the logic simulation. Insufficient consideration is given to the amount. That is, it is a method of reducing logic elements without signal change, dividing logic elements having the same function as a series of processing target groups, and executing logic simulation processing for each logic element unit. There is no change in the number of logic elements to be operated, and the event of signal change does not change. Therefore, the event processing time of the logic simulation processing cannot be reduced. An object of the present invention is to reduce the number of events of signal change of a logic element without affecting the connection form of a logic circuit, and to speed up the logic simulation processing.

[0004]

In order to achieve the above object, the present invention reads a logic element and its connection information in a logic circuit into a computer and verifies the logical operation of the logic circuit on the computer. In the simulation method, the information of the logic elements and their connections in the logic circuit is read into the computer, the net expression table and the logic element expression table are created, and the logic circuit connections are made based on the parameters of the specified control signal line in the logic circuit. The state is traced through the net expression table and the logic element expression table, and each logic element of the logic circuit is divided into an assembly of control signal line units, and the net expression table and the logic element are grouped by control signal line units. Trace the expression table to find the number of connection stages in the logic circuit of each logic element, and identify the same in the same set. A logical element expression table of the number of logic elements in the succeeding stage is extracted, the logical elements having the same number of connection steps are collected as a multi-input element, and a logical element expression table of the multi-input element is newly generated and associated with the logical element expression table. A new net representation table is generated, the input signal value is changed for each aggregate, and signal value propagation is performed using the newly generated net representation table and logical element representation table for each aggregate. I have to.

Further, when each logic element of the logic circuit is divided into a group of control signal line units, a logic element of a flip-flop is connected from the control signal line based on a parameter of a designated control signal line in the logic circuit. Trace the connection state up to the expression table, classify each control signal line by assigning a division section number to the flip-flop logic element expression table, and then connect from the flip-flop logic element expression table with the same division section number. The above net expression table and logic element expression table are sequentially traced, and the logic element expression table of the flip-flops with different division division numbers or the input / output terminals of the logic circuit are used as end points and traced to the logic element expression table existing up to the end points. Assign the same division classification number as the logical element expression table of the start flip-flop, and Are each logic element of the logic element representation table split partition number is granted to a collection of the control signal line basis.

Further, when obtaining the number of connection stages in the logic circuit of each of the logic elements, the delay time from the input terminal or the input side flip-flop in the aggregate unit to each logic element is obtained, and the logic elements having the same delay time are obtained. To have the same number of connection stages.

[0007]

In general, the signal value of each logic element used in the logic simulation is expressed by signal value levels of maximum 32 values, generally 4 values or 8 values. To handle these signal values on a computer, 2 bits or 3
Although it can be represented by a bit memory area, conventionally one logic element has been executed by one logic operation. According to the present invention, the signal change of each logic element can be aggregated into one by a multi-input functional element, and in a logic simulator that handles a four-valued signal level, on a computer that processes data of one word and four bytes. As the logical operation of the 2-input AND element, 16 logical elements can be handled by one logical operation. Therefore, it is possible to reduce the amount of events that propagate the signal change between the respective logic elements, and at the same time, it is possible to speed up the logical operation processing of the logic elements associated with the signal change of the respective logic elements.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a logic compilation flow for producing the multi-input functional device of the present invention. FIG. 2 shows a net expression table configuration showing a signal name connection state between the respective logic elements. The table includes a signal name table and a net table. FIG. 3 shows a logical element expression table configuration expressing the logical elements. The table includes an element table, a signal value table, and an output value table. As a connection-related example of these tables, FIG. 8 shows a connection state of the target logic circuit expressed by a net expression table and a logic element expression table.

In the net representation table of FIG. 2, 20
1 is a signal name table, and each record has a signal name 2
03, the connection source address 204, that is, the address of the element table of the connection source element, and the connection destination address 205,
That is, the record address of the connection destination net table is described. Reference numeral 202 denotes a net table. In each record of the table, a link 206, that is, a record address of the net table to be linked (“0” indicates no link), a terminal position 207, that is, a pin number of the element table, and an address. 208, that is, the address of the element table of the element of the connection destination is described. In the logical element representation table of FIG. 3, 310 is an element table and 320
Is a signal value table, and 330 is an output value table. Here, the logic element representation table has a plurality of values obtained by collecting signal values and output values in separate tables and separating the element table from the signal value table and the output value table. Although it is designed to handle the signal value and output value of the logic element, the signal value,
The output value may be included in the element table 310 instead of being a single table. It should be noted that each item of these tables will be sequentially clarified in the following description.

First, a method of modeling a logic circuit will be described in detail with reference to the table connection relation of FIG. FIG.
FIG. 8 (2) shows an example of the target logic circuit. An example of setting this logic circuit in a signal name table showing a net connection state, a net table and an element table showing the function of each logic element is shown in FIG. 8 (2). Shown in. In this example, for example, the signal line F of FIG. 8 (1) sets the signal name in the sixth record of the signal name table 801, and indicates f of the element table 803 as the connection source address, and the connection destination address. Sets the record number 6 indicating the corresponding connection destination of the net table 802. The element table is shown here in a simplified form. Further, in the net table 802, when the same signal line has a plurality of connection destinations, a record having the address of the element table of each connection destination is sequentially generated as link information. In this example, the signal line F
Are connected from the element table f as the connection source, and are connected to the pin number 2 of the element table g shown in the record 6 of the net table 802 and the pin number 1 of the element table h shown in the record 7 as the connection destination. Indicates that.
Further, the element table g has a signal line name G as an output signal line.
Of the signal name table 801 having "c" (record address)
Connected to Further, the signal value of each logic element is provided for each input terminal / output terminal in a portion which can be directly referred to from the corresponding element table 803, and the method of easily calculating the logic element and its result can be set. In this example, v1 and v2 prepared in the element table 803 represent the input signal value areas of the input terminal pin number 1 and the input terminal pin number 2, respectively,
ov represents the output signal value region.

A method of creating the logical element expression table and the net expression table will be described with reference to the logic compilation flow of FIG. 1, the net expression table configuration of FIG. 2, the logical element expression table configuration of FIG. 3, and the logic circuit example of FIG. Will be explained. As a means for dividing a logic circuit corresponding to a signal change occurrence factor of the target logic circuit, in the logic compilation flow of FIG. 1, first, in step 101, each logic element existing in the simulation target logic circuit is read and each logic element is read. And a flip-flop or an input / output terminal of a target logic circuit, and a connection state between respective logic elements in a signal name table 201, a net table 202, an element table 310, a signal value table 320, and an output value table 330. create. In step 102, the connection state from the corresponding signal line to the portion where the element function 311 of the element table 310 indicates a flip-flop based on the parameters of the control signal line such as a clock specified in advance by the input card or the storage medium. That is, from the input terminal CK0 shown in the logic circuit example of FIG.
12, 613 and the connection state from the input terminal CK1 to the flip-flops 661, 662, 663 are traced using the signal name table 201, the net table 202, the element table 310, and the output value table 330, and each control is performed. A number is added to the divided section 318 of the flip-flop logic element for each signal for classification. In the example of the logic circuit of FIG. 6, as the division division of each flip-flop, a flip-flop 611 connected from the input terminal CK0,
Number 1 is set for 612 and 613, and input terminal C
Flip-flops 661, 662 connected from K1
The number 2 is set for 663. Next step 1
In 03, the flip-flop logic elements having the same division section 318 are extracted, the connection destinations of the logic elements are sequentially traced using the net expression table and the logic element expression table, and the flip-flop logic elements having different division section numbers,
Alternatively, with the input / output terminal of the target logic circuit as the end point of each logic element group, the same numerical value as the division section 318 of the flip-flop element of the trace start is added to the division section 318 of the element expression table of the logic elements enclosed between them. ,
By setting each control signal line as a number unit of the same division section, each logic element of the target logic circuit is divided into a group of control signal line units.

In step 104, the divided aggregate unit, that is, the division value 318 of the output value address 317 of the element table 310 corresponding to each of the same logic elements is used to output the flip-flops or the target logic circuits of the output terminals of the target aggregate. The number of logic element stages up to the output terminal is calculated by the element table 310.
The signal name table 201 and the net table 202 are traced from the target device table 310 to obtain the device table 31.
The number of passages of 0 is calculated, and the number of passages indicating the number of connection stages up to the output end point of the element is set in the number of connection stages 313 of each element table 310.

Further, in step 105, the division division 318 is performed.
Of the same target aggregate having the same number of connected stages up to the output end point, the element function 311 of the element table 310 and the logic element having the same number of inputs 314 indicating the number of input terminals are extracted from the element table. In the logic simulation to be used, logic elements having the same delay time are used as extraction conditions, and the logic elements satisfying the same condition are collected as a multi-input element to create a new element table 310. As the connection state of the corresponding elements, the total number of logical elements is set to the number of elements 315, and the signal value table 320 of the input terminal of each element is represented by the signal value n1 and the signal value n2 according to the order of compilation n of each element. The output values n of the output values 331 of the respective elements are also arranged and the signal name table 20 is arranged.
The address 332 of 1 is arranged as indicated by the address n, and the terminal position 207 of the net table 202 is also classified into the element collection order n and the input terminal number of each element, and the element table address 208 is newly created. The address is updated to indicate the element table 310 of the multi-input element. Here, a new element table for the multi-input logic element is created, and the element table 310, the signal value table 320, and the output value table 330 that are no longer needed are created.
Is used as a new registration area for the logic element. On the other hand, regarding the flip-flops for extracting the target aggregate, the ones in which the division section 318 divided into control signal units in step 102 and the element function 311 are the same and the number of inputs 314 is the same are summarized. A new element table 310, a signal value table 320, and an output value table 330 are created as input logic elements.

Through the above processing steps, the logic circuit example of FIG. 6 is expressed as a processing result logic model shown in FIG. In this way, a single logic element can be generated as a multi-input logic element, and the number of logic elements to be simulated by the logic simulator can be reduced.

Regarding the logic simulation procedure using these logic compilation results, first, as a method of propagating a signal change in the logic simulation, only the logic element in which the signal value of the signal line connected to the input terminal of each logic element has changed A signal propagation procedure in the event driven method, which is characterized in that the output signal value of the target logic element is calculated, will be described in detail with reference to the table connection in FIG. 8 and the event processing method in FIG. When the signal propagation delay time of the logic element e in FIG. 8 (1) is 2 and the signal propagation delay time of the logic element f is 1, a High signal is input to each of the input terminals A, B, C, and D at time t. When a value is given, as shown in FIG. 9 (1), a signal change event for calculating output values of the logic element e and the logic element f is registered in the event table as an event at time t on the time wheel. It

Next, when the simulation time reaches t, the first event registered in the entry of the event table corresponding to the time t is taken out, the output value of the logic element e indicated by the event is calculated, and the calculated value is calculated. In order to propagate the output value, the element e of the table 803 of FIG.
From the connection destination address of the signal via the signal name table of the table 801 to search the address of the logic element table of the signal connection destination registered on the net table of the table 802, and propagate the corresponding address g from the current time to the signal value of the element. The event is registered in the event table as an event at time t + 2 indicating the delay time 2. Further, the event of the logic element f registered in the entry linked to the entry of the event table corresponding to the time t is extracted, the output value of the logic element f indicated by the event is calculated, and the propagation destination of the output signal value is calculated. The events of the logic elements g and h are registered in the entry of the event table corresponding to the current time t + 1 on the time wheel. After all the events registered in the entry of the event table corresponding to the time t are processed, the time is advanced, the event processing at the next time is similarly performed, and the signal change generated on the logic circuit is sequentially propagated to the logic of the subsequent stage. By doing so, the logic circuit simulation is executed.

Next, the logic simulation execution procedure in the present invention will be described in detail. In the logic simulation execution flow of FIG. 4, first, the signal name table 201, the net table 202, the element table 310, the signal value table 320, and the output value table 330 of the logic expression table generated by the logic compilation in step 401.
Is created in the memory, the initial value of each logic element signal value is set as an indefinite value, an event table for propagating a change in the signal value is created, and the simulation time is set to zero. In step 402, input data such as input signal values prepared in advance in the DISC or the like is read, and the net indicated by the connection destination address 205 of the signal name table 201 for the corresponding signal line to which the input signal value corresponding to the corresponding simulation time should be given. The setting position of the signal value table is obtained from the element table 310 and the terminal position 207 from the address 208 of the table 202, and the signal value is set to the input signal value 321 indicated by the terminal position 207 of the signal value table 320 to which the input value address of the element table is connected. While propagating, when the flag 312 of the element table 310 of the corresponding signal value propagation destination is OFF, the signal change event for the corresponding logic element is registered in the event table 502. The flag 312 of the element table 310 indicates that an event has already been registered for the corresponding logic element. That is, when the flag 312 of the element table 310 is ON, the event registration to the corresponding logic element is not performed. By applying this method, duplicate event registration to the same logic element is suppressed, and the number of processing events is reduced.

In step 403, the time wheel 50 is
The element table 310 indicated by the element address 503 registered in the event table 502 at time 1 is read, the flag 312 of the corresponding logic element is turned off, and all output signal values for all input signal values of the aggregate are set. In step 404, the output signal value 331 of each logic element of the aggregate is compared with the output signal value of the calculation result,
When the output value changes, the output signal value 331 of the corresponding logic element whose output value has changed in step 405 is updated, and the trace from the signal name table 201 indicated by the address 332 of the signal line connection destination to the element table 310. Carried out,
The signal value of the calculation result is propagated to the signal value 321 of the propagation destination. If the flag 312 of the element table 310 to which the signal line is connected is off in step 406, step 40
In step 7, the flag 312 is turned on, and the element address of the signal connection destination is set to the event 502 for the corresponding time of the time wheel 501 indicated by the time obtained by adding the delay time of each logic element to the new signal change event. to register. As shown in step 408, the processing from step 403 to step 407 is repeated until there is no signal change event on the simulation elapsed time. If there are no events within the relevant time, the simulation elapsed time is advanced at step 409, and the simulation ends. Until time, the processing from step 402 to step 409 is repeated. The generated new signal change event is registered with respect to the corresponding time of the time wheel 501 indicated by the time added with the delay time of each logic element.

As described above, the signal change event of the logic element is generated for each aggregate of the logic elements, and the logical operation of each aggregate is collectively executed, and the signal change event to the same logic element is performed. By not overlapping, it is possible to reduce the number of computer processes for signal changes. As an application of this method, the multi-input logic element creation method at the time of logic compilation in logic circuit simulation considering delay time is
For the group divided in step 103 of FIG. 1, the delay time from the output terminal of the flip-flop is used as a further division section in step 104. In step 105, the same functional element and the same input terminal are used for each division section. The logical circuit simulation according to this procedure can be realized by collecting the logical elements having a number as one element expression table. Moreover, since the simulation can be executed for each aggregate, the aggregate can be distributed to a plurality of processors and processed in parallel using a parallel computer, a vector computer, or the like.

[0020]

According to the present invention, it is possible to reduce the signal change event of the logic circuit and the computer time required for the logic simulation by using the logic elements having the same function in the logic circuit simulation as one set. You can Further, by using a parallel computer, a vector computer, or the like, it is possible to distribute the aggregate of each logic element to a plurality of processors and execute the logic operation in parallel.

[Brief description of drawings]

FIG. 1 is a diagram showing a logic compilation flow for generating a multi-input functional element.

FIG. 2 is a diagram showing a configuration of a net representation table.

FIG. 3 is a diagram showing a configuration of a logical element expression table.

FIG. 4 is a diagram showing a logic simulation execution flow.

FIG. 5 is a diagram showing a structure of an event table.

FIG. 6 is a diagram showing an example of a logic circuit.

FIG. 7 is a diagram showing a logical model of a logical compilation processing result.

FIG. 8 is a diagram showing an example of a table connection relation between a net expression table and a logic element expression table.

FIG. 9 is a diagram for explaining an event processing method.

Claims (3)

[Claims] 1. A method for simulating a logic element in a logic circuit and its connection in a computer and verifying the logic operation of the logic circuit on a computer, comprising: Read it to a computer, create a net expression table and a logic element expression table, and trace the connection status of the logic circuit based on the specified control signal line parameters in the logic circuit by tracing the net expression table and the logic element expression table. Each logic element of the logic circuit is divided into a group of control signal line units, and the net expression table and the logic element expression table are traced for each group of control signal line units, and the number of connection stages in the logic circuit of each logic element is traced. And extract the logic element representation table of the logic elements with the same number of connection stages in the same set. , Grouping the logic elements of the same number of connection stages as a multi-input element, newly generating a logic element expression table of the multi-input element, and generating a new net expression table related to the logic element expression table. A method for simulating a logic circuit, characterized in that an input signal value is changed for each body and the signal value is propagated using the newly generated net expression table and logic element expression table for each aggregate. 2. The logic circuit simulation method according to claim 1, wherein when each logic element of the logic circuit is divided into a group of control signal line units, a parameter of a designated control signal line in the logic circuit is used. , The connection state from the control signal line to the logic element expression table of the flip-flop is traced, the division element number is assigned to the logic element expression table of the flip-flop for each control signal line, and then the division division number is The net expression table and the logical element expression table of the connection destination are sequentially traced from the logical element expression table of the same flip-flop, and the logical element expression table of the flip-flops having different division division numbers or the input / output terminals of the logical circuit are used as end points. The theory of the flip-flop of the trace start in the logic element expression table existing up to the end point Logic simulation method characterized by imparting the same division classification number as elements expression table, a collection of identical division division control signal line units each logic element of the logic element representation tables that are numbered. 3. The logic circuit simulation method according to claim 1, wherein when determining the number of connection stages in the logic circuit of each of the logic elements, a delay from an input terminal or an input-side flip-flop in each unit of the aggregate to each logic element. A method for simulating a logic circuit, characterized in that the time is obtained and the logic elements having the same delay time have the same number of connection stages.