JPH05314212A - Circuit information correction system - Google Patents

Abstract

PURPOSE:To considerably improve the delay time of critical signal paths exceeding specified delay time. CONSTITUTION:All the function blocks 22-24 constituting the critical signal path between function blocks 20 and 21 are gathered at one place, and a new single function block 30 is prepared with the same function as these function blocks 22-24. The critical signal path is corrected by replacing the function blocks 22-24 with this single function block 30. Therefore, there is no wiring among the function blocks 22-24, and the delay time among the function blocks is practically turned to zero.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a circuit information correction system, and more particularly to a circuit information correction system for improving the delay time of a signal path of a circuit.

[0002]

2. Description of the Related Art If there is a so-called critical signal path that exceeds a prescribed signal delay time among circuit connection information, the wiring length between the functional blocks forming this critical signal path is made shorter, or this critical signal path is made shorter. The functional blocks forming the path are changed to a functional block that operates at a higher speed, the delay time of the critical signal path is improved, and the standard is satisfied.

In such a method of improving the delay time of the critical signal path, it is impossible to reduce the wiring delay time between the functional blocks forming the signal path to zero, so that the delay time cannot be significantly improved. There are drawbacks.

[0004]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art. The object of the present invention is to modify the circuit information capable of greatly improving the delay time of the critical signal path. It is to provide a system.

[0005]

The circuit information correction system according to the present invention comprises:
Signal path extracting means for extracting a predetermined signal path from circuit connection information to obtain a functional block forming the signal path, and a new single functional block that is the same as all the functional blocks forming the predetermined signal path. A new block creating means for creating a new signal, and a modifying means for modifying the new circuit connection information by forming a signal path replaced with the new single functional block instead of all the functional blocks configuring the predetermined signal path. It is characterized by including.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a system block diagram of an embodiment of the present invention. The logic circuit information storage means 1 stores connection information of logic circuits in advance. The delay analysis unit 2 analyzes the delay time of each signal path of the logic circuit information, determines whether the delay time of the signal path exceeds a predetermined limit, and if the delay time exceeds the predetermined limit, the delay path of the signal path is determined as a critical signal. Use as a pass. Then, the type and order (function of signal propagation) of the functional blocks forming the critical signal path are stored in the delay analysis result storage means 3 as the delay analysis result.

The new functional block creating means 5 uses the information on the functional blocks of the critical signal path of the delay analysis result storage means 3 and the information on the functional blocks stored in advance in the functional block information storage means 4 to determine the critical signal. A new single functional block that is the same as all the functional blocks forming the path is created, and the created new single functional block is stored in the functional block information storage means 4.

The logic circuit correction means 6 uses the new single functional block newly stored in the functional block information storage means 4 as the constituent functional block of the critical signal path stored in the delay analysis result storage means 3. The replacement is performed and the critical signal path stored in the logic circuit information storage means 1 is corrected.

The operation of the embodiment of the present invention is shown in FIG.
This will be described with reference to a specific example of (C).

In the logic circuit information storage means 1, it is assumed that the connection information of the logic circuit as shown in FIG. 2A is stored in advance. It should be noted that, in this figure, an example of a signal path composed of wirings indicated by thick lines and the functional blocks 22 to 24 is shown between the functional blocks 20 and 21.

The delay time analysis means 2 analyzes the delay time of this signal path, and if this delay time exceeds the limit value, this path is regarded as a critical signal path. The analysis of the delay time is performed by calculating information such as the wiring length and the delay time of each functional block. Then, regarding this critical signal path, the constituent functional blocks 22 to 2 are
The types and order of 4 are stored in the delay analysis result storage means 3 as analysis results.

Next, the new functional block creating means 5 determines the critical signal path from the analysis result stored in the delay analysis result storing means 3 and the information regarding each functional block stored in the functional block information storing means 4. A new and single functional block 30 having the same functions as all the functional blocks 22 to 24 constituting the above is created as shown in FIG.

That is, all the functional blocks 22 to 24 constituting the critical signal path are regenerated as a single functional block 30 by consolidating them in one place without changing the signal propagation order or the input / output relationship. .. The generated new functional block 30 is stored in the functional block information storage means 4.

The logic circuit correction means 6 stores the information of the signal path of FIG. 2A stored in the logic circuit information storage means 1 in the functional block information storage means 4 of FIG. 2) is modified by using the new functional block of FIG.
Obtain the modified signal path information shown in (C). This signal path information is stored in the logic circuit information storage means 1, and the correction of the critical signal path is completed.

[0016]

As described above, according to the present invention, with respect to a critical signal path whose delay time exceeds the limit value, all the functional blocks constituting this path are replaced with a single new functional block. As a result, the wiring between the functional blocks is eliminated, the delay time between the functional blocks can be substantially reduced to zero, and the delay time can be significantly improved.

[Brief description of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

2A is a signal path diagram showing an example of logic circuit information, FIG. 2B is a single new functional block diagram in which functional blocks constituting the signal path of FIG. FIG. 7B is a new signal path diagram after the signal path correction of FIG.

[Explanation of symbols]

 1 logic circuit information storage means 2 delay analysis means 3 delay analysis result storage means 4 functional block information storage means 5 new functional block creation means 6 logic circuit correction means

Claims (2)

[Claims] 1. A signal path extracting means for extracting a predetermined signal path from circuit connection information to obtain a functional block forming the signal path, and a new novel function identical to all the functional blocks forming the predetermined signal path. New block creating means for creating a single functional block, and a signal path replaced with the new single functional block instead of all the functional blocks forming the predetermined signal path to form new circuit connection information. A circuit information correction system comprising a correction means for correcting. 2. The signal path extracting means includes means for analyzing a delay time of each signal path of the circuit connection information, and means for extracting a signal path exceeding a specified delay time based on the analysis result. The circuit information correction system according to claim 1.