JPH07334530A - Delay minimizing device/method for logic circuit - Google Patents

Abstract

PURPOSE:To provide a delay minimizing device/method for logic circuit, which can suppress the increase of the area and which can minimize the delay of logic circuit. CONSTITUTION:A library input means 100 inputting technology library information 101 used for the technology mapping of logic circuit, a circuit input means 102 inputting logic circuit description 103, a restriction condition input means 104 inputting a restriction condition 105 such as the delay or the area, a, logic optimizing means 106 shortening the delay in accordance with the restriction condition by optimizing logic, analyzing timing in the level of technology independence, obtaining a maximum critical path and partially collapsing only a cluster on the maximum critical path, a technology mapping part 107 mapping a technology library block and a circuit output means 108 outputting logic circuit description 109 which is logically synthesized are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for minimizing the delay amount of a logic circuit, and more particularly to an apparatus and method for minimizing the delay amount of a logic circuit using partial collapsing.

[0002]

2. Description of the Related Art Conventionally, as a delay minimization device for a logic circuit using partial collapsing, for example, "Delay Optimum" in ICCD-'91 (ICCAD-'91) is used.
miza-tion of Combinational Logic Circuits Cluster
ing and Partial Collapsing ”.
Partial collapsing is a process of dividing a circuit into some partial circuits and performing collapsing (two-stage) on each of them.

A conventional process flow will be described with reference to FIG. First, a technology-independent circuit that is not mapped to a technology library block is provided.
Disassembled into standard form. FIG. 13 shows a 2-input N
It is an example of a circuit after being decomposed into AND, the circuit is represented in the form of a graph, a node represents a combinational circuit, a directed technique represents a signal line, and a direction of an arrow indicates a signal flow direction. Is represented.

Next, in step 1201, labeling clustering is performed, and in this process, the circuit is divided into some partial circuits called clusters. The label given to each node corresponds to the number of logic stages from the input terminal. This labeling is performed as follows. A depth-first search is performed from the output terminal to the input terminal, the nodes are searched in the order of the arranged nodes (hereinafter referred to as topological order), and each node v
However, the largest label L in the fan-in is required. If the node v has no fan-in, the label of the node v is 0. Find the number k of all nodes (hereinafter referred to as TFI node groups) that can reach the fan-in direction of the node v having the same label as L, and the value of k is the maximum number of nodes in the cluster. If the threshold value K (hereinafter referred to as cluster size) is exceeded, the label of the node v is set to L + 1, and if it is not exceeded, it is set to L.

A case of a cluster size of 3 will be described as an example with reference to FIGS. 13 and 14. When the nodes are arranged in a topological order, the nodes 1300, 1301, 13
04, 1302, 1303, 1305, 1306, 13
08, 1307, 1309, 1310 in that order. First, the nodes 1300 and 1301 have label 0 because there is no fan-in. Next, the TFI of node 1304
In the node group, the label having the maximum value is the two nodes 1300 and 1301 having the label 0.
Even if 04 is added, since the cluster size is within 3, the label of the node 1304 becomes 0. Similarly, node 130
Label 0 is given to 2, 1313 and 1305.
However, in the case of the node 1306, the one having the maximum label value of 0 in the TFI node group is the node 1300.
There are 6 of 1305, and since the cluster size exceeds 3, the label of the node 1306 becomes 1. In this way, the same process is repeated and all nodes are labeled. In FIG. 14, the numbers in the nodes indicate the label values.

Clustering is performed as follows. The depth-first search is performed in the direction from the input terminal to the output terminal, and the nodes are searched for in the arranged node order (hereinafter referred to as reverse topological order). If the label of the node v is smaller than the label of the fan-out node, a new cluster is created by the node having the same label as the node v and the node v in the TFI node group of the node v. Since the labeling is different and the order is reverse topological, the nodes 1310, 1309, 1307, 130
8, 1306, 1305, 1303, 1302, 130
The search is performed in the order of 4, 1301, and 1300. First,
Since there is no fanout of node 1310, cluster 1404 is created. Also, since there is no TFI node group of the node 1310 having the same label as the node 1310, a cluster 1404 of only the node 1310 can be formed. Next, the label of the node 1309 is fanout 13
Since it is smaller than the label of 10, a cluster different from the cluster 1404 is created. At this time, the TFI node group having the same label as the node 1309 is the nodes 1306 and 1
307, and the cluster 140
3 is created. In FIG. 14, clusters 1400, 1401, 140 corresponding to the respective areas indicated by the broken lines
2, 1403 and 1404 are the results of clustering.

At step 1202, collapsing is performed on all the clusters thus formed. Collapsing is performed on all the nodes in the cluster with respect to the most output node in each cluster. At this time, nodes belonging to a plurality of clusters are subjected to overlapping collapsing processing. The clusters 1400, 1401, 140 shown in FIG. 14 described above.
When collapsing is performed on the nodes 1, 1403 and 1404, as shown in FIG.
To 1504, the number of logic stages from the input terminal to the output terminal is reduced.

[0008]

In the above-described conventional delay minimizing apparatus and method for a logic circuit, collapsing is performed on all clusters when the logic is optimized. In this case, if there are nodes belonging to a plurality of clusters, the nodes must be duplicated, and the required area increases accordingly. Therefore, when the maximum delay value is shortened, there is a disadvantage in that an unnecessary area increase occurs because the collapsing process is performed on the clusters that are not on the maximum critical path.

Further, conventionally, the partial collapsing is considered to be applied only to the technology-independent circuit, and therefore, there is a drawback that it cannot be directly applied to the technology-mapped circuit.

[0010]

A logic circuit delay minimization apparatus according to the present invention inputs a library input means for inputting technology library information used for technology mapping of a logic circuit, and a logic circuit description corresponding to the logic circuit. Circuit input means, constraint condition input means for inputting constraint conditions including delay and occupied area by the logic circuit, and logic optimization processing, and partial collapsing of only clusters on the maximum critical path By doing so, the logic optimization means having the function of minimizing the delay and the mapping of the technology library block in consideration of the constraint conditions including the delay and the occupied area by the logic circuit are performed and the maximum critical path By partially collapsing only the clusters A technology mapping means having a function that minimizes the delay, is characterized in that at least comprises a circuit output means for outputting the logic circuit logic synthesis, a.

In the logic circuit delay minimization method of the first invention, the logic optimization means included in the logic circuit delay minimization apparatus performs timing analysis on the logic circuit at a technology-independent level, In the first step of obtaining the maximum critical path corresponding to the logic circuit, and in the first step, if even one of the required times in the input circuit of the logic circuit is not satisfied, labeling clustering is performed to perform collapsing. According to a constraint condition including a delay and an occupied area by the logic circuit, and a second step of creating a cluster to be processed, a third step of selecting only the cluster on the maximum critical path and performing partial collapsing. A fourth step of determining whether or not has been shortened It is characterized in Rukoto.

According to a second aspect of the present invention, there is provided a logic circuit delay minimization method, wherein the technology mapping means included in the logic circuit delay minimization apparatus uses the delay data of the technology library block to analyze the timing of the logic circuit. And a first step of obtaining a maximum critical path corresponding to the logic circuit, and labeling clustering when the required time in the input circuit of the logic circuit is not satisfied in the first step. The second step is to create a cluster to be collapsed, and the third step to select only the cluster to be collapsed on the maximum critical path for technology independence, and only the cluster on the maximum critical path to be selected. 4th step of partial collapsing And flop, a fifth step of re-technology map pink part circuits Korappushingu, subject to constraints including delay and area occupied, etc. by the logic circuit, the determining whether the delay is shortened 6
And at least the steps of.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, in the present embodiment, the library input means 1 that receives the technology library information 101 used for the technology mapping of the logic circuit is input.
00 and the circuit input means 1 for inputting the logic circuit description 103
02, constraint condition input means 104 for inputting a constraint condition 105 such as delay or area, and timing analysis at a technology-independent level together with logic optimization to obtain the maximum critical path, and only the clusters on the maximum critical path are partially A logic optimizing unit 106 that reduces delay according to a constraint condition by wrapping, a technology mapping unit 107 that performs mapping of technology library blocks, and a circuit output unit 108 that outputs a logic-synthesized logic circuit description 109. It is equipped with. Further, FIG. 2 is a flowchart showing a processing procedure in this embodiment.

Next, the operation of the optimization processing means 106 in FIG. 1 will be described with reference to FIG. Note that FIG.
FIG. 4 is a diagram showing an input logic specification in the present embodiment, in which arrival times arvl of input signals of nodes 600, 601, 602 and 603 on the input side are 12 as delay constraints, respectively.
0, 120, 120, 0, and the requested times req of the output side nodes 609 and 611 are 15 respectively.
The cluster size is set to 0 and 150 and the cluster size is set to 4.

First, in step 200, timing analysis is performed. The numbers shown in the nodes in FIG. 6 represent literal numbers. The timing analysis here means the calculation of the maximum delay value of each path. This is a value obtained by adding the arrival times of the signals that arrive at the output side of the node latest among the signals input to each node in order from the input side of the path. In the case of technology independence, the following formula is used as the delay calculation formula of each node.

D = a ₀ + a ₁ lnc + a ₂ lnf ………………………… (1) This is the “High-Level DelayEstimation for Technology-Indep” in ICCD'90 (ICCD-'90).
ndent Logic Equations ”. In the above equation (1), d is the delay of the node, c is the complexity of the logic function, and f is the fanout number of the node. a ₀ , a ₁ and a ₂ are technology-dependent parameters. Technology-dependent parameters. Technology-dependent parameters depend on the given technology library to be mapped. The delay time when the circuit is actually mapped is statistically processed and calculated.Here, assuming that the number of literals of all nodes and the complexity of the logic function are equal, the technology-dependent parameter is _{, a 0 = 30, a 1} = 60, if it is assumed that a ₂ = 10, the arrival time arvl the output side of the node 609 shown in Figure 7, when the request req and slack sl
ack (req minus arvl) is arvl = 3
66, req = 150, slack = -116, and the node 611 has arvl = 526, req = 150, slack, respectively.
= -376. Here, if there is no negative output for the slack, it is assumed that all the required times of the input circuit are satisfied in step 200, and the processing in the logic optimizing means 106 ends. Note that, also in the following description, as numerical examples of the technology-dependent parameters, the above a ₀ = 30, a ₁ = 60,
Let us use a ₂ = 10.

On the other hand, if at least one negative output terminal exists in the slack, it is determined in step 200 that all the required times of the input circuit are not satisfied, and the process proceeds to the next step 201, and in step 201. , Labeling clustering is performed. FIG. 3 is a flowchart showing the processing steps of this labeling clustering. The processing steps of the labeling and clustering will be described below.

In FIG. 3, first, at step 300, a determination process as to whether or not labeling / clustering has been performed is performed. If the determination process has already been performed, the label link clustering process ends. On the other hand, when the labeling / cluster rig processing has not been performed yet, the number of occupied clusters and the start label are set in step 301. In the present invention, the cluster sizes are evaluated by the number of literals so that the nodes are not divided into two-input NAND and the nodes are not aligned in the same size, and the cluster sizes are aligned. However, when the cluster size is evaluated by the number of literals, one node may exceed the class size K. Therefore, it is necessary to calculate the number of occupied clusters lev occupied by one node. If the number of literals in the node is within the cluster size K, the number of occupied classes
Let lev = 1. The number of literals in the node is the class size K
In the above case, the number of occupied clusters lev is calculated by the following formula.

Lev = (a ₀ + a ₁ lnc) / (a ₀ + a ₁ lnK) (2) From the above equation, the number of occupied clusters lev (v) of the node v is rounded to the nearest whole number and rounded to the nearest whole number. Convert and calculate. c is the logical complexity. a ₀ and a ₁ are delay parameters in equation (1), and K is the cluster size. When the cluster size K = 4, the literal number of the node 611 is 1
Since 3 is greater than 4, lev = 2 is calculated by the above equation (2). For all other nodes, lev
= 1.

In the present embodiment, the label of the input terminal starts from alev in consideration of the case where the arrival times of the input terminals are different. In this case, the value of alev is calculated by the following formula (rounded to the nearest whole number).

Alev = (arrival time) / (a ₀ + a ₁ lnK) (3) In the above expression, arrival time is the arrival time of the input terminal, and a ₀ and a ₁ are in the above expression (1). The delay parameter, K, is the cluster size. However, except for the input terminals, alev = 0. The values of the nodes 600, 601, 602, and 603 are arrival time of arvl shown in FIG. 7, and therefore, from the above equation (3), these nodes 60
The values of 0, 601, 602 and 603 are alev = 1, alev = 1, alev = 1 and alev = 0, respectively, as shown in FIG.

Next, in step 302, labeling is performed. The labeling is the same as in the prior art, but in the present invention, the start label is set to alev instead of 0, and the label difference between adjacent clusters is processed to lev instead of 1. Next, in step 303, clustering processing is performed. Since the processing content of this clustering is the same as the clustering in the above-described conventional example, the description thereof is omitted here. Note that FIG. 9 shows the result of the labeling process and the clustering process corresponding to the content of the timing analysis of the input circuit shown in FIG. 7, and the region surrounded by the broken line corresponds to the cluster.

Next, returning to FIG. 2, in step 202, collapsing is performed. The content of this collapsing process is shown in the flowchart of FIG. 4. First, in step 400, a cluster to be collapsed is selected. In the prior art, collapsing is performed on all clusters, but in the present invention, clusters on the maximum critical path are selected and collapsing. The maximum critical path of the circuit in this embodiment shown in FIG. 9 is assumed to be the path indicated by the thick arrow in the cluster selection diagram of FIG. In this case, the clusters 902 and 906 are clusters on the maximum critical path and have two or more nodes, so they are candidates for collapsing. As the cluster to be collapsed, the cluster having the smallest evaluation function is selected by the following equation (4).

[0025]

The evaluation value by the above equation (4) is obtained for the node with the smallest slack. If the clusters are on multiple maximum critical paths, the slack minimum nodes are on many of those paths, and the clusters that are less likely to overlap due to collapsing are selected.
slack (c) i is for all nodes (hereinafter, slack of cluster c that can reach its fanout direction).
It is the slack of the output terminal when it is equal to the slack of the i-th output terminal in the TFO node), and is 0 when they are not equal. N (c) is the TF of cluster c
It is the number of output terminals that become O nodes, and dulp (c) is the total number of literals of overlapping nodes in the cluster. α and β are coefficients that indicate which of the delay time and the area is to be emphasized. The larger α, the higher the degree of attention of the delay time, and the larger β, the higher the degree of attention of the area. In the present embodiment, when α = 1 and β = 1, as the value of value, the cluster 902 is value = −376 + 0 = −
376, and the cluster 906 has value = -376 + 2
= -374, the cluster 902 is selected.
Next, in step 401, cluster selection determination processing is performed. If no cluster is selected in step 400, the collapsing process is completed. On the other hand, in step 400,
When the cluster is selected, the collapsing process is executed in step 402, and the collapsing process ends. As a result, all processing by the logic optimizing means 106 shown in FIG. 1 is completed.

Returning to FIG. 2, in step 203, delay improvement determination processing is performed. FIG. 5 is a flowchart showing the processing steps of this delay improvement determination processing. The processing steps of the delay improvement determination processing will be described below. In FIG. 5, first, the arrival time of the collapsed node is calculated by the above equation (1), and step 50
At 0, arrival time determination is performed. If the delay is improved in step 500, the delay improvement determination process ends. On the other hand, if the delay is not improved, the process proceeds to step 501, and the restoration process for the circuit before the collapsing process is performed. Once done, return to step 200 shown in FIG. In FIG. 2, step 203
When the delay improvement determination process of step 200 is completed, the step 200 is performed again.
Although the process is repeated more and more, the cluster restored in step 203 is excluded from the selection targets in the subsequent cluster selection process and the process is continued. Then, in step 200, when all the required times of the input circuit are satisfied, or in step 202
In, when the cluster having the smallest evaluation function is not selected, all the processes are completed.

Next, a second embodiment of the present invention will be described. This embodiment has the same basic configuration as that of the first embodiment described above and is as shown in FIG. 1, but it is different from the first embodiment in that it handles a technology-dependent circuit.
Is different from the embodiment described above. Regarding processing points, in the technology mapping means 107 shown in FIG. 1, partial collapsing is applied and timing analysis using technology library block data is used. Further, the processing flows of the first embodiment shown in the processing flow of FIG. 2, the labeling / clustering processing flow of FIG. 3, and the delay improvement determination processing flow of FIG. 5 are exactly the same in the case of the present embodiment. The processing flow is different from that of the present embodiment only in the collapsing processing flow in the first embodiment of FIG. The collapsing processing flow of this embodiment corresponding to FIG. 4 of the first embodiment is as shown in the processing flow of FIG. 11, and as is clear from the comparison between FIG. 4 and FIG. 11, in FIG. , Step 402 before the step 402, a step 1100 for making the nodes to be collapsed technology independent, and a step 1101 for mapping the collapsed nodes after the step 402 are added.

Regarding the collapsing processing flow of this embodiment, in FIG. 11, first, in step 400, a cluster to be collapsed is selected. Next, in step 401, a cluster selection determination process is performed. If no cluster is selected in step 400, the collapsing process is completed. On the other hand, in step 400,
When the cluster is selected, in step 1100, the nodes to be collapsed are technology-isolated and the process proceeds to step 402, in which the collapsing process is executed. Next, in step 1101, the collapsed nodes are mapped, and the collapse processing ends.
As a result, all processing by the logic optimizing means 106 shown in FIG. 1 is completed.

Further, in this mapping process part, a separate delay optimization method can be applied to the mapping process.

According to the result of the experiment by applying the present invention, it is possible to reduce the area of the circuit having about 100 to 1000 gates by about 2% on average and about 12% at the maximum as compared with the prior art. Has become.

[0032]

As described above, according to the present invention, the technology mapping reduces the delay of the logic circuit according to a predetermined constraint condition. Therefore, the maximum critical path is obtained by using the technology independent timing analysis. , By partially collapsing only the clusters on the maximum critical path, collapsing processing of the clusters that does not affect the reduction of the maximum delay can be eliminated, thereby preventing an increase in the required area. In addition to the above, there is an effect that it can be directly applied to a technology-mapped circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing first and second embodiments of the present invention.

FIG. 2 is a diagram showing a processing flow of the first embodiment.

FIG. 3 is a diagram showing a labeling / clustering processing flow of the first embodiment.

FIG. 4 is a diagram showing a collapsing process flow of the first embodiment.

FIG. 5 is a diagram showing a delay improvement determination processing flow of the first embodiment.

FIG. 6 is a diagram showing an input logic specification of the first embodiment.

FIG. 7 is a diagram showing a timing analysis of the input circuit of the first embodiment.

FIG. 8 is a diagram showing the number of occupied clusters and the setting of a start label in the first embodiment.

FIG. 9 is a diagram showing labeling clustering according to the first embodiment.

FIG. 10 is a diagram showing cluster selection according to the first embodiment.

FIG. 11 is a diagram showing a processing flow of the second embodiment of the present invention.

FIG. 12 is a diagram showing a processing flow of a conventional example.

FIG. 13 is an exploded view of a conventional 2-input NAND standard type.

FIG. 14 is a diagram showing conventional labeling and clustering.

FIG. 15 is a diagram showing collapsing in a conventional example.

[Explanation of symbols]

100 Library Input Means 101 Technology Library Information 102 Circuit Input Means 103, 109 Logic Circuit Description 104 Constraint Condition Input Means 105 Constraint Conditions 106 Logic Optimization Means 107 Technology Mapping Means 108 Circuit Output Means 200 Timing Analysis 201, 1201 Labeling Clustering 202, 302, 402, 1202 Collapsing 203 Delay improvement determination 300 Labeling / clustering determination processing 301 Occupied cluster number and start label setting 303 Clustering 400 Cluster selection 401 Cluster selection determination 500 Arrival time determination 501 Return processing 600-611, 1300-1310, 1500 ~ 15
04 node 900-907, 1400-1404 cluster 1100 technology independence 1101 mapping 1200 2-input NAND standard form decomposition

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Naotaka Maeda 5-7-1 Shiba, Minato-ku, Tokyo Inside NEC Corporation

Claims (3)

[Claims] 1. A library input unit for inputting technology library information used for technology mapping of a logic circuit, a circuit input unit for inputting a logic circuit description corresponding to the logic circuit, a delay and an occupied area in the logic circuit, and the like. A logical optimization that has a function that can minimize the delay by performing the logical optimization process and the partial collapsing of only the clusters on the maximum critical path, together with the constraint condition inputting device that inputs the constraint conditions including And a technology library block in which a constraint condition including a delay due to the logic circuit and an occupied area is taken into consideration, and the delay is reduced by partially collapsing only the cluster on the maximum critical path. Technology with the ability to minimize Mappings means and delay minimization device of the logic circuit, characterized in that it comprises a circuit output means for outputting the logic circuit logic synthesis, at least. 2. A first step of obtaining a maximum critical path corresponding to the logic circuit by performing timing analysis on the logic circuit at a technology independent level in a logic optimizing means included in the delay minimization device for the logic circuit. And in the first step, if any of the required times in the input circuit of the logic circuit is not satisfied,
A second step of creating a cluster for performing collapsing by performing labeling clustering, a third step of selecting only a cluster on the maximum critical path and performing partial collapsing, and a delay and an occupied area in the logic circuit are described. A fourth step of determining whether or not the delay has been shortened in accordance with a constraint condition including: and a delay minimization method for a logic circuit, comprising: 3. A technology mapping means included in the delay minimization device for the logic circuit performs a timing analysis on the logic circuit using the delay data of the technology library block to obtain a maximum critical path corresponding to the logic circuit. In the first step, and in the first step, if even one of the required times in the input circuit of the logic circuit is not satisfied,
The second step of creating clusters for collapsing by performing labeling clustering, the third step of selecting only the clusters to be collapsed on the maximum critical path to be technology independent, and the cluster on the maximum critical path only. The fourth step of selecting and partially collapsing, the fifth step of re-technology mapping the collapsed partial circuit, and the reduction of the delay according to the constraint conditions including the delay and the occupied area by the logic circuit. A sixth step of determining whether or not the delay has been made, and a delay minimization method for a logic circuit, comprising: