JP3004589B2 - Pass transistor logic design method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a design automation technique for improving the efficiency of designing circuits such as LSIs, and more particularly to a technique for generating a pass transistor logic circuit based on a functional description of a circuit at a stage independent of process technology. It relates to a logic design method.

[0002]

2. Description of the Related Art Recently, attention has been paid to a pass transistor logic having features of higher speed, lower power consumption and smaller area than CMOS logic which has been widely used in the past.

On the other hand, in order to cope with the problem of an increase in the number of design steps of an LSI which is increasing in scale, a top-down design in which an LSI is functionally described using a hardware description language and a logic circuit is automatically designed using an automatic logic synthesizer. The technique has become widespread. Automatic logic synthesis from functional description is a key technology of this top-down design method, and has been energetically researched and developed.

As the top-down design method has become widespread as described above, even if the above-mentioned pass transistor logic is
Even if it has characteristics superior to OS logic, it cannot be widely used as logic design technology if it cannot be designed automatically and must be carefully designed by hand. It is considered that only the special circuit is used.

Therefore, it is essential to establish an automatic design technique for improving the performance and reducing the cost of an LSI by utilizing the excellent characteristics of the pass transistor logic.

As an example of a conventional pass transistor logic design method, for example, “Lean Integration: Achieving a Qu
antum Leap in Performance and Cost of Logic LSIs ''
(IEEE 1994 Custom Integrated Circuits Conferenc
e) can be mentioned.

Hereinafter, a design flow described in the above document will be described.

First, a binary decision diagram is generated from a logical specification expressed in a hardware description language or the like.

Next, the nodes in the graph are replaced with pass transistors to form a transistor network.

Next, a buffer is inserted at an appropriate place in the network for the purpose of restoring the potential level and amplifying the current.

Next, a prepared lean cell is assigned to the generated circuit, and a netlist is output.

In the above processing flow, the first two steps are technology-independent processing that does not depend on a specific cell library, and the last two steps are technology-dependent processing.

[0013]

SUMMARY OF THE INVENTION The present invention is to solve the problem in the technology independent processing among the above-mentioned conventional methods.

[0014] Such problems include the following.

(1) Low Power Consumption With the advance of semiconductor integrated circuit technology, the number of elements that can be integrated on one chip exceeds several million Tr, and as a result, heat generation of the LSI has become a serious problem. Also, with environmental changes such as the expansion of the market for portable devices, reducing power consumption of LSIs has become an important issue.

The same applies to a pass transistor logic characterized by lower power consumption than CMOS.

(2) Speed-up Although pass transistor logic is said to be faster than CMOS logic, the actual circuit performance is often determined by the delay of a specific critical path. Even though on average in many passes faster than CMOS circuits,
If the delay of these critical paths that determine the performance is large, the performance as a circuit will be low.

(3) Circuit Size Reduction In the conventional design method in which each node of the generated BDD is replaced with a pass transistor, the finally generated circuit size largely depends on the size of the BDD. On the other hand, it is known that the size of BDD depends on the input signal order in Shannon expansion processing. Therefore, in order to reduce the circuit size, it is necessary to optimize the input signal order, but this is a difficult problem to determine, and "minimizing a binary decision diagram representing a logical function" Report COMP91-15 p2
As described in 7), at present, no effective method is known when the number of inputs exceeds about 17.

In a practical circuit, the number of input signals is 100
Therefore, it is impossible to optimize the input signal sequence of such a circuit. As a result, the size of the BDD becomes larger than the optimum one, and the final circuit scale also increases.

Also, there is no guarantee that the method of converting the entire circuit into an integrated BDD will produce a minimum circuit.

An object of the present invention is to improve the processing of generating a BDD from a logic specification, thereby realizing low power consumption, high speed, and a reduction in circuit scale, which were difficult with the conventional pass transistor logic design method. Is to do.

[0022]

According to the present invention, there is provided a method of designing a pass transistor logic circuit based on a logic specification of a given circuit, the logic circuit including a logic gate based on the logic specification. Generating, and evaluating the signal transition probability of each input signal of the logic circuit, ordering the input signal from the highest signal transition probability to the lowest signal transition probability, and for the logic circuit, Generating a binary decision diagram corresponding to the logic circuit by applying Shannon expansion processing in the order of the signal transition probability of the input signals in descending order; Generating a technology-independent pass transistor logic circuit by replacing with a two-input selector circuit. By reducing the number of logic stages between the high transition probability input and output signals, characterized in that to reduce the power consumption of the generated circuit. This achieves the above object.

The above method is based on a delay time constraint defining a delay time allowed between input and output signals of the given circuit and an average delay time of a pass transistor logic circuit.
Calculating a stage number constraint defining the number of stages allowed in the pass transistor logic circuit, wherein the input signal of the logic circuit may be ordered in consideration of the stage number constraint and the signal transition probability. Good.

[0024] The stage number constraint may have a higher priority than the signal transition probability.

Another method of the present invention is a method of designing a pass transistor logic circuit based on a logic specification of a given circuit, wherein a logic circuit including a logic gate is generated based on the logic specification. And defining the number of stages allowed in the pass transistor logic circuit based on a delay time constraint defining a delay time allowed between input and output signals of the given circuit and an average delay time of the pass transistor logic circuit. Calculating a stage number constraint, determining an optimal input signal order for Shannon expansion in consideration of the stage number constraint, and performing Shannon expansion processing on the logic circuit in accordance with the input signal order. Generating a binary decision diagram corresponding to the logic circuit by applying each of the nodes; Generating a technology-independent pass transistor logic circuit by substituting a two-input selector circuit with a delay time constraint, thereby limiting the number of pass transistor stages between the input signal and the output signal given the delay time constraint. Allows multiple pastora
Without taking steps to generate and compare transistor circuits,
The generated circuit satisfies a given delay time constraint. This achieves the above object.

Another method of the present invention is a method of designing a pass transistor logic circuit based on a logic specification of a given circuit, wherein a logic circuit including a logic gate is generated based on the logic specification. Performing a logic optimization process on the logic circuit to delete a redundant circuit;
Dividing the optimized logic circuit into a plurality of sub-circuits in consideration of the number of input signals of each of the divided sub-circuits, and minimizing a generated binary decision diagram. Determining an optimal order of input signals for Shannon expansion for each of the plurality of sub-circuits, and applying Shannon expansion processing according to the order of the input signals for each of the plurality of sub-circuits. Generating a binary decision diagram corresponding to the logic circuit; and replacing, for each of the plurality of sub-circuits, each node of the binary decision diagram with a two-input selector circuit using pass transistors. Generating a transistor logic circuit to limit the number of input signals of the individual sub-circuits. To allow determination of optimal input signal sequence by, characterized by minimizing the circuit generated. This achieves the above object.

The method further includes evaluating a signal transition probability of each of the input signals of the sub-circuit, wherein an order of the input signals of the sub-circuit is determined based on the signal transition probabilities. Is also good.

The above method is based on a delay time constraint defining a delay time allowed between input and output signals of the given circuit and an average delay time of a pass transistor logic circuit.
The method may further include calculating a stage number constraint defining the number of stages allowed in the pass transistor logic circuit, and the order of the input signals of the sub-circuit may be determined based on the stage number constraint.

The above method is based on a delay time constraint defining a delay time allowed between input and output signals of the given circuit and an average delay time of a pass transistor logic circuit.
The method further includes calculating a number-of-stages constraint defining the number of stages allowed in the pass transistor logic circuit, wherein the order of the input signals of the sub-circuit is determined based on the number-of-stages constraint and the signal transition probability. Is also good.

The operation will be described below.

According to the present invention, by adopting the above configuration, in processing for generating a BDD corresponding to a given logical specification, Shannon expansion of input signals having a high transition frequency is performed first, and those having a low transition frequency are performed. Will be later expanded to Shannon.

In the BDD, since the node corresponding to the input signal which has been Shannon-expanded earlier is closer to the output side, after converting each node of the BDD into a pass transistor, the number of logic stages between the input and the output having a higher transition frequency becomes higher. Becomes smaller.

Since an internal signal included in a path between an input signal and an output having a high transition frequency often has a high transition frequency, by reducing the number of logical stages of such a path,
The sum of transition frequencies of all signals included in the circuit can be reduced.

Since the BDD often spreads from the root to the branch similarly to other graphs, the number of pass transistors connected to the input having a high transition probability decreases, and in that sense, the overall transition frequency also increases. Can be reduced.
As a result, the power consumption of the circuit can be reduced.

In the present invention, a pass transistor stage number constraint corresponding to the delay time constraint is calculated from a given delay time constraint between input and output and a previously determined average delay time of the pass transistor circuit.

In the design method of the present invention in which each node of the BDD is replaced with a pass transistor, the order of the input signals of Shannon expansion at the time of generating the BDD is directly related to the number of pass transistor stages between input and output. The constraint on the number of stages can be replaced by a constraint on the input signal order.

After obtaining the constraints on the number of pass transistor stages corresponding to all the delay time constraints, the Shannon expansion order of the input signal satisfying these constraints is determined. The BDD is generated by performing Shannon expansion according to the order obtained in this manner, and the result is converted into a pass transistor circuit. The result satisfies the constraint on the number of pass transistor stages. By careful design in the subsequent technology-dependent processing, a circuit that satisfies given delay constraints can be designed.

Also, in the present invention, considering the difficulty of determining the optimal input signal order for minimizing the size of the BDD,
First, at the stage of converting the logic specification to a normal logic circuit,
It is divided into a plurality of sub-circuits. Here, division is performed so that the number of inputs of each sub-circuit is equal to or less than a predetermined number.

In such a design method, the entire circuit does not become one BDD, and the redundancy of the logic cannot be removed between a plurality of BDDs. Preliminarily performs a logic optimization process.

In the sub-circuit having a limited number of inputs, the order of input variables in Shannon expansion can be optimized, and the size of the BDD corresponding to each sub-circuit can be minimized.

On the other hand, when converting the entire circuit into one BDD, it is highly likely that the optimal input variable order cannot be found and the size of the BDD will not be minimized. As a result, the scale of the final pass transistor circuit is reduced.

Also, depending on the circuit, the circuit scale may be smaller when converting to a network composed of a plurality of BDDs and then converting to a pass transistor logic circuit than generating a pass transistor logic circuit after converting to an integrated BDD. In many cases.

[0043]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a processing flow chart showing a processing flow of a pass transistor logic design method according to the present invention.

In the figure, a logical specification 1 describes a logical specification of a circuit to be designed in a format such as a hardware description language or a logical expression.

FIG. 4 shows a hardware description language verilo.
It is an example of a function description using gHDL. This describes the operation of a 4-bit adder that outputs the result of adding two 4-bit input values a and b to y. The present embodiment is a combinational circuit, and can be directly processed by the design method of the present invention using BDD. However, since the sequential circuit can also be divided into a combinational circuit and a flip-flop, the design method of the present invention can be applied to the combinational circuit portion.

FIG. 5 is an example of a logical expression expressing the most significant bit y3 of the output y of the 4-bit adder. here"
&"Is a logical product," | "is a logical sum, and" $ "is an operator representing an exclusive logical sum.A logical expression is an example of a logical specification similarly to the above-described functional description. It may be expressed in other formats.

In step 2, a hardware description language (H
A logic circuit composed of ordinary gates is generated on the basis of logical specifications such as a function description and a logical expression using DL). In this step, there are a method of manually performing a logic design and a method of using a logic synthesis tool, and any method may be used.
In the present embodiment, the latter is adopted.

FIG. 6 shows a step 2 based on the logical expression shown in FIG.
Is an example of a logic circuit generated by the processing of FIG. Here, a circuit is represented by a network of logic gates such as AND and OR. In this embodiment, this one-output logic circuit will be described as an example, but a multi-output logic circuit can be basically handled in the same manner.

In step 3, the signal transition probability of each input of the logic circuit generated in step 2 is evaluated. Normal,
In most cases, a logic circuit is designed in a synchronous manner that operates in synchronization with a clock. In this case, the values of all the signals in the circuit are determined in synchronization with the clock, and the values change in a certain clock cycle from the previous cycle, and retain the values of the previous cycle in another clock cycle. The signal transition probability is defined by dividing the number of clock cycles whose value changes by the total number of clock cycles.

The power consumption of each signal in the logic circuit is given by (Equation 1). Since there is the relationship of (Equation 2), it is understood that the power consumption of each signal is proportional to the signal transition probability. Since the power consumption of the entire circuit is the sum of the power consumption of each signal of the circuit, it is necessary to reduce the signal transition probability of each signal of the circuit in order to reduce the power consumption of the circuit.

[0052]

P = (1/2) · C · Vdd ² · SWR C: load capacitance of signal, Vdd: power supply voltage of circuit, SW
R: Number of transitions per unit time of signal

[0053]

SWR = STR / Tcycle STR: signal transition probability, Tcycle: clock cycle time If the logic circuit is an entire circuit to be designed, its input is an external input of the entire circuit and its signal transition The probability is determined by the specification of the signal input to the circuit. However, usually, circuits are designed hierarchically and logically designed for each sub-circuit in many cases. In this case, the signal transition probability of the input of the sub-circuit is roughly determined by the specification of the signal given to the external input of the entire circuit and the logic of the peripheral sub-circuit connected to the sub-circuit. There are several methods for evaluating the signal transition probability. In the present embodiment, the evaluation is performed by logic simulation.

FIG. 7 shows an example of a test vector given to an input signal in a logic simulation. Each row is one vector and describes a signal applied to an input in a certain clock cycle. Each number in the vector represents the value of the corresponding input signal by position. The first row describes the vector of the first clock cycle, the next row describes the vector of the second clock cycle, and so on.

When the input value of each clock cycle is determined,
Then, by performing a logical operation, each internal signal value of the circuit in each clock cycle is determined. By comparing the signal value of each clock cycle with the value of the previous cycle, it is determined whether or not the signal has changed, so that the signal transition probability can be calculated. Since the internal signal includes the input signal of the sub-circuit, the signal transition probability of the input of the sub-circuit can be obtained.

In order to accurately evaluate the signal transition probability by the method based on the logic simulation, it is necessary to prepare an appropriate test vector that accurately reflects a situation actually used.

In step 4, the input signals are ordered in descending order of the signal transition probability of each input evaluated in step 3. FIG. 8 shows an ordered list of input signals.

In step 5, Shannon expansion is performed on the logic circuit generated in step 2 according to the order determined in step 4 to generate a binary decision diagram (BDD).

The Shannon expansion of the logical function f by the input variable p is a logical function in which the input p in f is fixed to 1
[p = 1], a logical function in which the input p in f is fixed to 0 is f
When [p = 0] is used, the left side is converted to the right side by using the fact that the equation shown in (Equation 3) holds. It can be seen that the logic on the left side is an alternative logic of f = f [p = 1] if p is 1, and f = f [p = 0] if p is 0. The logic circuit generated in step 2 corresponds to the logic function of (Equation 4). When y3 is Shannon-expanded with a0 according to the order, (Equation 5) and (Equation 6) are developed, and (Equation 7) is developed.

[0060]

F = p & f [p = 1] | ＾ p & f [p = 0] “&”: logical product, “|”: logical sum, “＾”: logical inversion

[0061]

Y3 = ((a0 & b0 & (a1 | b1) | (a1 & b1)) & b2 | (a0 & b0 &
(a1 | b1) | (a1 & b1) | b2) & a2) @ a3 @ b3

[0062]

Y3 [a0 = 1] = ((b0 & (a1 | b1) | (a1 & b1)) & b2 | (b0 &
(a1 | b1) | (a1 & b1) | b2) & a2) @ a3 @ b3

[0063]

Y3 [a0 = 0] = ((a1 & b1 & b2) | ((a1 & b1) | b2) & a2)
@ a3 @ b3

[0064]

[Equation 7] y3 = a0 & y3 [a0 = 1] | ∧a0 & y3 [a0 = 0] Further, when Shannon expansion is subsequently performed on b0, (Equation 8) is obtained. On the other hand, y3 [a0 = 0] does not include b0, so there is no need for Shannon expansion. Therefore, it is expanded to (Equation 9).

[0065]

[Equation 8] y3 [a0 = 1] [b0 = 1] = ((a1 | b1 | (a1 & b1)) & b2 | (a1 |
b1 | (a1 & b1) | b2) & a2) @ a3 @ b3 y3 [a0 = 1] [b0 = 0] = ((a1 & b1 & b2) | ((a1 & b1) | b2) & a2) @
a3 @ b3

[0066]

[Equation 9] y3 = a0 & b0 & y3 [a0 = 1] [b0 = 1] | a0 & ∧b0
& y3 [a0 = 1] [b0 = 0] | ∧a0 & y3 [a0 = 0] Subsequently, Shannon expansion is executed for a1, b1, a2, b2, a3, and b3.

FIG. 9 shows the BDD generated in this manner. A non-terminal node (round node) of the BDD corresponds to one logical function Shannon-expanded by an input variable described in the node. The edge extending upward from each node is an output edge, which transmits the logical function represented by that node to the upper node. On the other hand, edges extending downward from each node include those written as 1 (1 edge) and those written as 0 (0 edge). The former is connected to a node corresponding to a logical function with an input variable fixed to 1 in the Shannon expansion, and the latter is connected to a node corresponding to a logical function with an input variable fixed to 0.

That is, the uppermost node 31 corresponds to the output y3 of the logic circuit. The node 32 corresponds to a logical function in which the input variable a0 is fixed to 1 in the logical function of y3. There are terminal nodes (square nodes) described as 1 and nodes described as 0, which correspond to logical constants 1 and 0, respectively. Since the zero edge of the node 35 is connected to the constant 1 and the one edge is connected to the constant 0, it can be seen that the corresponding logical function is (Equation 10). Similarly, node 36 corresponds to logic function b3. The logical function corresponding to the node 33 is (Equation 11).

[0069]

[Equation 10] b3 & 0 | ∧b3 & 1 = ∧b3

[0070]

A3 & ∧b3 | ∧a3 & b3 = a3 @ b3 In step 6, the BDD generated in step 5 is converted into a pass transistor logic circuit. As described above, each node of the BDD is an alternative logic, while the pass transistor logic is based on a two-input selector.
By applying the conversion shown in FIG. 10 to each node of the BDD, a corresponding pass transistor circuit can be obtained.

FIG. 11 shows a pass transistor logic circuit converted from the BDD of FIG. As shown in FIG. 11, as the input has a higher signal transition probability such as a0 or b0, the number of pass transistor stages up to the output y3 is smaller, and conversely, the input has a lower signal transition probability such as a3 or b3, the larger the number of pass transistor stages up to the output. It can be seen that the power consumption has been reduced.

In practice, many pass transistors cannot be connected in series as shown in FIG. 11, and it is necessary to insert a buffer for restoring potential and amplifying current at an appropriate place. Is not processed in a technology-independent logic design step, but in a subsequent technology-dependent logic design step. Therefore, although the final number of pass transistor stages between input and output and the number of transitions of internal signals per unit time in the final pass transistor logic circuit cannot be estimated at this stage, the relative distance from each input to the output is final. It is also stored in the circuit.

FIG. 12 shows a “BDD processing technique on a computer” (information processing vol. 34 No. 5 p59) without performing the ordering of input signals based on signal transition probabilities as in the present embodiment.
As described in 3), a method of performing Shannon expansion on inputs having strong locality in order from the input having the strong power to control the output, and the BDD generated in this manner. It is reported that the logic circuit generated in step 2 was converted to BDD when the size of the logic circuit was reduced.)

FIG. 13 shows a pass transistor logic circuit converted from the BDD of FIG. FIG. 13 shows that a0 has a higher signal transition probability than the result (FIG. 11) according to the present embodiment.
It can be seen that the number of pass transistor stages from the input like y and b0 to the output y3 is large. As previously mentioned,
Since the internal signal included in the path from the input to the output having a high signal transition probability has a high transition frequency, the result of FIG. 13 consumes more power than the result of the present embodiment.

In fact, “Technology Decomposition and M
apping Targeting Low Power Dissipation '' (30th IEEE
As a result of estimating the sum of the signal transition probabilities of all the signals included in both circuits by the method described in Design Automation Conference p68), the result of the present embodiment is 11.4, whereas the result of FIG. As a result, it is understood that the result is reduced by about 30% to 16.6, which indicates that the method according to the present embodiment has a great effect in reducing power consumption.

(Embodiment 2) FIG. 2 is a process flowchart showing a process flow of a pass transistor logic design method according to the present invention. Since the logic specification 1 of this embodiment and step 2 of generating a logic circuit using normal gates are the same as those of the first embodiment, the description is omitted here.

Normally, in the design of a logic circuit, it is necessary to satisfy the given logic specification 1, but in addition to that, a delay time constraint 13 to be satisfied by the circuit is often given. In the combinational circuit design as in the present embodiment, the delay time constraint is generally given by the maximum delay value from input to output as shown in FIG.

Here, the delay from the input a0 to the output y3 is 2.
It is described that the delay from the input b0 to the output y3 must be 1.5 ns or less for 0 ns or less. No delay constraint is applied to inputs other than a0 and b0. The delay constraint is often given in the form of a maximum delay value from all inputs to all outputs.However, for example, a specific input signal is delayed more than another Is often performed in an actual design.

In step 14, a constraint on the number of pass transistor stages between input and output is calculated based on the given delay time constraint. For this purpose, it is necessary to previously determine the average delay time per pass transistor stage by some method. Usually, these values fluctuate depending on the characteristics of the circuit to be designed. Therefore, it is important to obtain a highly reliable value by collecting statistics on as many circuits as possible.

Here, assuming that a delay value of 0.4 ns on average per pass transistor stage has been previously obtained, a0 to y3 are within 5 pass transistor stages, and b0 to y3 are 3 pass transistor stages. It is possible to calculate the number-of-stages constraint within.

In step 15, the order of the input variables is determined in consideration of the restriction on the number of stages of each input obtained as a result of step 14. The pass transistor logic design method according to the present invention is characterized in that the BDD structure is reflected in the final circuit structure. Therefore, the number of stages between the input and output of the generated circuit is determined by the order of the input variables in the Shannon expansion. It is possible to adjust.

In the present embodiment, since no delay constraint is imposed on inputs other than a0 and b0, the constraint on the number of stages of a0 and b0 is satisfied, and the method described in the above “BDD processing technique on computer” is used. Is used to determine an input variable.

FIG. 15 shows the input variable order determined in this step. As is clear from the logical expression shown in FIG.
And b3, a2 and b2, a1 and b1, and a0 and b0 appear as a pair in the logical expression, and have local computability. In addition, since the power to control the output is strong in the order described above, basically follow this order. However, since a0 and b0 are limited by the number of stages, b0 is set to the third position and a0 is set to the fourth position in consideration of this. ing.

In step 16, as in step 5 of the first embodiment, the logic circuit is Shannon-expanded according to the variable order determined in step 15 to generate a BDD. FIG.
Shows the generated BDD.

At step 17, similarly to step 6 of the first embodiment, the BDD generated at step 16 is converted into a pass transistor logic circuit. FIG. 17 shows the generated pass transistor logic circuit 18.

FIG. 17 shows that the number of pass transistor stages from the input a0 to the output y3 is four, and the number of pass transistor stages from the input b0 to the output y3 is three. The circuit delay cannot be accurately evaluated until after the layout design is completed from the technology-independent logic design step to the technology-dependent logic design step according to the present invention. By incorporating a sufficient design margin in step 14 for calculating the number of logic stages, it is possible to satisfy the given delay time constraint.

On the other hand, according to the result shown in FIG. 13 corresponding to the case where the input variable order of Shannon expansion is determined without considering the delay constraint, the number of pass transistor stages from the inputs a0 and b0 to the output y3 is seven. In consideration of the fact that the average delay time per stage is 0.4 ns, the delay constraint is not satisfied, and there is a high possibility that the circuit is not actually usable.

(Embodiment 3) FIG. 3 is a process flowchart showing a process flow of a pass transistor logic design method according to the present invention. This embodiment is originally effective for a large-scale circuit that cannot be optimally converted to BDD as a whole circuit. However, for the sake of simplicity, FIG. 5 shows the same as in the first and second embodiments. A description will be given based on the logical specifications shown.

Step 2 for generating a logic circuit using normal gates is the same as that in the first embodiment, and a description thereof will not be repeated.

At step 23, the logic redundancy included in the circuit is removed by applying a logic optimization process to the logic circuit generated at step 2.

The reason for performing the logic optimization processing in the present embodiment is that, in the present embodiment, the logic circuit is divided and each partial circuit is independently converted into a pass transistor circuit. This is because if exists, it remains until the end.

In the conventional method of converting the whole circuit into BDD, this step is not performed because the converted BDD does not depend on the structure of the original logic circuit (it is uniquely determined by the input order in logic and Shannon expansion). is necessary.

The logic circuit shown in FIG. 6 is a logic circuit generated by performing steps 2 and 23 based on the logic specification 1. (Embodiments 1 and 2)
, The logic circuit of FIG. 6 is a result of performing a logic optimization process. In step 24), the generated logic circuit is divided into a plurality of sub-circuits.

Here, the fan-out 2 which has been often used in the technology mapping process of allocating cells to technology-independent logic in the logic synthesis process has been conventionally used.
The technique of dividing the circuit by the internal signal (signal i in FIG. 6) is used.

The number of inputs of each of the divided sub-circuits is checked. If the number is larger than a predetermined value, the circuit is further divided, and the division is repeated until the number of inputs falls within the limit value. As the limit value, the number of inputs capable of optimizing the order of input signals in Shannon expansion processing is used.

In the logic circuit shown in FIG. 6, since the number of inputs is 8, it is not necessary to divide the circuit in principle. However, for the sake of explanation, the circuit is divided into two by the signal i.

At this time, the logical functions of the two divided sub-circuits are expressed by (Equation 12) and (Equation 13).

[0098]

[Equation 12] i = a ((a0 & b0 & (a1 | b1)) | (a1 & b1))

[0099]

Y3 = (((∧i | b2) & a2) | (∧i & b2)) @ a3 @ b3 In step 25, for example, "minimizing a binary decision diagram expressing a logical function" The optimal input order is determined by using a technique such as that described in Science Technique COMP 91-15 p27). Since the number of inputs to each sub-circuit is limited in advance by the circuit division in step 24, the order of input variables can be determined by the above method. Here, it is assumed that the input order is determined as shown in FIG.

In step 26, according to the input order determined in step 25, each sub-circuit is Shannon-expanded and B
Convert to DD. Since this step basically repeats the processing of step 5 in the first embodiment for each sub-circuit, the description is omitted here.

A plurality of BDs generated in this step
Since a logical expression in which D is connected in a network form is no longer a BDD as a whole, it cannot be applied to general BDD applications. However, as in the present invention, a BDD is directly connected to a logic circuit. Such a method can be used effectively for the purpose of reducing the total number of BDD nodes.

FIG. 19 shows the generated BDD.

In step 27, as in step 6 of the first embodiment, the BDD generated in step 26 is converted to a pass transistor logic circuit. FIG. 20 shows the generated pass transistor logic circuit.

(Embodiment 4) FIG. 21 is a processing flow chart showing a processing flow of a pass transistor logic design method according to the present invention. The logic specification 1 of this embodiment, the step 2 of generating a logic circuit using normal gates, and the step 3 of evaluating the signal transition probability of each input are the same as those of the first embodiment, and therefore, the description is omitted here. I do. It is assumed that the signal transition probability shown in FIG. 8 is also obtained in the present embodiment.

FIG. 24 shows a delay time constraint 210 according to the present embodiment. Here, it is described that the delay from the input a3 to the output y3 must be 1.2 ns or less, and the delay from the input b3 to the output y3 must be 1.7 ns or less.

Step 14 for calculating the constraint on the number of pass transistor stages between the input and the output is the same as that in the second embodiment, so a detailed description is omitted.
In the case of an average delay of 0.4 ns per stage, a3 to y3 are within 3 stages of the pass transistor and b3 to
The delay up to y3 can be calculated to be within four stages.

In step 211, the input variables are ordered in consideration of the signal transition probability of each input obtained as a result of step 3 and the number of pass transistors between inputs and outputs obtained as a result of step 14.

In the present embodiment, it is essential to generate a circuit that satisfies the delay constraint, and aims at minimizing the power consumption. Therefore, the circuit satisfies the constraint on the number of pass transistor stages related to a3 and b3. Then, the input signals are ordered in descending order of signal transition probability. in this way,
The pass transistor stage number constraint has a higher priority than the signal transition probability. FIG. 25 shows an ordered list of input signals.

Step 5 of generating a BDD by Shannon expansion of a logic circuit and step 6 of converting the BDD into a pass transistor logic circuit are the same as those in the first embodiment, and thus description thereof will be omitted.

As described above, by using the design method of this embodiment, it is possible to generate a pass transistor circuit with low power consumption while satisfying the given delay constraint.

(Embodiment 5) FIG. 22 is a processing flow chart showing a processing flow of a pass transistor logic design method according to the present invention. The logic specification 1 of this embodiment and the step 2, the logic optimization step 23, and the circuit division step 24 for generating a logic circuit using normal gates are the same as those in the third embodiment, and therefore the description thereof is omitted here. .

In step 221, the signal transition probability relating to the input signal of each sub-circuit divided in step 24 is evaluated. This can also be performed by using logic simulation as in step 3 of the first embodiment.

In step 222, the order of the input variables is determined for each sub-circuit from the one with the largest signal transition probability to the one with the smallest signal transition probability. This step can be performed in the same manner as step 4 of the first embodiment.

In this embodiment, the order of input variables is determined based on signal transition probabilities for the purpose of reducing power consumption. However, in an actual circuit design, both reduction in power consumption and minimization of the circuit scale are compatible. Often not. In such a case, it is necessary to order the input signals in consideration of the trade-off between the two, and the present invention includes such a case.

Step 26 for generating BDD by Shannon-expanding each sub-circuit of this embodiment and B
Step 2 of converting DD into a pass transistor logic circuit
7 is the same as that of the third embodiment, and the description is omitted.

By using the design method of this embodiment as described above, a pass transistor circuit with low power consumption can be generated even for a large-scale logic circuit.

(Embodiment 6) FIG. 23 is a process flowchart showing a process flow of a pass transistor logic design method according to the present invention. The logic specification 1 of this embodiment and the step 2, the logic optimization step 23, and the circuit division step 24 for generating a logic circuit using normal gates are the same as those in the third embodiment, and therefore the description thereof is omitted here. .

It is assumed that the same delay time constraint 13 as that of the second embodiment shown in FIG. 14 is given.

In step 231, the delay time constraint 13
, A constraint on the number of pass transistor stages between the input and output of each sub-circuit divided in step 24 is calculated. Here, a method is used in which the number-of-inputs / outputs number constraint in the entire circuit is calculated in the same manner as in step 14 of the second embodiment, and the obtained number-of-steps constraint is then distributed to each sub-circuit.

As shown in FIG. 15, in the entire circuit, the number of stages is restricted such that a0 to y3 are within 5 stages and b0 to y3 are within 3 stages. When this is distributed so as to balance the delay constraint among the sub-circuits, in the sub-circuit corresponding to (Equation 12), a0 to i are within three stages, b0 to i are within one stage, and one (Equation 13) corresponds. In such a sub-circuit, the number of stages is restricted from i to y3 within two stages.

There are various methods for calculating the number of stages between the input and output of each sub-circuit from the delay time constraint, in addition to the above-described methods. The present invention includes such a method. I have.

In step 232, the order of the input signals is determined for each sub-circuit in consideration of the above-mentioned stage number constraint in the same manner as in step 15 of the second embodiment. FIG. 26 shows the input order obtained as a result of this step.

Step 26 of generating BDD by Shannon-expanding each sub-circuit of this embodiment
Step 2 of converting DD into a pass transistor logic circuit
7 is the same as that of the third embodiment, and the description is omitted here.

By combining the fifth embodiment (FIG. 22) and the sixth embodiment (FIG. 23), the order of input signals to each sub-circuit is determined based on the signal transition probability and the number of stages. You may.

[0125]

As described above, according to the present invention, it is possible to synthesize a pass transistor circuit having the following features from given logical specifications.

(1) Since the number of pass transistor stages between the input and the output is smaller as the input has a higher signal transition probability, a signal with a higher transition probability does not propagate for a longer time, the sum of the transition probabilities is smaller as a whole circuit, and the power consumption is lower. Be transformed into

(2) The number of pass transistor stages between the input and output to which the delay time constraint is given is limited based on the delay constraint value. By imposing a delay constraint between the input and output serving as a critical path, a high-speed operation of the circuit is realized.

(3) A practical circuit size can be realized even for a circuit which cannot be optimized by the conventional design method due to a large number of inputs and becomes unnecessarily large.

[Brief description of the drawings]

FIG. 1 is a process flowchart of a pass transistor logic design method according to a first embodiment of the present invention.

FIG. 2 is a process flowchart of a pass transistor logic design method according to a second embodiment of the present invention.

FIG. 3 is a processing flowchart of a pass transistor logic design method according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a functional description for describing a pass transistor logic design method of the present invention.

FIG. 5 is a diagram showing a logical expression for explaining a pass transistor logical design method of the present invention.

FIG. 6 is a logic circuit diagram generated from a logical expression according to the first embodiment of the present invention.

FIG. 7 is a diagram showing test vectors necessary for evaluating a signal transition probability in the first embodiment of the present invention.

FIG. 8 is a diagram showing a result of ordering inputs based on signal transition probabilities in the first embodiment of the present invention.

FIG. 9 is a diagram showing a BDD generated from a logic circuit in the first embodiment of the present invention.

FIG. 10 is a diagram showing conversion from BDD to a pass transistor logic circuit in the first embodiment of the present invention.

FIG. 11 is a diagram illustrating a pass transistor logic circuit converted from BDD in the first embodiment of the present invention.

FIG. 12 is a diagram illustrating a BDD generated from a logic circuit in an input order determined using a conventional method.

FIG. 13 is a diagram illustrating a pass transistor logic circuit converted from a BDD generated using a conventional method.

FIG. 14 is a diagram illustrating an example of a delay constraint according to the second embodiment of the present invention.

FIG. 15 is a diagram showing a result of ordering inputs in consideration of a pass transistor stage number restriction in the second embodiment of the present invention.

FIG. 16 is a diagram showing a BDD generated from a logic circuit in the second embodiment of the present invention.

FIG. 17 is a diagram illustrating a pass transistor logic circuit converted from BDD in the second embodiment of the present invention.

FIG. 18 is a diagram illustrating a result of ordering inputs such that a BDD size is minimized for each sub-circuit in the third embodiment of the present invention.

FIG. 19 is a diagram showing a BDD generated from a logic circuit in the third embodiment of the present invention.

FIG. 20 is a diagram illustrating a pass transistor logic circuit converted from BDD in the third embodiment of the present invention.

FIG. 21 is a processing flowchart of a pass transistor logic design method according to a fourth embodiment of the present invention.

FIG. 22 is a processing flowchart of a pass transistor logic design method according to the fifth embodiment of the present invention.

FIG. 23 is a processing flowchart of a pass transistor logic design method according to the sixth embodiment of the present invention.

FIG. 24 is a diagram illustrating an example of a delay constraint according to the fourth embodiment of the present invention.

FIG. 25 is a diagram illustrating a result obtained by ordering inputs in consideration of a pass transistor stage number constraint and a signal transition probability in the fourth embodiment of the present invention.

FIG. 26 is a diagram illustrating a result of ordering inputs in consideration of a restriction on the number of pass transistor stages for each sub-circuit in the sixth embodiment of the present invention.

[Explanation of symbols]

 1 Logic specification 2 Generate logic circuit with normal gate 3 Evaluate signal transition probability of each input 4 Order each input by signal transition probability 5 Generate BDD by Shannon expansion of logic circuit 6 Convert BDD to pass transistor logic circuit 7 pass transistor logic circuit

Claims (8)

(57) [Claims] 1. Based on a logical specification of a given circuit,
A method for designing a pass transistor logic circuit, comprising: generating a logic circuit including a logic gate based on the logic specification; evaluating a signal transition probability of each input signal of the logic circuit; Ordering the signal transition probabilities from high to low, and applying the Shannon expansion process to the logic circuit in order from the signal transition probabilities of the input signals in descending order. Generating a corresponding binary decision diagram, and generating a technology-independent pass transistor logic circuit by replacing each node of the binary decision diagram with a two-input selector circuit comprising pass transistors; By reducing the number of logic stages between the input signal and the output signal with high transition probability, Pass transistor logic design wherein the reducing the power consumption of the circuit. 2. The number of stages allowed for the pass transistor logic circuit based on a delay time constraint defining a delay time allowed between input and output signals of the given circuit and an average delay time of the pass transistor logic circuit. The pass transistor logic design method according to claim 1, further comprising a step of calculating a number-of-stages constraint defining: the input signal of the logic circuit is ordered in consideration of the number-of-stages constraint and the signal transition probability. . 3. The pass transistor logic design method according to claim 2, wherein said stage number constraint has a higher priority than said signal transition probability. 4. Based on a given circuit logic specification,
A method for designing a pass transistor logic circuit, comprising: generating a logic circuit including a logic gate based on the logic specification; and a delay defining an allowable delay time between input and output signals of the given circuit. Calculating, based on the time constraint and the average delay time of the pass transistor logic circuit, a stage number constraint that defines the number of stages allowed in the pass transistor logic circuit; Determining the order of the input signals, and applying a Shannon expansion process to the logic circuit according to the order of the input signals, thereby generating a binary decision diagram corresponding to the logic circuit; By replacing each node of the binary decision diagram with a two-input selector circuit using pass transistors, Such include the step of generating a pass-transistor logic circuit, by limiting the pass transistor stages between the input signal and the output signal the delay time constraints given, a plurality
Take steps to generate and compare pass transistor circuits
A pass transistor logic design method , wherein a generated circuit satisfies a given delay time constraint without causing any problem. 5. Based on a given circuit logic specification,
A method of designing a pass transistor logic circuit, comprising: generating a logic circuit including a logic gate based on the logic specification; performing a logic optimization process on the logic circuit to delete a redundant circuit; Dividing the optimized logic circuit into a plurality of sub-circuits in consideration of the number of input signals of each of the plurality of sub-circuits, and minimizing a generated binary decision diagram. Determining an optimal order of input signals for Shannon expansion for each of the plurality of sub-circuits; and applying Shannon expansion processing according to the order of the input signals for each of the plurality of sub-circuits. Generating a binary decision diagram corresponding to a logic circuit; and for each of the plurality of sub-circuits, Generating a technology-independent pass-transistor logic circuit by replacing each node of the sub-circuit with a two-input selector circuit using pass transistors, and limiting the number of input signals of individual sub-circuits. A pass transistor logic design method characterized in that an order can be determined and a generated circuit is minimized. 6. The method of claim 1, further comprising evaluating a signal transition probability of each of the input signals of the sub-circuit, wherein an order of the input signals of the sub-circuit is determined based on the signal transition probabilities. Item 6. The pass transistor logic design method according to item 5. 7. The number of stages allowed for the pass transistor logic circuit based on a delay time constraint defining a delay time allowed between input and output signals of the given circuit and an average delay time of the pass transistor logic circuit. The pass transistor logic design method according to claim 5, further comprising: calculating a number-of-stages constraint that defines the following. The order of the input signals of the sub-circuit is determined based on the number-of-stages constraint. 8. The number of stages allowed in the pass transistor logic circuit based on a delay time constraint defining a delay time allowed between input and output signals of the given circuit and an average delay time of the pass transistor logic circuit. 7. The pass transistor logic according to claim 6, further comprising calculating a number-of-stages constraint defining: the order of the input signals of the sub-circuit is determined based on the number-of-stages constraint and the signal transition probability. Design method.