JPH0997281A - Path transistor logic design method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method designing a path transistor logic circuit which is low in power consumption and high in speed, and small in circuit scale. SOLUTION: This method is a path transistor logic design method having a step 2 generating the logic circuit composed of normal logic gates from a logic specification, a step 3 evaluating the signal transition probability of each input signal of a logic circuit, a step 4 ordering input signals from higher signal transition probability signal to lower probability sygnal, a step 5 generating the bisecting determination graph corresponding to the logic circuit by applying a shannon development processing in order of the higher signal transition probabilities of the input signals for the logic circuit, and a step 6 generating a technologically independent path transistor logic circuit by replacing each node of the bisecting determination graph by the two-input selector circuit by a path transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a design automation technique for efficiently designing a circuit such as an LSI, and particularly, at a stage independent of process technology for generating a pass transistor logic circuit based on a functional description of the circuit. It relates to a logic design method.

[0002]

2. Description of the Related Art Recently, pass-transistor logic, which has the features of high speed, low power consumption, and small area, has attracted attention as compared with the CMOS logic which has been widely used in the past.

On the other hand, in order to deal with the problem of an increase in the design man-hours of a large-scale LSI, a hardware description language is used to functionally describe the LSI and a logic circuit is automatically designed using an automatic logic synthesizer. The method has become popular. The automatic logic synthesis technology from the function description is the key technology of this top-down design method, and research and development have been vigorously carried out conventionally.

Now that the top-down design method has become widespread, even if the above-mentioned pass transistor logic is CM.
Even if it has better characteristics than the OS logic, if it cannot be automatically designed and must be carefully designed manually, it cannot be widely used as a logic design technique. It is thought that it will be limited to the special circuit of.

Therefore, it is indispensable to establish an automatic design technique for improving the performance and cost of the LSI by utilizing the excellent characteristics of the pass transistor logic.

An example of a conventional pass transistor logic design method is, for example, "Lean Integration: Achieving a Qu
antum Leap in Performance and Cost of Logic LSIs ''
(IEEE 1994 Custom Integrated Circuits Conferenc
e) can be mentioned.

The design flow described in the above document will be described below.

First, a binary decision graph is generated from a logical specification expressed in a hardware description language or the like.

Next, the nodes in the graph are replaced with pass transistors to form a transistor network.

Next, a buffer for the purpose of recovering the potential level and amplifying the current is inserted at an appropriate location inside the network.

Next, a prepared lean cell is assigned to the generated circuit and a netlist is output.

In the above processing flow, the first two steps are technology-independent processing that does not depend on a specific cell library, and the latter two steps are technology-dependent processing.

[0013]

The present invention is intended to solve the problems associated with the technology-independent processing, among the above-mentioned conventional methods.

Examples of such problems include the following.

(1) Reduction of power consumption With the progress of semiconductor integrated circuit technology, the number of elements that can be integrated on one chip exceeds several million Tr, and as a result, heat generation of LSI has become a serious problem. In addition, as the market for portable devices expands and the environment changes, reducing the power consumption of LSIs has become an important issue.

This also applies to the pass transistor logic, which is characterized by lower power consumption than CMOS.

(2) Speedup It is said that the pass transistor logic is faster than the CMOS logic, but it is often the delay of a specific critical path that determines the actual circuit performance. Even if many paths are faster than CMOS circuits on average,
If the delay of these critical paths that determine performance is large, the performance of the circuit will be low.

(3) Circuit Scale Reduction In the conventional design method in which each node of the generated BDD is replaced with a pass transistor, the finally generated circuit scale greatly depends on the size of the BDD. On the other hand, it is known that the BDD size depends on the input signal order in the Shannon expansion process. Therefore, in order to reduce the circuit scale, it is necessary to optimize the input signal order, but this is a difficult problem to decide, and "minimization of a binary decision graph expressing a logical function" Report COMP91-15 p2
As described in 7), at present, no effective method is known when the number of inputs exceeds about 17.

In a realistic circuit, the number of input signals is 100
Therefore, it is impossible to optimize the input signal sequence of such a circuit. As a result, the size of the BDD becomes larger than the optimum size, and the final circuit scale also increases.

Further, there is no guarantee that the method of converting the entire circuit into an integrated BDD will generate a minimum circuit.

An object of the present invention is to improve the processing for generating a BDD from a logic specification, thereby realizing low power consumption, high speed, and reduction in circuit scale of a circuit which was difficult with the conventional pass transistor logic design method. To do.

[0022]

The method of the present invention is a method of designing a pass transistor logic circuit based on a given logic specification of a circuit, the logic circuit including a logic gate based on the logic specification. A step of evaluating the signal transition probability of each input signal of the logic circuit, a step of ordering the input signals from one having a high signal transition probability to one having a low signal transition probability, and for the logic circuit, A step of generating a binary decision graph corresponding to the logic circuit by applying Shannon expansion processing in order from the input signal having the highest signal transition probability, and each node of the binary decision graph is formed by a pass transistor. Generating a technology-independent pass transistor logic circuit by replacing it with a two-input selector circuit. By reducing the number of logic stages between the high transition probability input and output signals, characterized in that to reduce the power consumption of the generated circuit. This achieves the above object.

The method is based on a delay time constraint defining a delay time allowed between input and output signals of the given circuit and an average delay time of the pass transistor logic circuit.
The method may further include calculating a stage number constraint defining a number of stages allowed in the pass transistor logic circuit, wherein the input signals of the logic circuit may be ordered in consideration of the stage number constraint and the signal transition probability. Good.

The stage number constraint may have a higher priority than the signal transition probability.

Another method of the present invention is a method of designing a pass transistor logic circuit based on a given logic specification of a circuit, wherein a step of generating a logic circuit including a logic gate based on the logic specification. And the number of stages allowed in the pass transistor logic circuit based on the delay time constraint that defines the delay time allowed between the input and output signals of the given circuit and the average delay time of the pass transistor logic circuit. A step of calculating a stage number constraint, a step of determining an optimal order of input signals for Shannon expansion in consideration of the stage number constraint, and a Shannon expansion process for the logic circuit according to the order of the input signals. Applying a step of generating a binary decision graph corresponding to the logic circuit, and a path transition of each node of the binary decision graph. Generating a technology-independent pass-transistor logic circuit by replacing the input-output circuit with a delay-time-constrained input signal and an output signal by limiting the number of pass-transistor stages to each other. Is characterized in that the generated circuit satisfies the given delay time constraint. This achieves the above object.

Another method of the present invention is a method of designing a pass transistor logic circuit based on a given logic specification of a circuit, wherein a step of generating a logic circuit including a logic gate based on the logic specification. And performing a logic optimization process on the logic circuit to remove the redundant circuit,
For dividing the optimized logic circuit into a plurality of sub-circuits in consideration of the number of input signals of each of the divided sub-circuits, and for minimizing a generated BDD. , A step of determining an optimal input signal order for Shannon expansion for each of the plurality of sub-circuits, and applying Shannon expansion processing according to the order of the input signals for each of the plurality of sub-circuits, A step of generating a binary decision graph corresponding to the logic circuit, and a technology-independent path by replacing each node of the binary decision graph with a 2-input selector circuit using a pass transistor for each of the plurality of sub-circuits. Limiting the number of input signals of the individual subcircuits, including the step of generating a transistor logic circuit. To allow determination of optimal input signal sequence by, characterized by minimizing the circuit generated. This achieves the above object.

The method further comprises evaluating a signal transition probability of each of the input signals of the sub-circuit, wherein the order of the input signals of the sub-circuit is determined based on the signal transition probabilities. Good.

The method is based on a delay time constraint which defines a delay time allowed between input and output signals of the given circuit and an average delay time of the pass transistor logic circuit.
The method may further include calculating a stage number constraint that defines the number of stages allowed in the pass transistor logic circuit, and the order of the input signals of the sub-circuits may be determined based on the stage number constraint.

The method is based on a delay time constraint which defines a delay time allowed between input and output signals of the given circuit and an average delay time of the pass transistor logic circuit.
The method further includes the step of calculating a stage number constraint that defines the number of stages allowed in the pass transistor logic circuit, wherein the order of the input signals of the sub-circuit is determined based on the stage number constraint and the signal transition probability. Good.

The operation will be described below.

According to the present invention, by adopting the above configuration, in the process of generating the BDD corresponding to the given logical specifications, the input signals having the highest transition frequency are subjected to Shannon expansion first, and the ones having the low transition frequency. Will be expanded to Shannon later.

In the BDD, the node corresponding to the input signal which has been Shannon expanded earlier becomes closer to the output side. Therefore, after converting each node of the BDD to the pass transistor, the higher the transition frequency, the more the number of logic stages between the input and the output. Becomes smaller.

Since an internal signal included in a path between an input signal and an output with a high transition frequency also frequently has a high transition frequency, by reducing the number of logical stages of such a path,
The sum of transition frequencies of all signals included in the circuit can be reduced.

In addition, since BDDs often spread from roots to branches like other graphs, the number of pass transistors connected to inputs having a high transition probability is small, and in that sense, the entire transition frequency is high. The sum of can be reduced.
As a result, the power consumption of the circuit can be reduced.

Further, in the present invention, the pass transistor stage number constraint corresponding to the delay time constraint is calculated from the given delay time constraint between the input and output and the average delay time of the pass transistor circuit obtained in advance.

In the designing method of the present invention in which each node of the BDD is replaced with a pass transistor, the input signal order of Shannon expansion when the BDD is generated is directly related to the number of pass transistor stages between the input and the output. The stage number constraint can be replaced with an input signal order constraint.

After obtaining the corresponding pass transistor stage number constraints for all delay time constraints, the Shannon expansion order of the input signals satisfying these constraints is determined. The BDD is generated by Shannon expansion according to the order thus obtained and converted into a pass transistor circuit. The result satisfies the constraint on the number of pass transistor stages. Careful design in subsequent technology-dependent processing allows the design of circuits that meet given delay constraints.

Further, in the present invention, considering the difficulty of determining the optimum input signal order for minimizing the size of the BDD,
First, at the stage of converting from the logic specification to a normal logic circuit,
It is divided into a plurality of sub circuits. Here, carefully divide the number of inputs of each sub-circuit so that it is less than or equal to a predetermined number.

In such a design method, the entire circuit does not become one BDD, and the redundancy of logic cannot be removed between a plurality of BDDs. In advance, logic optimization processing is applied.

As described above, in the sub-circuit with the limited number of inputs, the input variable order of Shannon expansion can be optimized, and the size of the BDD corresponding to each sub-circuit can be minimized.

On the other hand, when converting the entire circuit into one BDD, it is highly possible that the optimum input variable order cannot be found and the size of the BDD is not minimized. As a result, the scale of the final pass transistor circuit also becomes smaller.

Further, depending on the circuit, the circuit scale is smaller when converted to a network composed of a plurality of BDDs and then converted to a pass transistor logic circuit than to generate a pass transistor logic circuit after conversion to an integrated BDD. In many cases

[0043]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a processing flow chart showing a processing flow of a pass transistor logic design method according to the present invention.

In the figure, a logic specification 1 describes the logic specification of a circuit to be designed in a format such as a hardware description language or a logical expression.

FIG. 4 shows the hardware description language verilo.
It is an example of a functional description using gHDL. This describes the operation of a 4-bit adder that outputs to y the result of adding the two 4-bit input values a and b. This embodiment is a combinational circuit, and can be directly processed by the designing method of the present invention using BDD. However, since the sequential circuit can also be divided into a combinational circuit and a flip-flop, the designing method of the present invention can be applied to the combinational circuit portion.

FIG. 5 is an example of a logical expression expressing the most significant bit y3 of the output y of the 4-bit adder. here"
&"Is a logical product," | "is a logical sum, and" @ "is an exclusive logical sum operator. A logical expression is also an example of a logical specification like the functional description above. It may be expressed in other formats.

In step 2, the hardware description language (H
A logic circuit composed of normal gates is generated based on a logic specification such as a functional description in DL) or a logic formula. In this step, there are a method of manually designing a logic and a method of using a logic synthesis tool.
In this embodiment, the latter is adopted.

FIG. 6 shows step 2 from the logical expression shown in FIG.
It is an example of a logic circuit generated by the process of. Here, the circuit is represented by a network of logic gates such as AND and OR. In this embodiment, the one-output logic circuit will be described as an example, but a multi-output logic circuit can be basically handled in the same way.

In step 3, the signal transition probability of each input of the logic circuit generated in step 2 is evaluated. Normal,
Most logic circuits are designed in a synchronous manner that operates in synchronization with a clock. In this case, the values of all the signals in the circuit are determined in synchronization with the clock, the value changes from the previous cycle in one clock cycle, and the value of the previous cycle is held in another clock cycle. The signal transition probability is defined as the number of clock cycles whose value changes divided by the total number of clock cycles.

The power consumption of each signal in the logic circuit is given by (Equation 1). Since there is a relationship of (Equation 2), it can be seen that the power consumption of each signal is proportional to the signal transition probability. Since the power consumption of the entire circuit is the sum of the power consumption of each signal of the circuit, reducing the signal transition probability of each signal of the circuit is an issue in reducing the power consumption of the circuit.

[0052]

[Equation 1] P = (1/2) · C · Vdd ² · SWR C: signal load capacitance, Vdd: circuit power supply voltage, SW
R: Number of transitions of signal per unit time

[0053]

## EQU00002 ## SWR = STR / Tcycle STR: signal transition probability, Tcycle: clock cycle time When the logic circuit is the entire circuit to be designed, its input is an external input of the entire circuit and its signal transition The probability is determined by the specifications of the signal input to the circuit. However, a normal circuit is designed hierarchically, and a logical design is often made for each sub-circuit. In this case, the signal transition probability of the input of the sub circuit is roughly determined by the specifications of the signal given to the external input of the entire circuit and the logic of the peripheral sub circuits connected to the sub circuit. There are several methods for evaluating this signal transition probability, but in this embodiment, it is evaluated by logic simulation.

FIG. 7 shows an example of a test vector given to an input signal in the logic simulation. Each row is one vector and describes the signal given to the input in a certain clock cycle. Each number in the vector represents the value of the corresponding input signal by position. The first line is the vector of the first clock cycle, the second line is the vector of the second clock cycle, and so on.

When the input value of each clock cycle is determined,
Then, a logical operation is performed to determine each internal signal value of the circuit in each clock cycle. By comparing the signal value of each clock cycle with the value of the immediately preceding cycle, it is determined whether or not the signal has changed, so the signal transition probability can be calculated. Since the input signal of the sub circuit is also included in this internal signal, the signal transition probability of the input of the sub circuit is obtained by this.

In order to evaluate the signal transition probability with high accuracy by the method based on this logic simulation, it is necessary to prepare an appropriate test vector that accurately reflects the situation in which it is actually used.

In step 4, the input signals are ordered in descending order of the signal transition probability of each input evaluated in step 3. FIG. 8 shows an ordered list of input signals.

In step 5, Shannon expansion is performed on the logic circuit generated in step 2 in the order determined in step 4 to generate a binary decision graph (BDD).

The Shannon expansion of the logical function f by the input variable p is a logical function in which the input p in f is fixed to 1.
[p = 1], the logical function with the input p at f fixed to 0 is f
When represented by [p = 0], the left side is converted to the right side by utilizing the fact that the equation shown in (Equation 3) holds. It can be seen that the logic on the left side is a binary logic of f = f [p = 1] when p is 1 and f = f [p = 0] when p is 0. The logic circuit generated in step 2 corresponds to the logic function of (Equation 4). According to the order, when Shannon expansion of y3 is performed with a0, (Equation 5) and (Equation 6) are obtained, which is expanded to (Equation 7).

[0060]

## EQU3 ## f = p & f [p = 1] | ^ p & f [p = 0] "&": logical product, "|": logical sum, "^": logical inversion

[0061]

[Expression 4] y3 = ((a0 & b0 & (a1 | b1) | (a1 & b1)) & b2 | (a0 & b0 &
(a1 | b1) | (a1 & b1) | b2) & a2) @ a3 @ b3

[0062]

[Formula 5] y3 [a0 = 1] = ((b0 & (a1 | b1) | (a1 & b1)) & b2 | (b0 &
(a1 | b1) | (a1 & b1) | b2) & a2) @ a3 @ b3

[0063]

[Equation 6] y3 [a0 = 0] = ((a1 & b1 & b2) | ((a1 & b1) | b2) & a2)
@ a3 @ b3

[0064]

[Equation 7] y3 = a0 & y3 [a0 = 1] | ^ a0 & y3 [a0 = 0] Further, Shannon expansion with b0 results in (Equation 8). On the other hand, y3 [a0 = 0] does not include b0, so Shannon expansion is not necessary. Therefore, it is developed as (Equation 9).

[0065]

[Equation 8] y3 [a0 = 1] [b0 = 1] = ((a1 | b1 | (a1 & b1)) & b2 | (a1 |
b1 | (a1 & b1) | b2) & a2) @ a3 @ b3 y3 [a0 = 1] [b0 = 0] = ((a1 & b1 & b2) | ((a1 & b1) | b2) & a2) @
a3 @ b3

[0066]

[Equation 9] y3 = a0 & b0 & y3 [a0 = 1] [b0 = 1] | a0 & ^ b0 &
y3 [a0 = 1] [b0 = 0] | ^ a0 & y3 [a0 = 0] Further, Shannon expansion is executed for a1, b1, a2, b2, a3 and b3.

FIG. 9 shows the BDD generated in this way. The non-terminal node (round node) of the BDD corresponds to one Shannon-expanded logical function with the input variables described in the node. The edge extending upward from each node is the output edge, which conveys the logical function it represents to the node above. On the other hand, the edge extending downward from each node includes one written as 1 (1 edge) and one written as 0 (0 edge). The former is connected to a node corresponding to a logical function with an input variable fixed to 1 in Shannon expansion, and the latter is connected to a node corresponding to a logical function with an input variable fixed to 0.

That is, the uppermost node 31 corresponds to the output y3 of the logic circuit. The node 32 corresponds to a logical function in which the input variable a0 is fixed to 1 in the logical function of y3. In addition, there are some terminal nodes (square nodes) described as 1 and ones described as 0, which correspond to the logical constants 1 and 0, respectively. Since the 0 edge is connected to the constant 1 and the 1 edge is connected to the constant 0 in the node 35, it can be seen that the corresponding logical function is (Equation 10). Similarly, the node 36 corresponds to the logical function b3. The logical function corresponding to the node 33 is (Equation 11).

[0069]

[Equation 10] b3 & 0 | ^ b3 & 1 = ^ b3

[0070]

A3 & ^ b3 | ^ a3 & b3 = a3 @ b3 In step 6, the BDD generated in step 5 is converted into a pass transistor logic circuit. As described above, each node of the BDD is a binary logic, while the pass transistor logic is based on a 2-input selector.
A corresponding pass transistor circuit can be obtained by applying the conversion shown in FIG. 10 to each node of the BDD.

FIG. 11 shows a pass transistor logic circuit converted from the BDD of FIG. From FIG. 11, the input such as a0 or b0 having a higher signal transition probability has a smaller number of pass transistor stages up to the output y3, and conversely, the input having a lower signal transition probability such as a3 or b3 has a larger number of pass transistor stages up to the output. It can be seen that the power consumption is reduced.

Actually, many pass transistors cannot be connected in series as shown in FIG. 11, and it is necessary to insert a buffer for potential recovery and current amplification at an appropriate position. It is not a technology-independent logic design step related to the above, but a technology-dependent logic design step that follows. Therefore, the number of pass transistor stages between input and output in the final pass transistor logic circuit and the number of transitions of the internal signal per unit time cannot be estimated at this stage, but the relative distance from each input to the output is It is also saved in the circuit.

FIG. 12 shows "BDD processing technique on computer" (information processing vol.34 No.5 p59) without ordering the input signals by the signal transition probability as in the present embodiment.
As described in 3), a method of Shannon expansion of inputs with strong power to control output first and inputs with local computability in order of closeness (BDD generated in this way) It is reported that the scale of is smaller.) Is taken, and the logic circuit generated in step 2 is converted to BDD.

FIG. 13 shows a pass transistor logic circuit converted from the BDD of FIG. 13 that the signal transition probability is higher than the result (FIG. 11) according to the present embodiment (FIG. 11) a0
It can be seen that the number of pass transistor stages from the input such as or b0 to the output y3 is large. As previously mentioned,
Since the internal signal included in the path from the input to the output having a high signal transition probability has a high transition frequency, the result in FIG. 13 consumes more power than the result according to the present embodiment.

In fact, “Technology Decomposition and M
apping Targeting Low Power Dissipation '' (30th IEEE
As a result of estimating the sum of signal transition probabilities of all signals included in both circuits by the method described in Design Automation Conference p68), the result of this embodiment is 11.4, while the result of FIG. The result is 16.6, which is a reduction of about 30%, and it can be seen that the method of the present embodiment has a great effect in reducing power consumption.

(Embodiment 2) FIG. 2 is a process flow chart showing a process flow of a pass transistor logic design method according to the present invention. Since the logic specification 1 of this embodiment and the step 2 of generating a logic circuit with a normal gate are the same as those of the first embodiment, their explanations are omitted here.

Normally, in the logic circuit design, it is necessary to satisfy the given logic specification 1. However, not only that, but the delay time constraint 13 that the circuit must satisfy is often given. In the combinational circuit design as in this embodiment, the delay time constraint is usually given by the maximum delay value from the input to the output as shown in FIG.

Here, the delay from the input a0 to the output y3 is 2.
It is stated that the delay from 0 ns or less and the input b0 to the output y3 must be 1.5 ns or less. No delay constraint is given to inputs other than a0 and b0. As the delay constraint, it is often given in the form of the maximum delay value from all inputs to all outputs, but for example, because a specific input signal is delayed from other input signals, the It is often done in an actual design to give a delay constraint to.

At step 14, the constraint on the number of pass transistor stages between input and output is calculated based on the given delay time constraint. For that purpose, it is necessary to previously obtain the average delay time per pass transistor by some method. Usually, these values vary depending on the characteristics of the circuit to be designed, so it is important to obtain highly reliable values by collecting statistics on as many circuits as possible.

If it is assumed that the average delay value per pass transistor is 0.4 ns, a0 to y3 are within 5 pass transistors, and b0 to y3 are 3 pass transistor. It is possible to calculate the step number constraint of within.

In step 15, the input variables are ordered in consideration of the constraint on the number of stages of each input obtained as a result of step 14. The pass transistor logic design method according to the present invention is characterized in that the BDD structure is reflected in the final circuit structure. Therefore, the number of stages between the input and output of the generated circuit is determined by the order of the input variables in the Shannon expansion. It is possible to adjust.

In this embodiment, since the input delay constraints other than a0 and b0 are not given, the method described in the above "BDD processing technique on a computer" is satisfied after the stage number constraints of a0 and b0 are satisfied. Shall be used to determine the input variables.

FIG. 15 shows the order of the input variables determined in this step. As is clear from the formula shown in FIG. 5, a3
And b3, a2 and b2, a1 and b1, a0 and b0 appear as a pair in the logical expression and have local computability, so the order is continued. Also, because the output control power is strong in the above order, basically this order is followed, but since a0 and b0 have a stage number constraint, consider that and bring b0 to the third and a0 to the fourth. ing.

In step 16, as in step 5 of the first embodiment, BDD is generated by Shannon expansion of the logic circuit in accordance with the variable order determined in step 15. FIG.
The BDD generated in FIG.

In step 17, the BDD generated in step 16 is converted into a pass transistor logic circuit as in step 6 of the first embodiment. FIG. 17 shows the generated pass transistor logic circuit 18.

It can be seen from FIG. 17 that the number of pass transistor stages from the input a0 to the output y3 is four, and the number of pass transistor stages from the input b0 to the output y3 is three. The delay of the circuit cannot be accurately evaluated until after the layout design is completed through the technology-independent logic design step and the technology-dependent logic design step according to the present invention. It is possible to satisfy the given delay time constraint by incorporating a sufficient design margin in the step 14 of calculating the number of logic stages.

On the other hand, in the result shown in FIG. 13 corresponding to the case where the input variable order of the Shannon expansion is determined without considering the delay constraint, the number of pass transistor stages from the inputs a0 and b0 to the output y3 is 7. Therefore, considering that the average delay time per stage is 0.4 ns, the delay constraint is not satisfied, and there is a high possibility that the circuit cannot be actually used.

(Third Embodiment) FIG. 3 is a process flow chart showing a process flow of a pass transistor logic designing method according to the present invention. This embodiment is originally effective for a large-scale circuit that cannot be optimally converted into BDD as a whole circuit, but here, for simplification, FIG. 5 is used as in Embodiments 1 and 2. An explanation will be given based on the logical specifications shown.

Since step 2 for generating a logic circuit using a normal gate is the same as that in the first embodiment, its explanation is omitted here.

In step 23, the logic redundancy included in the circuit is removed by applying the logic optimization process to the logic circuit generated in step 2.

The reason why the logic optimizing process is performed in this embodiment is that in this embodiment, since the logic circuit is divided and each partial circuit is independently converted into a pass transistor circuit, logical redundancy is provided between the partial circuits. This is because if exists, it remains until the end.

In the conventional method for converting the entire circuit into BDD, this step is not necessary because the converted BDD does not depend on the structure of the original logic circuit (it is uniquely determined by the logic and the input order in Shannon expansion). is necessary.

The logic circuit shown in FIG. 6 is a logic circuit generated by performing steps 2 and 23 based on the logic specification 1. (Embodiment 1 and Embodiment 2
Although it was not mentioned in the above description, the logic circuit of FIG. 6 is the result of the logic optimization processing. ) In step 24, the generated logic circuit is divided into a plurality of sub-circuits.

Here, the fan-out 2 which has been often used in the technology mapping process of allocating cells to the logic independent of the technology in the logic synthesis process is used.
The method of dividing the circuit by the above internal signal (signal i in FIG. 6) is used.

The number of inputs of each sub-circuit further divided is checked, and if it is larger than a predetermined value, the circuit is further divided, and the division is repeated until the number of inputs falls within the limit value. As the limit value here, the number of inputs that can optimize the input signal order in the Shannon expansion process is used.

In the logic circuit of FIG. 6, since the number of inputs is eight, it is not necessary to divide the circuit originally, but for the sake of explanation, the circuit is divided into two.

At this time, the logical functions of the divided two sub-circuits are expressed by (Equation 12) and (Equation 13).

[0098]

(12) i = ^ ((a0 & b0 & (a1 | b1)) | (a1 & b1))

[0099]

[Mathematical formula-see original document] y3 = (((^ i | b2) & a2) | (^ i & b2)) @ a3 @ b3 In step 25, for example, "minimization of binary decision graph expressing a logical function" (signal The optimal input order is determined using a method such as that described in Academic Techniques COMP 91-15 p27). Since the number of inputs of each sub-circuit is limited in advance by the circuit division in step 24, the order of input variables can be determined by the above method. Here, it is assumed that the input order is determined as shown in FIG.

In step 26, Shannon expansion is performed on each sub circuit according to the input order determined in step 25, and B
Convert to DD. Since this step basically repeats the process of step 5 in the first embodiment for each sub-circuit, the description thereof is omitted here.

Multiple BDs as generated in this step
The logical expression in which D is connected in a network form is no longer a BDD as a whole, and therefore cannot be applied to general BDD applications, but as in the present invention, the BDD is directly connected to a logical circuit. The method of converting to can be effectively used for the purpose of reducing the total number of BDD nodes.

FIG. 19 shows the generated BDD.

In step 27, the BDD generated in step 26 is converted into a pass transistor logic circuit as in step 6 of the first embodiment. FIG. 20 shows the generated pass transistor logic circuit.

(Embodiment 4) FIG. 21 is a processing flow chart showing the processing flow of the pass transistor logic design method according to the present invention. Since the logic specification 1 of the present embodiment, step 2 of generating a logic circuit using a normal gate, and step 3 of evaluating the signal transition probability of each input are the same as those of the first embodiment, their description is omitted here. To do. Also in this embodiment, it is assumed that the signal transition probabilities shown in FIG. 8 are obtained.

FIG. 24 shows a delay time constraint 210 in this embodiment. It is described here that the delay from the input a3 to the output y3 must be 1.2 ns or less and the delay from the input b3 to the output y3 must be 1.7 ns or less.

The step 14 for calculating the pass transistor stage number constraint between the input and output is the same as that of the second embodiment, and therefore the detailed description thereof will be omitted.
If the average delay per stage is 0.4 ns, from the delay time constraint, a3 to y3 are within 3 stages of pass transistors, b3 to
It can be calculated that the delay up to y3 is within 4 steps.

In step 211, the input variables are ordered while considering the signal transition probability of each input obtained as a result of step 3 and the pass transistor stage number constraint between the input and output obtained as a result of step 14.

In the present embodiment, it is indispensable to generate a circuit that satisfies the delay constraint, and the aim is to minimize power consumption on the circuit. Therefore, the constraint on the number of pass transistor stages relating to a3 and b3 is satisfied. Then, the input signals are ordered in descending order of signal transition probability. in this way,
The pass transistor stage number constraint has a higher priority than the signal transition probability. FIG. 25 shows an ordered list of input signals.

Since the step 5 of generating the BDD by Shannon expansion of the logic circuit and the step 6 of converting the BDD into the pass transistor logic circuit are the same as those in the first embodiment, their explanations are omitted here.

As described above, by using the designing method of this embodiment, it is possible to generate a pass transistor circuit which consumes less power while satisfying a given delay constraint.

(Fifth Embodiment) FIG. 22 is a processing flow chart showing the processing flow of the pass transistor logic designing method according to the present invention. Since the logic specification 1 of the present embodiment, the step 2 for generating a logic circuit with a normal gate, the logic optimization step 23, and the circuit division step 24 are the same as those in the third embodiment, their explanations are omitted here. .

In step 221, the signal transition probability concerning the input signal of each sub-circuit divided in step 24 is evaluated. This can also be performed by using the logic simulation as in step 3 of the first embodiment.

In step 222, the input variables are ordered for each sub-circuit from the largest signal transition probability to the smallest signal transition probability. This step can also be performed in the same manner as step 4 in the first embodiment.

In this embodiment, the input variable order is determined based on the signal transition probability for the purpose of reducing power consumption. However, in actual circuit design, low power consumption and minimization of circuit scale are compatible. Often not. In such a case, it is necessary to order the input signals while considering the trade-off between them, and the present invention includes such a case.

Step 26 of Shannon expansion of each sub-circuit of this embodiment to generate BDD and B for each sub-circuit
Step 2 of converting DD to pass transistor logic circuit
Since 7 is the same as that of the third embodiment, the description thereof is omitted.

By using the designing method of the present embodiment as described above, it is possible to generate a pass transistor circuit with low power consumption even for a large-scale logic circuit.

(Sixth Embodiment) FIG. 23 is a process flow chart showing a process flow of a pass transistor logic design method according to the present invention. Since the logic specification 1 of the present embodiment, the step 2 for generating a logic circuit with a normal gate, the logic optimization step 23, and the circuit division step 24 are the same as those in the third embodiment, their explanations are omitted here. .

It is assumed that the same delay time constraint 13 as that of the second embodiment shown in FIG. 14 is given.

At step 231, the delay time constraint 13 is given.
Based on the above, the pass transistor stage number constraint between the input and output of each sub-circuit divided in step 24 is calculated. Here, first, the same method as in step 14 of the second embodiment is used to calculate the constraint on the number of input / output stages in the entire circuit, and then distribute the obtained constraint on the number of stages to each sub-circuit.

As shown in FIG. 15, in the overall circuit, the number of stages constraint that a0 to y3 is within 5 stages and b0 to y3 is within 3 stages is obtained. When this is distributed so as to balance the delay constraints among the sub-circuits, in the sub-circuit corresponding to (Equation 12), a0 to i are within 3 stages, b0 to i are within 1 stage, and one is (Equation 13). In the sub circuit, the number of stages is restricted from i to y3 within 2 stages.

There are various methods for calculating the constraint on the number of stages between the input and output of each sub-circuit from the delay time constraint, but the present invention includes such a method. There is.

In step 232, the input signals are sequenced for each sub-circuit in consideration of the constraint on the number of stages in the same manner as in step 15 of the second embodiment. FIG. 26 shows the input order obtained as a result of this step.

Step 26 of Shannon expansion of each sub-circuit of this embodiment to generate BDD and B for each sub-circuit
Step 2 of converting DD to pass transistor logic circuit
Since 7 is the same as that of the third embodiment, the description thereof is omitted here.

Note that the fifth embodiment (FIG. 22) and the sixth embodiment (FIG. 23) are combined to determine the order of the input signals of each sub-circuit based on the signal transition probability and the stage number constraint. May be.

[0125]

As described above, according to the present invention, it is possible to synthesize a pass transistor circuit having the following features from given logical specifications.

(1) The higher the signal transition probability, the smaller the number of pass transistor stages between the input and the output. Therefore, a signal having a high transition probability does not propagate for a long time, and the sum of the transition probabilities is small in the entire circuit, resulting in low power consumption. Be converted.

(2) The number of pass transistor stages between the input and the output to which the delay time constraint is applied is limited based on the delay constraint value. A high-speed operation of the circuit is realized by giving a delay constraint between the input and output which are the critical paths.

(3) A practical circuit size is realized even for a circuit which cannot be optimized by the conventional design method due to the large number of inputs and becomes unnecessarily large.

[Brief description of drawings]

FIG. 1 is a process flow diagram of a pass transistor logic design method according to a first embodiment of the present invention.

FIG. 2 is a processing flow chart of a pass transistor logic design method according to the second embodiment of the present invention.

FIG. 3 is a process flow diagram of a pass transistor logic design method according to the third embodiment of the present invention.

FIG. 4 is a diagram showing a functional description for explaining a pass transistor logic design method of the present invention.

FIG. 5 is a diagram showing a logical expression for explaining a pass transistor logic design method of the present invention.

FIG. 6 is a logic circuit diagram generated from a logical expression according to the first embodiment of the present invention.

FIG. 7 is a diagram showing test vectors required to evaluate a signal transition probability in the first embodiment of the present invention.

FIG. 8 is a diagram showing a result of ordering inputs based on a signal transition probability in the first embodiment of the present invention.

FIG. 9 is a diagram showing a BDD generated from a logic circuit according to the first embodiment of the present invention.

FIG. 10 is a diagram showing conversion from BDD to pass transistor logic circuit in the first embodiment of the present invention.

FIG. 11 is a pass transistor logic circuit diagram converted from BDD in the first embodiment of the present invention.

FIG. 12 is a diagram showing a BDD generated from a logic circuit in an input order determined using a conventional method.

FIG. 13 is a pass transistor logic circuit diagram converted from a BDD generated using a conventional method.

FIG. 14 is a diagram showing an example of a delay constraint according to the second embodiment of the present invention.

FIG. 15 is a diagram showing a result of ordering inputs in consideration of a pass transistor stage number constraint in the second embodiment of the present invention.

FIG. 16 is a diagram showing a BDD generated from a logic circuit according to the second embodiment of the present invention.

FIG. 17 is a pass transistor logic circuit diagram converted from BDD in the second embodiment of the present invention.

FIG. 18 is a diagram showing the result of ordering the inputs so that the BDD size is minimized for each sub-circuit in the third embodiment of the present invention.

FIG. 19 is a diagram showing a BDD generated from a logic circuit according to the third embodiment of the present invention.

FIG. 20 is a pass transistor logic circuit diagram converted from BDD in the third embodiment of the present invention.

FIG. 21 is a process flow diagram of a pass transistor logic design method according to the fourth embodiment of the present invention.

FIG. 22 is a process flow diagram of a pass transistor logic design method according to the fifth embodiment of the present invention.

FIG. 23 is a process flow diagram of a pass transistor logic design method according to the sixth embodiment of the present invention.

FIG. 24 is a diagram showing an example of a delay constraint according to the fourth embodiment of the present invention.

FIG. 25 is a diagram showing a result of ordering the inputs in consideration of the pass transistor stage number constraint and the signal transition probability in the fourth embodiment of the present invention.

FIG. 26 is a diagram showing a result of sequencing inputs in consideration of a pass transistor stage number constraint for each sub circuit according to the sixth embodiment of the present invention.

[Explanation of symbols]

 1 Logic specification 2 Generate a logic circuit with normal gate 3 Evaluate signal transition probability of each input 4 Order each input by signal transition probability 5 Generate Shannon expansion of logic circuit to generate BDD 6 Convert BDD to pass transistor logic circuit 7 pass transistor logic circuit

Claims (8)

[Claims] 1. Based on the logic specifications of a given circuit,
A method of designing a pass transistor logic circuit, comprising: generating a logic circuit including a logic gate based on the logic specification; evaluating a signal transition probability of each input signal of the logic circuit; A step of ordering the signal transition probabilities from the highest to the lowest, and applying the Shannon expansion process to the logic circuit in order from the highest signal transition probability of the input signals to the logic circuit. The step of generating a corresponding binary decision graph, and the step of generating a technology-independent pass transistor logic circuit by replacing each node of the binary decision graph with a two-input selector circuit by a pass transistor. Generated by reducing the number of logic stages between the input signal and the output signal with high transition probability Pass transistor logic design wherein the reducing the power consumption of the circuit. 2. The number of stages allowed in the pass transistor logic circuit based on a delay time constraint that defines a delay time allowed between input and output signals of the given circuit and an average delay time of the pass transistor logic circuit. The pass transistor logic design method according to claim 1, further comprising the step of calculating a stage number constraint that defines :, wherein the input signals of the logic circuit are ordered in consideration of the stage number constraint and the signal transition probability. . 3. The pass transistor logic design method according to claim 2, wherein the stage number constraint has a higher priority than the signal transition probability. 4. Based on the logic specifications of a given circuit,
A method of designing a pass-transistor logic circuit, comprising: generating a logic circuit including a logic gate based on the logic specifications; and delay defining a delay time allowed between input and output signals of the given circuit. Calculating a stage number constraint that defines the number of stages allowed in the pass transistor logic circuit based on a time constraint and an average delay time of the pass transistor logic circuit; and considering the stage number constraint, an optimum for Shannon expansion Determining the order of different input signals, applying Shannon expansion processing to the logic circuit in accordance with the order of the input signals, and generating a BDD corresponding to the logic circuit. By replacing each node in the binary decision graph with a 2-input selector circuit using pass transistors, Generating a pass transistor logic circuit, the delay circuit having a given delay time constraint by limiting the number of pass transistor stages between the input signal and the output signal to which the delay time constraint is given. A pass transistor logic design method characterized by satisfying: 5. Based on the logic specifications of a given circuit,
A method of designing a pass transistor logic circuit, the method comprising: generating a logic circuit including a logic gate based on the logic specifications; performing a logic optimization process on the logic circuit to delete a redundant circuit; Dividing the optimized logic circuit into a plurality of sub-circuits in consideration of the number of input signals of each of the plurality of sub-circuits generated, and minimizing the generated BDD. Determining an optimum order of input signals for Shannon expansion for each of the plurality of sub-circuits, and applying Shannon expansion processing according to the order of the input signals for each of the plurality of sub-circuits, Generating a binary decision graph corresponding to a logic circuit; and, for each of the plurality of sub-circuits, the binary decision graph. The method includes the step of generating a technology-independent pass-transistor logic circuit by replacing each node of the above with a 2-input selector circuit using a pass transistor, and by limiting the number of input signals of each sub-circuit, the optimum input signal can be obtained. A pass-transistor logic design method characterized by enabling order determination and minimizing generated circuits. 6. The method further comprises evaluating a signal transition probability of each of the input signals of the sub-circuit, wherein the order of the input signals of the sub-circuit is determined based on the signal transition probabilities. Item 5. The pass transistor logic design method according to Item 5. 7. The number of stages allowed in the pass transistor logic circuit based on a delay time constraint that defines a delay time allowed between input and output signals of the given circuit and an average delay time of the pass transistor logic circuit. 6. The pass transistor logic design method according to claim 5, further comprising the step of calculating a stage number constraint that defines the step number constraint, wherein the order of the input signals of the sub-circuit is determined based on the stage number constraint. 8. The number of stages allowed in the pass transistor logic circuit based on a delay time constraint that defines a delay time allowed between input and output signals of the given circuit and an average delay time of the pass transistor logic circuit. 7. The pass transistor logic of claim 6, further comprising the step of calculating a stage number constraint that defines ## EQU1 ## wherein the order of the input signals of the sub-circuit is determined based on the stage number constraint and the signal transition probability. Design method.