JPH0423150A - Method and device for memory control of semiconductor disk device - Google Patents

Abstract

PURPOSE:To improve the availability of a semiconductor memory part by providing an address control part to store the addresses excluding only the error addresses into an address register when plural address errors are produced at the semiconductor memory part. CONSTITUTION:When plural address errors are produced at a semiconductor memory part 9, the addresses excluding these error addresses are stored in an address register 6 by an address control part 14. Then the part 14 performs the address addition processing to skip over the error addresses when optional addresses have errors at the part 9. The presence or absence of errors is also checked in regard of the added addresses. Then the addresses having no error are stored in the register 6 excluding the error addresses. Thus it is possible to inhibit the writing operations into plural error addresses of a semiconductor memory.

Description

[Detailed description of the invention] (Table of contents) Overview Industrial field of application Prior art (Figs. 9 to 12) Problems to be solved by the invention Means for solving the problems (Figs. 1 and 2) Figure) Example of operation (Figures 3 to 8) Effects of the invention [Summary] Regarding the memory control method in a semiconductor disk device, even if an error occurs in multiple addresses in the semiconductor memory, it is possible to prevent writing to only those addresses. A semiconductor memory section, a memory access controller that controls access such as writing and reading to the semiconductor memory section, a service processor that performs diagnosis and maintenance of the semiconductor memory section, etc., and a memory access controller that performs access control such as writing and reading to the semiconductor memory section; In a semiconductor disk device, the semiconductor disk device has an error address storage section that stores an error address when an error occurs in the semiconductor memory section during diagnosis, and an address register that stores an address of data to be written to or read from the semiconductor memory section. , an address control section for storing an address with only the error address removed in the address register when an error occurs at a plurality of addresses on the semiconductor memory section; If this occurs, the address control unit performs address addition processing to skip over the error address, determines whether or not the added address is in error, and removes only the error address.
The apparatus and method are configured to store other non-error addresses in the address register.

[Industrial application field]

The present invention relates to a memory control method in a semiconductor disk device.

(Prior Art) In a semiconductor disk device, when an error occurs in memory at multiple arbitrary addresses on the semiconductor memory section, attempts have been made to prevent the use of only the addresses where the error occurred. There were some technical inadequacies and areas that were out of control.

Therefore, there has been a strong demand for the development of a memory control method that further improves the usage efficiency of the semiconductor memory section.

The memory control device in a conventional semiconductor disk device is
There is something like the one shown in Figure 9. Among these, 1 is a memory access controller (MAC), which performs access control such as read/write of the semiconductor memory section 9.

A service processor (SVP) 2 diagnoses and maintains the semiconductor memory unit 9.

Reference numeral 3 denotes an error address storage section which stores an error address when an error occurs in the semiconductor memory section 9 during diagnosis of the service processor 2.

4 is an error address control section, and an error address storage section 3
Check if there are consecutive addresses in
The addition instruction is controlled by the consecutive number.

Reference numeral 5 denotes an error address comparison unit which determines whether or not there is an error location when the semiconductor memory unit 9 is accessed from the memory access controller 1.

6 is an address register, 7 is a data register, and 8 is an adder circuit which adds a predetermined number to an address in order to jump over the address when an error address is selected.

Reference numeral 9 denotes a semiconductor memory, which is a storage device that has addresses in the same format as a disk device and can perform high-speed writing and reading without requiring seek time.

In the operation of this semiconductor disk device, as shown in FIG. 10, first, the service processor 2 checks the semiconductor memory 9 in an initial diagnosis (Sl).

The diagnosis determines whether there is any abnormality (S2).

If there is no abnormality, the service processor 2 sets the address of the abnormality in the error address storage section 3 (S3
).

The error address control unit 4 checks whether there are consecutive addresses in the error address storage unit 3 (S
4).

The diagnosis determines whether there are consecutive addresses (S
5).

If there is no consecutive address, the error address control unit 4 stores an instruction to add +1 to that address (S6).

In S5, if there is a continuous address (of n steps), the error address control unit 4 stores an instruction to add +n to the first address (S7).

In S2, if there is an abnormality, the error address control unit 4
stores that no addition instruction is given at all (S8).

After storing the addition (non-addition) instruction, the memory access controller 1 transmits the read/write address (S9).

It is transmitted to the address comparator 5 through the address register (SIO).

It is compared to see if it matches the address set in the error address storage section 3 (Sll).

It is determined whether the comparison results match (S12).

If they do not match, the error address control unit 4 does not instruct the addition circuit 8 to add (313).

In S12, if they match, the error address control unit 4 instructs to add the previously stored addition amount corresponding to that address (S14).

Thereafter, an instruction to add the adder circuit 8 to the address from the address register 6 is executed (S15).

The semiconductor memory unit 9 is accessed using the address processed by the adder circuit 8 (S16).

Execute read/write in semiconductor memory section 9 (
S17).

It is checked whether reading/writing of data between the memory access controller 1 and the semiconductor memory section 9 has been completed (S18).

Determine whether the read/write is completed (S1
9). If the read/write execution has not been completed, the process returns to S9.

If the addition instruction has been completed, the addition instruction of the addition circuit 8 is canceled (S
20).

Then, it is checked whether there is data transfer to a new area (S21).

It is determined whether or not the data is transferred (S22).

As a result of the determination, if there is no data transfer, the process ends, and if there is, the process returns to S9.

To illustrate this process using a specific address, the first
As shown in Figure 1, if an error occurs at consecutive addresses 0005 and 0006, and then an error occurs at address 1 and 0008 as shown in Figure 12, the address is stored in the error address storage section 3. 0005゜000
6 is stored, and the addition instruction sent by the address control unit 4 becomes +2 from when address 0005 was sent, and the address for accessing the semiconductor memory unit 9 becomes 0004.
After the address comes the address 0007. After that, 000, which is the address 0008 stored in the error address storage section 3,
After the address 8 is transmitted, the addition instruction becomes +3, and the address for accessing the semiconductor memory section 9 jumps from address 0009 to address 3 and reaches address 000B.

(Problem to be Solved by the Invention) In the conventional memory control method described above, as shown in FIG. 12, after an error occurs at consecutive addresses 0005°0006, an error also occurs at the ooos address after the first address. In such a case, when address 0006 is sent from memory access controller 1, it will be written to error address 0008, and when address ooos is sent from memory access controller 1, the number of error addresses will be cumulatively added. Therefore, there was a problem in that the address 000A, which did not have an error, was omitted and written to the next address 0OOB.

The present invention has been made in view of the above-mentioned problems, and the technical problem set for solving the problem is to prevent writing to only those addresses even if an error occurs at multiple addresses in a semiconductor memory. An object of the present invention is to provide a memory control device for a semiconductor disk device and a memory control method thereof, which can perform the following operations.

[Means to solve the problem]

As a specific means for solving the above problems, the present invention provides a semiconductor memory unit 9 in configuring a memory control device in a semiconductor disk device, as shown in FIG.
, a memory access controller 1 that controls access such as writing and reading to the semiconductor memory section 9 , a service processor 2 that performs diagnosis and maintenance of the semiconductor memory section 9 and the like; In a semiconductor disk device having an error address storage section 3 for storing an error address when an error occurs in the semiconductor memory section 9, and an address register 6 for storing an address of data to be written to/read from the semiconductor memory section 9. , an address control section 14 that stores an address excluding only the error address in the address register 6 when an error occurs in a plurality of addresses of the semiconductor memory section 9.

As shown in FIG. 2, this address control unit 14 includes a comparison unit for determining whether or not the accessed address is an error address when the semiconductor memory unit 9 is accessed from the memory access controller 1. A circuit 16, an address control processing unit 17 that controls skipping of error addresses based on the comparison result, an addition circuit 18 that executes an address addition instruction under the control of the address control processing unit 17, and a circuit 16 that determines whether an error has occurred or not. It is preferable to include a multiplexer 15 for switching the output data for checking the address between the address obtained by adding the addresses by the adder circuit 18 and the address transmitted in response to an instruction from the memory access controller 1.

The memory control method in this device is such that when an error occurs at any plurality of addresses on the semiconductor memory section 9, the address control section 14 performs address addition processing to skip over the error address, and It is also determined whether or not an error has occurred in an address, and only the error address is removed, and other addresses with no error are stored in the address register 6.

(Function) With the above configuration, when an error occurs at any plurality of addresses on the semiconductor memory unit 9, the address control unit 14 performs address addition processing to skip over the error address, and the addition It is also possible to determine whether or not an error has occurred with respect to an address that has been detected, and to write to an error address in the semiconductor memory section 9, or conversely, to prevent a situation where an address that does not have an error is skipped over. To improve the usage efficiency of the memory section 9.

In this case, in the address control unit 14, the comparison circuit 16 determines whether the error address matches the error address stored in the error address storage unit 3, and based on the comparison result, the address control processing unit 17 outputs the error address. In such a case, the adder circuit 18 performs address addition to skip addresses, controls the adder circuit 18 so that address addition is not performed unless the address is an error address, and switches the bus of the multiplexer in accordance with the output of the comparison result of the comparator circuit 16. Also, regarding the address after adding the address,
The comparison circuit 16 compares whether the address is an error address or not.
If the address after the addition is an error address, it is added again to the adder circuit 18 via the address control processing section 17 to increase the address to be skipped, and if it is not an error address, it is output as is to the address register 6 side without being added.

(Embodiment) Hereinafter, as an embodiment of the present invention, a case where buses are switched by a multiplexer and the result of the adder circuit is inputted to the comparator circuit will be illustrated and explained.

An apparatus for implementing the present invention will be described based on the overall configuration of FIG. 3 and the configuration of the address control section of FIG. 4.

Here, 1 is a MAC (memory access controller), which performs access control such as writing and reading of the semiconductor memory section 9.

Reference numeral 2 denotes an SVP (service processor), which diagnoses and maintains the semiconductor memory section 9 and the like via an address bus 31 and a data bus 32.

Reference numeral 3 denotes an error address storage section, which stores an error address when an error occurs in the semiconductor memory section 9 when the semiconductor memory section 9 is diagnosed by the 5VP2 in accordance with instructions from the 5VP2.

6 is an address register that stores the address transmitted from the address control section 24.

7 is a data register that writes data to the semiconductor memory section 9.
Stores the data to be read.

A semiconductor memory section 9 is connected to the MACI and SVP 2 via an address bus 31, an address register 6, a data bus 32, and a data register 7, respectively. The semiconductor memory section 9 has data written to or read from it through MACI access, and receives instructions for diagnosis, maintenance, etc. through the 5VP2.

Reference numeral 24 denotes an address control unit which determines whether or not the accessed location is an error location when the semiconductor memory unit 9 is accessed from the MACl, executes control and address addition to skip the error address, and further performs address addition. The error check is performed by switching between the address specified by MACl and the address specified by MACl.

The address control unit 24 switches not only the address specified by MACl but also the address specified by MACl and the added address in order to determine whether or not an error has occurred in that address by adding the address. Multiplexer 2 outputs
5, a comparison circuit 26 for determining whether or not there is an error location when the semiconductor memory section 9 is accessed from the MACl, and an address control processing section that performs control to skip over the error address based on the comparison result. CPU
27, an adder circuit 28 that executes an address addition instruction under the control of the CPU 27, a register 29 that stores the output of the multiplexer 25, and a ROM 30 that stores a program for driving the CPU 27.

The multiplexer 25 receives an input from the J input terminal which is the output of the comparator circuit 26, and outputs signals from the summer output terminal and the Q output terminal, respectively, and the output from the output terminal of the JK flip-flop 25a and MACl. AND circuit (A) 25b which inputs the address from the JK flip-flop 25a, and an AND circuit (A) which inputs the output from the Q output terminal of the JK flip-flop 25a and the added address from the adder circuit 28.
B) 25c, the output of AND circuit 25b, and AND circuit 2
5c and output to the comparator circuit 26 side.
It consists of a circuit 25d.

The operation of the embodiment configured as described above will be explained next.

First, the clock control for each part is as shown in the clock timing chart in FIG.

In other words, the main clock (MA
IN CLOCK), as well as T as a timing signal.
I, T2. T3. Prepare four clocks called T4,
TIC by taking logical product (AND) with each main clock
LK, T2CLK.

Create T3CLK and T4CLK. And each signal TIC
LK, T2CLK, T3CLK.

Both T4CLK and clocks are generated at a rate of one for every four main clocks, and are shifted one by one each time the main clock is input.

FIG. 6 shows changes in signals in each part of the address control section 24 and each bus when processing is performed according to this timing, and the processing procedure is shown as a flowchart in FIGS. 7 and 8.

In FIG. 7, first, in step S1, 5VP2
In order to check whether the semiconductor memory section 9 operates normally, test data is written to and read from the semiconductor memory section 9 in an initial diagnosis after the power is turned on and before operation as a system.

Next, in step S2, if there is an abnormality in the semiconductor memory section 9, the error address is stored in the error address storage section 3 under the control of 5VP2, and conversely, if there is no abnormality, the error address is not stored in the error address storage section 3. .

Next, in step S3, the address control unit 24
Under the control of the PU 27, the addresses set in the error address storage section 3 are released, addition data is prepared and stored, and each head address of the error addresses is set in a register provided in the comparison circuit 26.

To explain the operation of step S3 more specifically,
As shown in the flowchart of FIG. 8, step S26
And in S27, the error address storage section 3 is sent by the CPU 27.
In order to check the addresses stored in the semiconductor memory section 9, the first address of the semiconductor memory section 9 is prepared. In step S28, it is checked whether the address is in the error address storage section 3. If so, the process advances to step S29, where +1 is set as addition data, and at the same time, step S3
0, the current address is set in the register of the comparison circuit 26.

Next, the process advances to steps S31 and S32, and it is checked whether there are any errors in consecutive addresses. In step S33, if there are consecutive addresses, the process advances to step S34, where the added data is further added, and up to the address where no error occurs, step S31. S32.
S33. and repeat S34.

If there is no error in step S33, the process advances to step S35, and the added data for the error head address is stored.

By the way, if the investigated address is not in the error address storage section (3) in the previous step S28, steps S29 to S
35 is omitted.

The process then proceeds to step S36, in which it is checked whether all addresses in the semiconductor memory section 9 have been checked. If not completed, the process advances to steps S37 and S38, addresses are added, and the operations from 328 onwards are repeated. When all addresses have been checked, this routine ends.

After completing the above operations, the process advances to step S4 in the flowchart of FIG. Here, write from MACl.
The address to be called is transmitted at timing T1. Thereafter, in step S5, the address is transferred to the address bus 3.
1. Set in the comparison circuit 26 via the multiplexer 25. Then, the process proceeds to step S6, and at timing T2, the address is compared with a preset address in a register in the comparator circuit 26.

Here, if the comparison results match as shown in step S7, the process advances to step S8, where a match signal is transmitted to the CPU 27 via the bus 34 at timing T2, and at the same time, the current address is set in the register 29 at the same timing. Then, the process proceeds to step SIO, and based on the match signal on the bus 34 and the signal output from the register 29 via the address bus 35, the CPU 27 transmits the addition data via the bus 36 under program control. Thereafter, as in step S12, the adder circuit 28 adds M at timing T3.
Addition data from the CPU 27 is added to the address received from the ACI via the address bus 31, and the added data is transmitted via the address bus 31a.

What you need to be careful about at this time is that if there was an error address and there was additional data,
If another error address exists, the added data is to be transmitted in the form of adding new added data to the previous added data. This will be explained later in the explanation based on the time chart shown in FIG. 6.

Next, step S14. S15 is not directly related to the actual operation, but I will mention its necessity.As long as there is no error address, the address sent from MACl via the address bus 31 is used as an input signal to the comparator circuit 26. , can be used as is. This is because the address is not corrected even after passing through the adder circuit 28.

However, if an error address exists, the adder circuit 28 adds the address and corrects it. Therefore, in order to compare addresses later, the corrected address, that is, the adder circuit 28
It is meaningless unless the address on the address bus 31a, which is the output of , is input. Therefore, as a circuit, the fourth
As shown in the figure, the coincidence signal of the comparison circuit 26 is taken into the flip-flop 25a via the bus 34, and the timing T
4 to switch the multiplexer 25.

By the way, the previous step S6. In S7, if the address comparison result does not match, step S11 is followed by C as in S13.
The PU 27 leaves the addition data as it was before. That is, in the first case, the addition data remains 0, and as a result, the address is not added.

Next, in step S16, the address output from the address control unit 24 via the rear address bus 31a is set in the address register 6 at timing T4. Then, as in step S17, the semiconductor memory section 9 is accessed using the address set in the address register 6, and step S17 is performed.
At step 18, writing and reading are executed to and from the semiconductor memory section 9.

When the operations up to this point are completed, the process advances to step S19.
It is checked whether writing and reading of data between the MACl and the semiconductor memory section 9 has been completed. If not, the process returns to step S4 and the above operations are repeated. Also,
If it has been completed, as shown in step S21, the CPU 2
Flip-flop 25 is used to cancel the addition data issue from 7 and at the same time restore the bus selection of multiplexer 25 to its original state.
Reset a.

Next, step S24. If data is transferred to a new area of the semiconductor memory section 9 in S25, the process returns to step S4 and the above operations are repeated. Furthermore, if there is no more data to be transferred, the process ends.

The above operation will be briefly supplemented and explained using a specific example shown in the time chart of FIG.

In this example, address 0005 of the semiconductor memory section 9, 0
Assume that an error occurs at addresses 006 and 0008.

According to step S3 in the flowchart of FIG. 7, that is, according to the flowchart of FIG. 8, address 0005 is stored in the error address storage section 3.

Since addresses 0006 and ooos are stored, the addition data +2. Added data +1 is obtained for the error address ooos.

Step S6. In S7, since there is no error from address 0001 to address 0004, control is performed on the step Sll side, and as a result, the semiconductor memory section 9 is accessed using the same address.

Next, when address 0005 comes, the comparison results match, so control is performed on the step S8 side, and the CPU
The added data +2 is transmitted to the bus 36 under the control of 27. Therefore, since the address 0007 appears on the address bus 31a for input to the address register 6, the semiconductor memory section 9 will be accessed using that address. At the same time, multiplexer 2
5, the B side, ie, the address bus 31a side, is selected. Therefore, 0006 is sent via address bus 31.
When the address is transmitted, the ooos address is outputted to the address bus 31a through the adder circuit 28, and inputted to the comparison circuit 26 via the multiplexer 25.

Then, since the comparison results match again, addition data +1 is prepared under the control of the CPU 27. However, since the addition data +2 has been set first, the addition data +3 will also be sent to the bus 36 as a result.

Therefore, since address 0009 appears as the address input to the address register 6 via the address bus 31a, the semiconductor memory section 9 will be accessed using that address. Since there are no errors in subsequent addresses, an address added by +3 to the address bus from MACl appears on the address bus 31a, and as a result, the semiconductor memory section 9 is accessed with that address.

As described above, according to the embodiment, even if an error occurs in the memory at any plurality of addresses on the semiconductor memory unit 9, the address addition process is performed to skip the error address under the control of the address control unit 24. In addition to checking whether there is an error in the added address, it is possible to prevent writing to an error address in the semiconductor memory section 9 or, conversely, to avoid writing to an error address in the semiconductor memory section 9 or skipping an address that does not have an error. I can do it,
The usage efficiency of the semiconductor memory section 9 can be further improved.

〔Effect of the invention 〕

By using the apparatus and method according to the present invention as described above, when an error occurs at any plurality of addresses on the semiconductor memory section 9, the address control section 14 performs address addition processing to jump over the error address, then determines whether or not there is an error in the added address, and if there is an error, performs addition processing to jump over that address. , it is possible to prevent writing to an error address in the semiconductor memory unit 9 and, conversely, prevent a situation where the process skips over an address that does not have an error and proceed to the next step, so that only the error address can be skipped and executed. 9 can be used more efficiently.

For error addresses, after address addition is performed by the adder circuit 18, the comparator circuit 16 inputs the address via the multiplexer 15 to compare whether or not it is an error address, and if the result is an error address, Addresses are added again by the adder circuit 18 under the control of the address control processing unit 17, making it possible to eliminate error addresses from being overlooked, making it possible to reliably jump over error addresses, and preventing errors from occurring in consecutive addresses. Even if an error occurs and an error also occurs at the address beyond the error address,
It is possible to prevent writing to error addresses, and the address control processing unit 17 is controlled not to add addresses to addresses that do not have errors,
Skipping can be prevented during memory access.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention; FIG. 2 is a diagram showing the address control section of the present invention; FIG. 3 is a diagram showing the configuration of the embodiment; FIG. 4 is the address control section of the embodiment. FIG. 5 is a time chart of the clock timing of the embodiment; FIG. 6 is a time chart showing the operation of the embodiment; FIG. 7-1 and FIG. 7-2 are the embodiments. FIG. 8 is a flowchart explaining the procedure for creating addition data for the error start address in the embodiment, FIG. 9 is a block diagram showing a conventional example, and FIGS. 10-1 to 10-3 are Flow chart according to the conventional example. FIG. 11 is an explanatory diagram of a specific example according to the conventional example. FIG. 12 is an explanatory diagram of a specific example in which a problem occurs in the conventional technique. l...Memory access controller (MAC) 2...
- Service processor (svp) 3...Error address storage section 6...Address register 9...Semiconductor memory section 14...Address control section 15...Multiplexer 6...Comparison circuit 7...Address Control processing unit 8...addition circuit Flowchart of FIG. 10 according to the conventional example (Part 1) Flowchart of FIG. 10 according to the conventional example (Part 3) o007 0o08 +2 +2 11th illustrating a specific example according to the conventional example FIG. 00A 00B 00C 00D 00E 01F Procedural Amendment (Bin) September 1990

Claims (1)

[Claims] (1) A semiconductor memory section (9);
), and a service processor (2) that performs diagnosis and maintenance of the semiconductor memory section (9), etc.
an error address storage section (3) for storing an error address when an error occurs in the semiconductor memory section (9) as a result of diagnosis from the service processor (2); In a semiconductor disk device having an address register (6) for storing an address of data to be written/read, the semiconductor memory section (
9) Memory control in a semiconductor disk device characterized by comprising an address control unit (14) that stores an address excluding the error address in the address register (6) when an error occurs in a plurality of addresses. Device. (2) The address control unit (14) is connected to the semiconductor memory unit (9) from the memory access controller (1).
) to determine whether the accessed address is an error address or not (
16), an address control processing unit (17) that controls skipping of error addresses based on the comparison result (16), and an addition circuit (18) that executes an address addition instruction under the control of the address control processing unit (17). and the address obtained by adding the address by the adder circuit (18) to the data to be output to check whether an error has occurred or not, or
a multiplexer () that switches to the address transmitted according to instructions from the memory access controller (1);
15). The memory control device in a semiconductor disk device according to claim 1, further comprising: (3) If an error occurs at any plurality of addresses on the semiconductor memory section (9), the address control section (14)
) performs address addition processing to jump over the error address, determines whether or not there is an error in the added address, removes only the error address, and stores the other non-error addresses in the address register (6). 3. The memory control method in a semiconductor disk device according to claim 1, wherein the memory control method is configured to store the memory in a semiconductor disk device.