JPH0434981A - Semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To make small the size of a memory and to make it possible to conduct a high-speed information readout by a method wherein a selector gate electrode and a floating gate electrode are arranged in parallel between source and drain regions and an increase in the density of the memory and the speedup of the memory are attained. CONSTITUTION:In case a memory is a non-selective one, the conductance of a channel formation region 3 of the non-selective memory can be always set into a small conductance by grounding the potentials of a selector gate electrode 10 and a control gate electrode 8. Accordingly, even if a voltage is applied to a drain region 4, an unnecessary charge is not injected in the region 3 because the inductance of the region 3 of the non-selective memory is set small. As this result, a high-speed information readout can be conducted. The reason why the conductance of the region 3 is small in a non-selective state regardless of the potential of a floating gate electrode 6 is because the conductance of the region 3 is controlled by the electrode 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor nonvolatile memory used in IC carts and the like.

[Summary of the invention]

This invention relates to MIS (Meta) having a selection gate electrode.
In a semiconductor nonvolatile memory of the 14nslator-5emiconductor type, a charge storage layer is provided above the channel formation region and a selection gate electrode is provided below the channel formation region, thereby achieving high speed operation and high integration density. be.

[Conventional technology]

Conventionally, as shown in FIG. 2, an N0 type source region 12 and an N' type drain region 14 are provided on the surface of a P type silicon substrate 11, and a selection gate insulating film 19 is provided between the source region 12 and the drain region 14. A selection gate electrode 20 is provided through the gate insulating film 15, and a floating gate electrode 16 is provided through the gate insulating film 15, and the conductance between the source region and the drain region is controlled by the selection gate electrode 20 and the floating gate electrode 16. sexual memory is known.

[Problem to be solved by the invention]

However, in conventional semiconductor non-volatile memories, the selection gate electrode and the floating gate electrode are arranged in series between the source region and the drain region, both electrically and structurally, making it difficult to achieve high integration. was difficult. Furthermore, when reading memory information, if the dark voltage of the control gate electrode 18 that controls the floating gate electrode is in a depressed state, the substrate 11 under the floating gate electrode of the selected memory
Since charging charges enter the zero surface, unnecessary charges increase, and as a result, high-speed readout is also difficult.

Therefore, in order to solve these conventional drawbacks, the present invention aims to provide a semiconductor nonvolatile memory that is small in memory size and capable of high-speed reading.

[Means to solve the problem]

In order to solve the above problems, the present invention makes it possible to achieve higher density and higher speed by arranging the selection gate electrode and the floating gate electrode in parallel between the source region and the drain region.

〔Example〕 Embodiments of the present invention will be described below based on the drawings.

In FIG. 1, a silicon thin film consisting of an N' type source region 2, an N+ type drain region 4, and a channel forming region 3 between the source region 2 and the drain region 4 is formed on the surface of an insulating base FiI. A selection gate f4 pole 10 is provided below the channel forming region 3 via a selection gate insulating film 9, a floating gate electrode 6 is provided above the channel forming region 3 via a gate insulating film 5, and a floating gate electrode 6 is provided above the channel forming region 3 via a gate insulating film 5. A control gate electrode 8 is provided on the control gate insulating film 7 with a control gate insulating film 7 interposed therebetween. The floating gate electrode 6 is entirely covered with an insulating film,
Its potential is controlled by the potential of control gate electrode 8. Further, the conductivity type of the channel forming region is controlled by the potential of the floating gate electrode 6 and the selection gate electrode 10. In general, since it is necessary to keep the conductance of the channel forming region 3 small when no memory is selected, it is formed to be P type, which is the opposite conductivity type to the source region 2 and drain region 4. The conductance of the channel forming region 3 is the same as that of the floating gate electrode 6 and the selection gate electrode IO.
In order to be able to control from both sides by the potential of
The thickness of the channel forming region 3 needs to be reduced to a level that allows all of the chaffle forming region 3 to be depleted.

Next, the operation of the semiconductor nonvolatile memory of the present invention will be explained.

First, to read memory information, the source region 2 is grounded, a voltage as high as the power supply voltage is applied to the control gate electrode 8 and the selection gate electrode 10, and the conductance between the source region 2 and the drain region 4 is detected. . That is, when a voltage a is applied to the drain region 4 through a load, if the conductance of the channel forming element el1M3 is large, the potential Vout of the drain region 4 becomes close to 0.
Conversely, when the conductance of the channel forming region is small, the potential Vout of the drain region 4 becomes a high potential on the power supply voltage side. The conductance of the channel forming region 3 is
It changes depending on the amount of charge on the floating gate electrode 6. When many electrons are injected into the floating gate electrode 6, the conductance is small, and conversely, when there are few electrons, the conductance becomes large.

When the memory is not selected, the conductance can always be kept small by grounding the potentials of the selection gate electrode 1o and the control gate electrode 8. Therefore, even if a voltage is applied to the train region 4, unnecessary charges are not injected into the channel forming region 3 because the conductance of the channel forming region 3 of the unselected memory is set small. As a result, information can be read out at high speed. Regardless of the potential of the floating gate electrode 6, the channel formation region 3
The reason why the conductance of the channel forming region 3 is small in the non-selected state is that the conductance of the selected gate electrode 10 is small in the non-selected state.
This is because it is controlled by

Next, a write operation for injecting electrons into the floating gate electrode 6 will be explained.

The source region 2 is grounded, a drain write voltage (for example, 5 V) is applied to the drain region 4, and a control gate write voltage V (6p (for example, 10 V) is applied to the control gate electrode 8.
) is applied. Many real carriers are generated between the drain region 4 and the channel forming region 3, and some of them are injected into the floating gate electrode 6. It is written by so-called channel injection. Writing can be performed at high speed by making the channel forming region 3 between the source region 2 and drain region 4 about 0.2-. Furthermore, in the nonvolatile memory of the present invention, since the channel forming region 3 is completely depleted during writing, the capacitance between the floating gate electrode 6 and the channel forming region 3 is very small. Therefore, a large capacitive coupling between the floating gate electrode 6 and the control gate electrode 8 can be formed in a small area, and as a result,
Furthermore, high-speed writing is possible.

Next, an erase operation for extracting electrons from the floating gate electrode 6 will be explained.

The control gate electrode 8 is grounded and the erase voltage V is applied to the source region 2.
stC (approximately 10 V) is applied, and the electrons in the floating gate electrode 6 are extracted to the source region 2 via the gate insulating film 5 by a tunnel current.
It is sufficient to form a thin oxide film between layers. In the case of the semiconductor nonvolatile memory of the present invention, when an erase voltage is applied, the potential of the channel forming region 3 is floating, so that the source region 2
Junction leakage current is less likely to flow between the channel forming region 3 and the channel forming region 3. Therefore, it can be easily erased by the voltage generated by the booster circuit.

Table 1 shows the operating voltages for reading, writing, and erasing.

Table 1 Operation Table of Semiconductor Nonvolatile Memory FIG. 3 is a circuit diagram when the semiconductor nonvolatile memory of the present invention is arranged in an array. Any memory can be selected by connecting the drain region to the focus line, and connecting the control gate electrode and the selection gate electrode to form a word line.

The semiconductor nonvolatile memory of the present invention described so far uses a floating gate electrode as the charge storage layer, but
FIG. 4 shows an example using an insulating film.

That is, a gate insulating film 35 and a gate electrode 38 are formed on the channel forming region 3 . A nitride film is provided in the gate insulating film 35 as a charge storage layer.

Charge can be transferred into and out of the nitride film by applying high positive and negative voltages to the gate electrode 38 with respect to the source/drain regions.

〔Effect of the invention〕

As explained above, this invention provides a very thin silicon film on an insulating substrate, a channel formation region in the silicon film, and a floating gate electrode formed above the silicon film and a floating gate electrode formed below the silicon film. By controlling the selection gate electrode formed in the
This has the effect of facilitating high-speed reading.

FIG. 2 is a cross-sectional view of a semiconductor nonvolatile memory according to a second embodiment of the present invention.

・Insulating substrate ・N-type source region ・N-type drain region ・Floating gate electrode that's all Applicant: Seiko Electronics Industries Co., Ltd. Agent: Patent Attorney Takayoshi Hayashi

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor nonvolatile memory according to the present invention, and FIG. 2 is a sectional view of a conventional semiconductor nonvolatile memory. FIG. 3 is a circuit diagram of a semiconductor nonvolatile memory array of the present invention. Figure 4 Cow conductor 1,000 volatile met'J Figure 1 Conventional cow s 1,000 1f light pillar memory Figure 3

Claims (1)

[Claims] A semiconductor thin film is provided on an insulating film substrate, and the semiconductor thin film is composed of a source region and a drain region of a first conductivity type, and a channel forming region formed between the source region and the drain region. , a floating gate electrode provided on the channel forming region via a first gate insulating film, a control gate electrode provided on the floating gate electrode via a control gate insulating film, and a control gate electrode provided below the channel forming region. and a selection gate electrode provided through a second gate insulating film.