JPH03123083A - Semiconductor memory element - Google Patents

Abstract

PURPOSE:To enable data to be rewritten at a high speed and to make a rewrite voltage low so as to enable a memory element of this design to approximate to a RAM by a method wherein the memory element is so structured as to have a specific energy band diagram characteristic conforming to the structure of a semiconductor memory element in which data is electrically rewritable. CONSTITUTION:A first conductive region E is negatively biased, whereby electrons are injected from the first conductive region E into a carrier trapping region C taking advantage of the change of the conduction band end of a second wide gap region D in average gradient. Then, when the bias is removed from the region E, a band profile reverts as shown in the Figure, so that injected electrons can be kept in a well correspondent to the carrier trapping region C and a memory stored after one of binary logical values is written can be realized. On the contrary, when the first conductive region E is positively biased, holes are injected from the region E into the carrier trapping region C through the intermediary of the second wide gap region D to potentially neutralize the previously stored electrons. Thereafter, when the bias voltage is removed from the region E, a band profile reverts as shown in the Figure and the stored logical value is electrically erased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory element in which information can be electrically written and erased in terms of cross-sectional structure, that is, information can be electrically rewritten. EEPR, a semiconductor memory element
Although it conforms to the structure of OM or EAROM elements, it particularly increases the electrical writing and erasing speed of information (ultimately, the rewriting speed is the sum of both), and also lowers the rewriting voltage. The present invention relates to a semiconductor memory element that can be used as a dynamic RAM (DRAM) or similar, if necessary, and that can withstand ultra-miniaturization of individual elements as a result of future ultra-high integration densities.

[Prior Art] As is well known, in this type of information storage field, the elements used for storage are broadly divided into read-only memory (ROM) types and random access memory (RA) types.
M) type, but it is hoped that the two will be unified in the future.

In other words, in existing semiconductor memory devices, generally called EEPROMs and EAROMs, in which information can be written and erased electrically, the information writing speed or rewriting speed can be sufficiently increased, and the voltage required for this can be sufficiently increased. By reducing the voltage to a much lower level, such a device could replace currently used RAM devices, if necessary. In other words, if such an element is developed, it can be used as a circuit that can store information for a long period of time on a year-by-year basis, or as a circuit that requires random access. Both of these circuits can now be constructed arbitrarily, and the ripple effects of their rationality are immeasurable. Naturally, the RAM refresh circuit, backup battery circuit, etc. that are currently required become completely unnecessary.

On the other hand, if we consider existing DRAMs, this device stores information by selectively accumulating charge in a suitable capacitor means such as a MOS capacitor or a pn junction capacitor. The input and output is performed using a MOS transistor as a switch.

Therefore, a leakage current on the order of pA flows through the source and drain of a MOS transistor even when it is off, which changes the charge stored as information, making a refresh operation inevitable. As ultra-high integration densities are required based on design rules of sub-micron order or less, the charge storage capacity of capacitor means becomes extremely small, and as a result, information is buried in switching noise when it is not read out. I ended up
In addition, the memory retention time will be shortened, making it impossible to use the current configuration principle.

Furthermore, as a structural factor in achieving ultra-high integration density, in principle, such a RAM element has a three-element configuration consisting of a combination of at least one capacitor means and one switch means (transistor). However, if possible, we would like to configure a unit memory cell with elements.

Therefore, as mentioned at the beginning, EEPROMEPROM
The reality is that various studies have been carried out on lowering the structural voltage, but so far the results have remained at a level that cannot be applied to RAM devices.

Furthermore, EEFROMs will also be required to be further miniaturized in the future, so in addition to the electrical characteristics issues mentioned above such as higher speeds and lower voltages, there will also be a need for EEFROMs to withstand miniaturization. Development of a structure (that has sufficient information storage capacity even when miniaturized) and various other practical requirements, such as productivity, must also be taken into consideration.

Among these, recent research and publications that are considered to be related to the present invention are listed below. Semiconductor loading disclosed as an example, F, C
A novel floating-gate structure memory device' was disclosed by AP8S et al.

An announcement like a tail (IEEE ELECTRON)
DEVICE LETTER5, VOL, 9. No,
8. August 1988).

The former is mainly a device to achieve electrical functions equivalent to an insulating film required for integrated circuits using a semiconductor single crystal, and one example of this is a floating gate embedded in a single crystal layer. - Discloses a nonvolatile memory having a structure.

On the other hand, for the latter, although electrical rewriting was considered, it was not successful, and in the end, only electrical writing is possible, and erasing is done by light irradiation in a so-called EPROM structure, but the energy of the stacked structure related to the storage mechanism is・As a device for band diagrams, a slope is added to the conductor edge in a specific region, and when a bias voltage is applied, carriers (electrons)
Discloses a structure that is easy to inject.

[Problems to be Solved by the Invention] In the semiconductor device disclosed in the above-mentioned Japanese Patent Laid-Open No. 59-99754, it is possible to use a semiconductor single crystal instead of an insulating film to surround the floating gate. Although there are some advantages, such as the fact that there is no trapping in principle and the number of rewrites can be extremely large, the writing and rewriting mechanism itself is not much different from conventional floating gate devices. However, there was still room for further investigation into higher speeds and lower voltages.

On the other hand, although the latter floating gate devices such as F and CAPASSO contribute to faster writing, they have a fatal flaw in that rewriting cannot be performed electrically as described above.

The present invention was made under these circumstances, and as an important stepping stone in the research and device development processes that will lead to the complete conversion of EEPROMs to RAM in the future, the present invention is designed to The first objective was to provide a semiconductor memory element that could achieve higher speed and lower voltage than the conventional EEPROM element, and thereby could be used as a RAM.

Furthermore, even if the memory retention capacity of the EEPROM element is sacrificed to some extent, by increasing the speed and lowering the voltage as mentioned above, it will continue to function as it is if it is extremely miniaturized as mentioned above. The present invention aims to provide a semiconductor memory element that can be used satisfactorily in the future as a replacement for the existing DRAM element, which is clearly no longer available.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention first has the following basic structural configurations: ■-1: An energy band sandwiched between a first semiconductor region and a carrier trapping region. - A first wide gap region having at least a part of the band gap larger than the band gap of the carrier trapping region on the diadarum: 3 ■-2 2 Between the carrier trapping region and the first conductive region We propose a basic configuration comprising: a second wide gap region sandwiched therebetween, and having at least a part of the band gap region larger than the band gap of the carrier capture region on the energy band diaphragm;

Here, for convenience, let us assume that the structural basic component of the present invention consisting of the above-mentioned constituent elements ■-1 and -2 is called the basic structure ■, and then add the following constituent element ■ to the basic structure Invention.

■: The conduction band edge of the second wide gap region has a gradient in which the energy level increases as it approaches the carrier trapping region, and the valence band edge has a gradient in which the energy level decreases as it approaches the carrier trapping region.

However, throughout the entire text of this book, the term "gradient" related to the conduction band edge or valence band edge mentioned above refers to not only a continuous change in a linear or curved shape, but also a discontinuous change, such as a step-like change. 4 In short, there is a difference in energy level at the conduction band edge and valence band edge between the two ends of the region in question, and when viewed from a broader perspective, there is a gradient as a whole. It is an expression of a state that shows a change.

However, although the basic structure (2) remains the same, if the following constituent feature (2) is used in place of the constituent feature (1), the second invention of the present invention is obtained.

■: The conduction band edge of the first wide gap region has a gradient in which the energy level increases as it approaches the carrier trapping region, and the valence band edge has a gradient in which the energy level decreases as it approaches the carrier trapping region.

However, when this requirement (2) is combined, as will become clear later, carriers of the opposite sign (opposite polarity) to the conductivity type of the first semiconductor region must also be injected or drawn out from the side of the first semiconductor region, or Additionally, in order to make it possible to directly inject and extract bipolar carriers, in addition to the basic structural requirements ■-1 and ■-2 mentioned above, the following structural structural requirement ■-3 is also required. Become.

(3) A second conductive region that is in contact with one or both of the first wide gap region and the first semiconductor region, or is in contact with the first semiconductor region and faces the carrier trapping region.

In contrast, the above configuration requirements ■-1, ■-2 and configuration requirements ■
As in the case of the combination of , this second conductive region ■-3 can be combined with, but does not have to be an essential component, and instead of the component ■, the component ■-1, ■- 2
As other constituent elements that can be selectively combined with the above, the present invention further discloses the following constituent element groups (1), (2), (2), (2), (2), (2).

■: The conduction band edge of the first wide gap region has a gradient in which the energy level increases as it approaches the carrier trapping region; and the energy level of the conduction band edge of the second wide gap region increases as it moves away from the carrier trapping region. have an increasing gradient.

■ = The valence band edge of the first wide gap region has a gradient in which the energy level decreases as it approaches the carrier trapping region; and the valence band edge of the second wide gap region has a gradient that decreases as it moves away from the carrier trapping region. Having a gradient of decreasing energy level.

■: The conduction band edge of the first wide gap region has a gradient in which the energy level decreases as it approaches the carrier trapping region; and the conduction band edge of the second wide gap region has a gradient in which the energy level decreases as it moves away from the carrier trapping region. Having a gradient of decreasing levels.

■; The valence band edge of the first wide gap region has a gradient in which the energy level increases as it approaches the carrier trapping region; and the energy level of the valence band edge of the second wide gap region increases as it moves away from the carrier trapping region. - Having a gradient of increasing levels.

■: The valence band edge of the first wide gap region has a gradient in which the energy level decreases as it approaches the carrier trapping region; and the energy level of the conduction band edge of the second wide gap region decreases as it moves away from the carrier trapping region. 7. Having a gradient in which the GI level decreases.

■: The conduction band edge of the first wide gap region has a gradient in which the energy level increases as it approaches the carrier trapping region; and the valence band edge of the second wide gap region has a gradient in which the energy level increases as it moves away from the carrier trapping region. Having a gradient of increasing levels.

With such a group of constituent elements, the present invention further includes the above-mentioned constituent elements ■-1, ■-2, and any one of the above-mentioned constituent elements groups ■, ■, ■, ■, ■, ■. Six inventions are proposed that combine
, ■-2 and constituent feature ■, and also proposed an invention in which constituent feature ■-3, which was essential to satisfy the above constituent feature ■, was added to each of these inventions. The invention has the following constituent requirements ■-4, ■-
We also propose inventions that add one, two, or all of 5.-6.

-4: The first conductive region includes a pn junction in a broad sense formed in the thickness direction or in-plane direction.

8 (1)-5: A potential control region is formed to be electrically isolated from the first conductive region and controls the potential of the carrier trapping region.

■-〇2 On the side opposite to the side where the first semiconductor region and the first wide gap region are in contact, there is a third wide gap region in contact with the first semiconductor region and a third wide gap region in contact with the first semiconductor region. and a third conductive region provided in contact with the gap region.

Furthermore, in each of the inventions defined as above, at least the third constituent feature ■-6 regarding the third wide gap region and the third conductive region, and the constituent feature ■ that defines the second conductive region already mentioned -3, we propose an invention that further adds the following constituent feature (1)-7.

■-7: The second conductive region has a first part and a second part separated from each other, one of the first and second parts is used as a source, the other as a drain, and the third conductive region is Contains a field effect transistor structure as a gate.

[Function] In the most basic aspect of the present invention, which consists of constituent elements ■-1, ■-2, and Requirements■
Under such a bias, the conduction band edge of the second wide-gap region sloped with the relationship specified in
Using the change in the average gradient on the diadem, electrons can be injected into the carrier trapping region from the side of the first conductive region through the second wide gap region, and then,
If the bias is removed, one storage state of a binary logic value can be realized as a first electrical state in which electrons are trapped in the carrier trapping region.

In other words, this operation corresponds to writing one logical value of binary logical information, or if holes were captured before that, it is an operation to neutralize this. This corresponds to erasing or rewriting one logical value of value logical value information. As stated in advance, in the following, if one is a write operation, the other will simply be written as an erase operation, but as mentioned above, writing and erasing information can be defined interchangeably. When a certain logic value is converted into an electron or a hole and written into the carrier capture region, if carriers of opposite polarity were previously captured in the carrier capture region, the stored binary logic value will be erased. Otherwise, a rewrite operation will occur.

However, since the number or amount of carriers injected into the carrier trapping region can be made to show continuous changes, the semiconductor memory element of the present invention is essentially limited to the above binary logic operation. It can also be applied to multivalued logic operations or analog quantity storage operations, and this can also be understood from the configuration principle based on the explanation of the embodiments of the present invention described later, but here, a simple explanation will be given. Therefore, the explanation will be continued below using an example of binary logic operation.

Therefore, in the above configuration, when the first conductive region is relatively positively biased with respect to the carrier trapping region, the resulting change in the average slope of the valence band edge of the second wide gap region causes 10) Holes are injected from the conductive region through the second wide gap region into the carrier trapping region, and then, when the positive bias is removed, the other logic value of the binary logic information is written; A memory state is realized.

On the other hand, in view of the operation of the present invention consisting of the above-mentioned constituent elements ■-1, ■-2, ■-3, and ■, in the semiconductor memory element according to the present invention, the first semiconductor region is made of, for example, an n-type semiconductor. If so, by biasing the first semiconductor region relatively negatively with respect to the carrier trapping region, the conduction band of the first wide gap region sloped according to the relationship specified in the above structural requirement Injecting electrons into the carrier trapping region from the first semiconductor region side through the first wide gap region by utilizing the change in the average slope on the band diadem that the edge exhibits under such bias. Then, by removing the bias, a first binary logic value storage state in which electrons are trapped in the carrier trapping region can be realized.

However, when injecting 2 carriers of a conductivity type opposite to that of the first semiconductor region, for example, although a negative bias relative to the carrier trapping region is applied to the first semiconductor region in the above example, Alternatively, holes cannot be injected efficiently simply by applying a relatively positive bias. This is because, unlike the first conductive region in the first invention, the n-type semiconductor cannot supply both electrons and holes with the same efficiency.

However, in the case of the second invention, as mentioned above, the constituent requirement (1)-3 is essential, and the first semiconductor region can have a configuration in which the second conductive region is in contact with the first semiconductor region. When injecting carriers of opposite sign to the conductivity type (n-type or p-type) of the first semiconductor region, an inversion layer is formed by applying an appropriate bias to the first semiconductor region. By injecting carriers from the second conductive region, carriers of opposite sign can be indirectly injected into the carrier trapping region.

Further, according to the present invention, this second conductive region is configured to directly oppose the carrier trapping region via the first wide gap region (it is sufficient if there is at least a portion facing the carrier trapping region; carriers of the selected polarity are directly injected from this second conductive region depending on the polarity and appropriate magnitude of the bias applied to the second conductive region. You can also do that.

In this case, it is easy to understand if it is considered that the role played by the first conductive region in the first invention is played by the second conductive region in the second invention. Therefore, it is naturally possible to directly inject both carriers, electrons and holes, only from this second conductive region. Therefore, in this case, in principle, the first semiconductor region is injected directly into the second conductive region and carriers. It has the meaning of a substrate that physically supports the capture area and other areas.

However, as will be described later, it is possible to add a third wide gap region or a third conductive region, or to divide the first conductive region into a first part and a second part, and distribute one part to the source and drain. When used, the first semiconductor region is also used as an electrically functional region (for example, a region for forming a channel of a field effect transistor).

Next, an invention in which constituent feature ■-1 and ■-2 are combined with constituent feature ■ or In the inventions characterized in requirements (■) or (2), electrons or Holes can be injected, and then the bias can be removed to achieve a first logical value storage state, and then applying a relative positive or negative bias to the first conductive region can achieve the above In this way, the electrons or holes previously captured in the carrier trapping region can be taken out to the first conductive region side, so if the bias is then removed, the write storage state of other logical values or the stored state can be changed. It is possible to erase or rewrite a logical value.

5 In exactly the same way, for the constituent requirements ■-1 and ■-2 mentioned above,
In an invention that combines constituent feature ■ or ■, that is, an invention characterized in said constituent feature ■ or ■ with respect to the conduction band edge or valence band edge of the first and second wide gap regions, carrier capture By applying a negative or positive bias to the first conductive region relative to the region, electrons or holes can be injected from the first conductive region to the carrier trapping region, and then by removing the bias, the first conductive region can be injected. When a storage state of one logical value can be realized and then a relatively positive or negative bias is applied to the first semiconductor region, the electrons or holes previously captured in the carrier trapping region as described above are removed. Since it can be taken out to the first semiconductor region side, if the bias is removed afterwards,
It is possible to write and store other logical values, or to erase or rewrite stored logical values.

An invention that combines constituent feature ■ with constituent feature ■-h■-2 described above, that is, an invention that combines constituent feature ■ with regard to the conduction band edge or valence band edge of the first and second wide gear regions. In the characterized invention, by applying a relatively negative bias to the first conductive region with respect to the carrier trapping region, electrons can be injected from the first conductive region to the carrier trapping region, and then the bias is applied to the first conductive region. By removing , the storage state of the first logical value can be realized. Then, when a relatively positive bias is applied to the first semiconductor region, holes are injected from the side of the first semiconductor region, thereby injecting carriers. By neutralizing the electrons captured in the capture region or positively charging the carrier capture region, it becomes possible to erase or rewrite the stored information.

On the contrary, for the configuration requirements ■-1■-2 mentioned above,
In the invention combining constituent feature (2), holes can be injected from the first conductive region to the carrier trapping region by applying a positive bias to the first conductive region relative to the carrier trapping region, Thereafter, by removing the bias, the storage state of the first logical value can be realized, and then by applying a relatively negative bias to the first semiconductor region, electrons can be injected from the side of the first semiconductor region. The stored information can be erased or rewritten by neutralizing the holes trapped in the carrier trapping region or by negatively charging the carrier trapping region.

In addition to these inventions, in an invention that further adds the structural requirement (3) that specifies the structure of the second conductive region described above, injection into the carrier trapping region is performed according to the conductivity type of the first semiconductor region. Alternatively, when dealing with polar carriers that are difficult to take out from the carrier trapping region, the second conductive region can be conveniently used by the same mechanism as described above.

Furthermore, depending on the application of bias to the first conductive region, the first semiconductor region, or the second conductive region, for example, carriers injected into the carrier trapping region via the first or second wide gap region may be If there is a high probability that the leakage will occur through the second or first wide gap region under the application of the bias, the above-mentioned structural requirements -
By providing a potential control region defined according to No. 5, such inconvenience can be avoided.

For example, if we consider a configuration in which carriers are injected from the first conductive region to the carrier trapping region via the second wide gap region, if the second wide gap region is made of a semiconductor material, the high speed is quite high even if it is within the shell. However, if the first wide gap region is also composed of a semiconductor region, the carriers injected into the carrier trapping region will not remain here during the bias application process for the injection and will be reversed. In some cases, it may pass directly into the first semiconductor region or the second conductive region via the first wide gap region located on the side. In such a case, if there is a potential control region as described above, the potential of the carrier trapping region can be kept at least as low as possible during the injection operation by applying a bias with the opposite polarity to the injection bias, or by keeping the potential at the same potential as before injection. It is possible to prevent the change from occurring too much, and to effectively prevent the generation of carriers flowing out.

9 The same applies when extracting captured carriers from the carrier trapping region; for example, due to the bias relationship when extracting carriers to the second conductive region, carriers may be accidentally injected from the first conductive region through the second wide gap region. Therefore, overall, the existence of a potential control region that can control the potential of the carrier trapping region is the optimal writing or rewriting for each of the above-mentioned inventions. This works extremely effectively in realizing the potential relationship between the band and diadem.

Furthermore, to all the present inventions described so far, the above-mentioned constituent feature ■-6 is added, and on the side opposite to the side where the first semiconductor region and the first wide gap region are in contact, By providing a third wide gap region in contact with the first semiconductor region and a third conductive region in contact with the third wide gap region, carriers are captured in the carrier capture region when reading information. When the amount of charge fluctuates slightly, the effect of suppressing this can be obtained. This is because the presence of such a third conductive region of 0 allows the density of carriers (electrons or holes) in the first semiconductor region to be controlled.

In addition, in a configuration that has this constituent feature ■-6 and the above-mentioned constituent feature ■-3 regarding the second conductive region, the above-mentioned constituent feature ■-7, that is, the second conductive region It is separated into a first part and a second part, and these first part,
If the configuration includes a field effect transistor structure in which one of the second parts is a source and the other is a drain, and the third conductive region is a gate, selective storage and reading of information can be handled as a variable threshold element. Semiconductor memory elements can be constructed.

In other words, the threshold voltage of the drain current vs. gate voltage characteristic of this transistor structure changes depending on the polarity and amount of trapped charges in the carrier trapping region, so conversely,
The current memory contents of this element can be read from the threshold voltage value.

Note that in the semiconductor memory element of the present invention, a configuration in which writing or erasing time is shortened as described above can be easily obtained, but if this is done, carrier leakage may occur through the first or second wide gap region. There is also. In that case, it is sufficient to read the memory contents before they are completely erased, amplify the contents, and write them again, a so-called refresh operation. This also means that a DRAM of Of course, it has been confirmed that when a refresh operation is performed, a sufficient storage content retention time can be obtained even if a considerably high-speed semiconductor memory element is constructed according to the present invention.

[Example] FIG. 1 schematically shows a main part of a cross-sectional structure of a basic example of a semiconductor memory element of the present invention.

Above the first semiconductor region A, a first wide gap region B1 carrier trapping region C, a second wide gap region D,
A first conductive region E is laminated and a first semiconductor region A
In this case, a second conductive region F is also shown which faces and partially overlaps with the carrier trapping region C when viewed in plan.

Here, regarding the first and second wide gap regions B and D, the term "wide gap" refers to the relative energy and It means that at least a part of the band gap is larger than the band gap, and in the relationship between the first wide gap region B and the second wide gap region, there is a difference between them on the energy band diagram. Band profiles may be similar or different, as will be apparent in each of the embodiments described below.

In addition, in this semiconductor memory element, the flow of charge that should be noted in operation is the one that connects the first semiconductor region A (or second conductive region F) and first conductive region E in the cross-sectional structure shown in the first diagram. The region X surrounding both sides or the periphery of the carrier trapping region C along the in-plane direction, which is perpendicular to this direction, is made of the same material as the first wide gap region B;
The carrier trapping region C may be formed in the first wide gap region B, or may be made of the same material as the second wide gap region. The carrier trapping region C may be formed within the carrier trapping region C, but as long as the carrier trapping region C has a wider band gap than the carrier trapping region C, that is, the carrier trapping region C The layer region may have a composition or material different from that of the first and second wide gap regions B and D, as long as it can prevent charges from flowing out in the in-plane direction.

Further, the second conductive region F may be essential or vice versa depending on the characteristic configuration on the energy band diagram to be combined with the basic structural configuration shown in the first diagram. In principle, it may no longer be necessary.

However, even if it is unnecessary in principle, it may be better to provide it, and in that case, as shown by the imaginary line in FIG. The first part F- and the second part F- can be provided all around, or facing each other in the in-plane direction.
It may be provided in two parts. The first part F- and the second part F- may be used selectively, as will be described later, or in order to include a field effect transistor structure inside the semiconductor memory element of the present invention. ,
One side may be used as its source and the other as its drain.

However, with respect to the physical or geometrical structure shown in Figure 1, as described below with reference to Figure 2.3.4,
By combining any of the overall energy band diagram structures, it is possible to construct an embodiment element of the present invention, each having its own characteristics.

First, if we look at the energy band diagram shown in Figure 2A, we can see that the upper and lower (second
In the figure, the first and second wide gap regions B and D located on the left and right sides (as they are shown lying horizontally) both have a wider band gap portion than the carrier trapping region C. In particular, in the second wide gap region, both the conduction band edge CB and the valence band #VB have a slope, and the energy band gap on the side closer to the carrier trapping region C is higher than that in the first conductive region E. The side closest to it has a larger f.

However, the gradient shape of the band profile of the conduction band edge CB and the valence band edge VB in the second wide gap region is a nearly linear continuously changing shape, as shown by the solid line in the figure. The virtual line C shown in the diagram
As shown by B' and VB', the change may be discontinuous, such as a stepwise change.

Furthermore, with respect to the conduction band edge and valence band edge of the first conductive region E, the conduction band edge and valence band edge of the second wide gap region B are also
Both have shapes that connect smoothly, but there may be a step here that does not pose a problem in terms of operation, which will be described later, or conversely, there may be a step between the conduction f@ of the carrier trapping region C and the valence band edge. Although the part has a steep stepped shape in the figure, it may have a slightly slanted shape.

Conduction band edge and valence band edge CB' indicated by these virtual lines
, VB' and the above descriptions may be considered in exactly the same way in other embodiments to be described later. This also applies to embodiments in which the above-mentioned gradient is provided with respect to the conduction band edge and valence band edge of the first wide gap region B.

In any case, in the device according to the first embodiment of the present invention, which has a cross-sectional structure as shown in the first figure and an energy band diagram as shown in the second figure, the first conductive region E is negatively biased. Taking advantage of the bending of the band profile of the second wide gap region, especially the change in the average slope of its conduction band edge, electrons can be injected from the first conductive region E into the carrier trapping region C, and then, If the bias is removed, the band profile returns to the one shown in Figure 2A, so the injected electrons can be retained in the well corresponding to the portion of the carrier trapping region C sandwiched between the regions B and D, which have wide gaps on both sides. As the first electrical state in the carrier capture region C, a state in which one of the binary logic values is written and then stored can be realized.

On the other hand, when the first conductive region E is biased in the positive direction, holes can be injected from the first conductive region E into the carrier trapping region C via the second wide gap region. Therefore, if the electrons were previously accumulated as described above, the electrical state in the carrier trapping region C can be changed to the second state by neutralizing them electrically. , then the first conductive region Ek
``If the relatively applied positive bias is removed, the second electrical state can be maintained by returning to the band profile shape shown in Figure 2A.

This ends up being an electrical erasing operation of the stored logic value, and from the above definition, also a rewriting operation. Of course, as already defined, if holes are written first, then the electron injection operation corresponds to the erasing or rewriting operation of the information logic.

Furthermore, since the number or amount of carriers captured by the carrier capture region can be made to change continuously, the device of the present invention can also be used to store multivalued logical information or analog quantitative information. . These points also apply to all of the following embodiments, so they will not be repeated.

By the way, as seen in the first embodiment of the present invention,
Naturally, when electrons and holes are selectively injected from the first conductive region E to the carrier trapping region C as necessary,
The first conductive region E must be capable of supplying both electrons and holes.

However, this is not difficult, and the first conductive region E
A metal may be selected as the material or composition of the carrier, or a narrow gap semiconductor may be selected in which a large number of both carriers exist at least at the operating temperature of this device.

On the other hand, when a semiconductor with an energy band gap of around 1 eV to 2 eV is used as the first conductive region E, a structure having at least one p-n junction in a broad sense in the thickness direction or in-plane direction is used. Alternatively, if the structure is a combination of a semiconductor layer that is sufficiently thin to form a depletion layer in the operating state and a metal formed thereon, a structure that can similarly supply both carriers can be realized.

A pn junction in a broad sense is a concept that also includes rectifying junctions such as pin junctions, as can be seen in the examples described later.

Also, as is clear, in the device of the first embodiment of the present invention, as long as the basic operation as described above is satisfied,
In the first illustrated structure, the second conductive region F is not required. just,
Although this is common to some of the other embodiments described later, this can be used significantly, and simply put, for example, when the first semiconductor region A is connected to a general ground potential. Alternatively, if a potential is intentionally applied, this second conductive region F (including F-, p-, etc.) can be used as a region for electrical connection to the external power supply circuit or other circuits. Alternatively, by controlling the potential of the first semiconductor region A or carrier trapping region C from the side opposite to the first conductive region E as necessary, it is used to optimize the operation during carrier injection. You can also do that. Regarding this point as well, in the examples described below, this second conductive region F
The same consideration can be given to embodiments in which the above is not an essential component.

FIG. 2B shows that even though the static cross-sectional structure is as shown in FIG. 1, other structures that can be combined with the basic structure instead of the energy band profile shown in FIG. It shows the energy band profile of the shape.

In other words, the energy of the carrier capture region C sandwiched between
In contrast to the band gap, both wide energy bands and
Among the first and second wide gap regions B and D having a gap, the first wide gap region B near the first semiconductor region A has a slope with respect to the conduction band edge and valence band edge. It has become. Virtual line conduction band edge, valence band edge CB', VB
The explanation of the gradient shape itself, including ``, refers to the previous explanation.

In the example element having such an energy band profile, if the first semiconductor region A is, for example, an n-type semiconductor, the band bending of the first wide gap region B can be caused by applying a negative bias of 1. In particular, electrons can be injected into the carrier trapping region C by utilizing the change in the average slope of the conduction band edge CB; By doing so, one hole can be injected into the capture region C by utilizing the bending of the band in the band region B, especially the change in the average slope of the valence band edge VB. .

However, carriers having a polarity opposite to that of the conductivity type of the first semiconductor region A cannot generally be injected into the carrier trapping region with an efficiency comparable to that of injecting carriers of the same polarity. Therefore, the energy shown in Figure 2B
In the device according to the invention having a band profile, the second conductive region F shown in the first illustrated structure is essential.

If this second conductive region F exists, for example, carriers having a polarity opposite to the conductivity type of the first semiconductor region A can be transferred to the carrier trapping region F.
When injecting carriers into the first semiconductor region A or the first conductive region E, an appropriate bias 2 is applied to the first semiconductor region A or the first conductive region E to form an inversion layer, and then the carriers of opposite polarity are injected into this inversion layer from the second conductive region F. can,
As expected, the reverse polarity gear 1-rear can be injected into the carrier capture area C.

Of course, for both electrons and holes, if the bias required for the injection is removed after the injection operation (information writing or erasing operation, or rewriting operation) is completed, the result will be as shown in Figure 2B. It returns to the energy band profile and enters the information storage state.

Furthermore, if the energy band profile shown in Figure 2B is satisfied in relation to the second conductive region F, a configuration is obtained in which both electrons and holes are injected from the second conductive region F. be able to.

In this case, as in the case where both electrons and holes are selectively injected from the first conductive region E mentioned above, the second conductive region F performs the function performed by the first conductive region E. Therefore, the second conductive region F is made of a narrow gap semiconductor in which a large number of bipolar carriers can exist at least at the operating temperature, or made of a metal,
Alternatively, by constructing the semiconductor with impurities added to such an extent that it becomes degenerate, carrier injection may be performed by the tunnel effect.

Of course, in order to satisfy the operation of directly injecting carriers from the second conductive region F, at least a part of the second conductive region F is in contact with the first semiconductor region A, but the carrier trapping region C is formed in the thickness direction. must be facing below.

The energy band profile shown in Figure 3A is the first
It is shown in other embodiments of the present invention that can be adopted with the illustrated cross-sectional structure, and the energy level of the conduction band edge of the first semiconductor region A or the second conductive region F is The first wide gap region B has a conduction band edge CB whose energy level gradually increases as it moves away from the second conductive region F, and the energy level at the conduction band edge of the carrier trapping region C. On the other hand, the further away from the carrier capture area C, the higher the energy level gradually becomes.
cBe, Zi:E-Y w y jflI* D h<
"*"js,.

It is.

However, these first and second wide gap regions B.

Regarding the valence band edge VB of D, there is no particular necessary limitation, and those of the first semiconductor region A or the second conductive region F,
In addition to having a flat relationship with that of the carrier capture area C, as shown by virtual lines VB' and VB'' in the same figure,
It may have a continuous or discontinuous gradient. This also applies to the energy band profile shown in Figure 4A, which will be described later.

However, in the device of the present invention having the energy band profile shown in Figure 3A, when the first semiconductor region A or the second conductive region F is biased in the negative direction, the average conduction band edge CB of the first wide gap region B Due to the change in the gradient, electrons can be injected into the carrier trapping region C,
Then apply bias? If you stop, carrier capture area C
It is possible to realize an electron accumulation state corresponding to one of the logical value write states in the memory. 5. Next, when the first conductive region E is biased in the positive direction, the electrons in the capture region C that have been injected and held in the above manner are transferred to the second wide gap region by applying the bias. Due to the change in the average slope of the conduction band edge CB, it can be pulled out to the side of the first conductive region E, and the information can be erased or the second logical value can be written. can.

The i3B illustrated energy band profile is the first
It shows a further embodiment of the present invention that can be employed with the illustrated cross-sectional structure, and shows that the energy level of the valence band edge of the first semiconductor region A or the second conductive region F is or a first wide gap region B having a valence band edge VB whose energy level gradually decreases with a gradient as it moves away from the second conductive region F;
A second method gap having a valence band edge VB whose energy level gradually decreases with a gradient as the distance from the carrier trapping region C increases relative to the energy level of the valence band of the carrier trapping region C. 6 area is shown.

However, these first and second wide gap regions B.

Regarding the conduction band edge 08 of D, there is no particular necessary limitation.
In addition to having a flat relationship with those of the first semiconductor region A or the second conductive region F or the carrier trapping region C, as shown by virtual lines CB' and f:B'' in the figure,
It may have a continuous or discontinuous gradient. This also applies to the energy band profile shown in Figure 4B, which will be described later.

In the device according to the present invention having such an energy band profile as shown in Figure 3B, when the first semiconductor region A or the second conductive region F is biased in the positive direction, the valence band edge VB of the first wide gap region B Holes can be injected into the carrier trapping region C by changing the average slope of , and if the bias is then stopped, holes corresponding to one logic value writing state will be injected into the carrier trapping region C. An accumulation state can be achieved.

Next, when the second conductive region E is biased in the negative direction, the holes in the capture region C that have been injected and held as described above are transferred to the second wide gap region due to the application of the bias. By changing the average slope of the valence band edge VB, it can be drawn out to the side of the second conductive region E, and this can erase information or write a second logical value. .

Figures 4A and 4B each illustrate yet another energy band profile disclosed in the present invention.

In the case of FIG. 4A, the energy level of the conduction band edge of the first semiconductor region A or the second conductive region F has a gradient that gradually increases as it approaches the first semiconductor region A or the second conductive region F. The first wide gap region B has a conduction band edge CB whose energy level increases as the energy level increases, and the energy level of the conduction band edge of the carrier trapping region C gradually increases as the energy level approaches the carrier trapping region C. A second wide gap region with a conduction band edge CB whose energy level increases with a gradient is shown, and conversely, in the case shown in 4B, the gradient with respect to the valence band edge VB is shown. administered,
With respect to the energy level of the valence band edge of the first semiconductor region A or the second conductive region F, the energy level gradually increases as it approaches the first semiconductor region A or the second conductive region F. With respect to the energy level of the valence band in the first wide gap region B, which has a valence band edge VB that becomes lower, and the carrier trapping region C, the energy level gradually increases as it approaches the carrier trapping region. - A second wide gap region is shown with the valence band edge VB decreasing in level.

Therefore, in the case shown in 4A, by applying a negative bias to the first conductive region E, electrons can be transferred to the 4B
In the illustrated case, by applying a positive bias to the first conductive region E, holes can be injected into the carrier trapping region C through the second wide gap region, respectively. By applying a positive bias in the case shown in 4A and a negative bias in the case shown in 4B to the semiconductor region A or the second conductive region F, via the first 9 wide gap region B, The carriers captured in the carrier capture area C can be drawn out to the first half-capture area A or the second conductive area F.

FIGS. 5A and 5B show yet another energy band profile applicable to the device according to the embodiment of the present invention.

In the case of FIG. 5A, the valence band #VB of the first wide gap region B and the conduction band edge CB of the second wide gap region are noteworthy; The edge VB has a gradient in which the energy level decreases as it approaches the carrier trapping region C, and the conduction band edge CB in the second wide gap region has a gradient in which the energy level increases as it approaches the carrier trapping region C. ing.

As mentioned above, each gradient is not continuous, but shows discontinuous changes such as steps, as shown by virtual lines VB' and CB' in the figure. Moreover, there is no particular limitation on the shape of the conduction band edge of the first wide gap region B, which is not being focused on, and the valence band edge of the second method 0 gap region. It is also possible to have a slope like this, as shown by virtual lines CB" and VB", respectively.
It may be flat.

On the other hand, in the case shown in Figure 5B, the conduction band edge CB of the first wide gap region B and the valence band edge VB of the second wide gap region
is involved in the selective injection operation of positive and negative carriers, and the conduction band edge CD of the first wide gap region B has a gradient in which the energy level increases as it approaches the carrier trapping region C, and the value of the second wide gap region increases. The electron band edge VB is the carrier trapping region C
There is a gradient in which the energy level decreases as it approaches .

In addition, the virtual line V shown in FIG. 5B
B', CB', CB", VB" 1. : Tweets can be thought of in the same way as in Figure 5A above.

If the semiconductor memory element of the present invention has such a band diaphragm, as is already clear from the above explanation, a negative bias is applied to the first conductive region E in the case shown in FIG. 5A. By applying a positive bias to the first semiconductor region A or the second conductive region F, holes can be transmitted through the first wide gap region B. Holes can be selectively injected into the carrier trapping region C, respectively, and in the case shown in Figure 5B, by applying a positive bias to the first conductive region E, holes can be injected through the second wide gap region. First semiconductor area A
Alternatively, by applying a negative bias to the second conductive region F, electrons can be injected into the respective carrier trapping regions C via the first wide gap region B.

By the way, when the first and second wide gap regions B and D are used alternately to write different logical values as in the example device shown in Figure 3.4.5 above, it is also particularly 4th A
, B. As is evident in the case where carrier injection is expected from the first conductive region E in the illustrated embodiment, the carrier injection speed is high and desirable. If region B is left as it is, a change in the average slope will occur at the conduction band edge CB or valence band edge VB, so a bias of a predetermined polarity and magnitude is applied to the first conductive region E to capture carriers from there. When carriers are injected into the region C, the freshly injected carriers may flow out into the first semiconductor region A or the second conductive region F via the first wide gap region B.

Therefore, in order to prevent such inconveniences, it is advantageous to also employ a configuration as shown in FIG. 6, for example.

That is, a potential control region G that can control the potential of the carrier trapping region C is provided.

In the illustrated case, this potential control region G is located on the first wide gap region, facing the carrier trapping region C in the thickness direction, and via the potential separation region H in the in-plane direction, It is configured to face the first conductive region E.

If such a potential control region G is provided, a bias of a predetermined polarity and a predetermined magnitude is applied to the first conductive region, and carriers of a polarity selected from there are generated according to the mechanism described above. When entering the carrier trapping region C via the second wide gap region, a potential with the opposite polarity to that of the carrier trapping region C is applied to the potential control region G, or a potential with a polarity opposite to that of the carrier trapping region C is applied before the injection or operation starts. An unchanging potential can be applied, and by doing so, the potential of the global portion of the carrier trapping region C can be made to at least not change much with respect to the previous one, so that during the carrier injection operation, the first The amount of charge leaking toward the semiconductor region A or the second conductive region F can thus be significantly reduced.

Note that, as in the illustrated case, when the potential control region G and the first conductive region E are provided at the same lamination level in the laminated structure of the present device via the potential separation region H, the illustrated Accordingly, the area of the potential control region G that controls the potential of the carrier trapping region C is increased, and the area of the potential control region G that controls the potential of the carrier trapping region C is increased.
It is common practice to reduce the area of the first conductive region E for injecting carriers. The potential control region G cannot effectively control the potential unless it faces the carrier trapping region C in its global area, and the first conductive region E, which is the region for carrier injection, is As long as there is even a small part that faces the carrier capture area C, it can satisfy the function required of this area E, and even if it is minute in area, it is usually of no use. That's because there isn't.

However, these potential control region G and first conductive region E are
There is no reason why they must coexist at the same lamination level in the laminated structure of this device, and they can be electrically separated by sandwiching a wide gear area layer (not shown) between them along the thickness direction. In the first place, the potential control region G and the carrier trapping region C may be opposed to each other not with the second wide gap region layer interposed therebetween, but through another wide gap region.

Further, as shown in the figure, when the potential control region G and the first conductive region E are separated in the in-plane direction by a separation region H, in addition to the case where the separation region H is formed of an insulating film, both In addition, regarding the extraction of carriers in the lateral direction (in-plane direction) such that a reverse bias occurs in each potential relationship selectively applied during carrier injection operation between regions G and E, first semiconductor region A is Although an embodiment has been described for drawing out the second conductive region F, this also applies in particular to the third conductive region F.
．． 4. When the band profile is as shown in the illustrated embodiment, carriers are drawn out to the second conductive region F that faces the carrier trapping region C in a slightly overlapping relationship as shown in the first diagram. (In other words, assuming that the band profile shown in Figure 3.4 is that of the portion passing through the second conductive region F), similarly, unexpected carriers from the first conductive region E on the opposite side across the carrier trapping region C. Injection can be suppressed.

Of course, the potential control region G can be used more actively, not only to control the potential difference between the carrier trapping region C and the first conductive region E, but also to control the potential difference between the carrier trapping region C and the first conductive region E. , also in embodiments in which one of the bipolar carriers is selectively injected using only the first conductive region E, or only the first semiconductor region A or the second conductive region F,
1) It can be effectively used to provide an optimal shape for the band profile during injection.

As described above, in each of the embodiments of the present invention, one of the basic effects of the present invention is that although it is structurally similar to the existing EEPROME structure, it is operationally similar to the DRA.
A semiconductor memory element is obtained in which information can be easily written and rewritten to the extent that M-like operation is possible, and in particular, if semiconductors are selected for the first and second wide gap regions B and D, the speed increase is further promoted.
Further, the limit value for the number of rewrites can be set to a large number.

However, in other words, the first and second wide gap regions B and D
Even if C is an insulating member, it is acceptable because it is theoretically easier to rewrite electrical information compared to conventional elements of this type. When providing the control region G or exchanging carriers with the second conductive region F, it is necessary to use a semiconductor, metal, or other material with appropriate conductivity.
In other cases, it is not particularly necessary to have conductivity in the in-plane direction.

Furthermore, as is clear from the above-mentioned principle of operation, the semiconductor memory element of the present invention is particularly resistant to miniaturization or ultra-miniaturization. This is because information charges are not stored in the capacitor component, unlike the DRAM elements provided so far.

However, since the semiconductor memory element of the present invention can be easily rewritten in this way, when reading the memory content by applying a bias to the first conductive region E, for example, the semiconductor memory element of the present invention is in charge of the memory content. There is a risk that the charge in the carrier trapping region C may vary, even if only slightly. This also reduces the non-volatile performance that this element has in principle and structure.

Therefore, if such a problem occurs, it is effective to add a configuration as shown in FIG. 7 to the embodiments described so far.

In FIG. 7, the first wide gap region B is in contact with the first semiconductor region A on the side opposite to the side on which the first wide gap region B is provided, and a band larger than the energy band 8 gap of the first semiconductor region A is formed. Third wide gap region with a gap (can be made of insulator or semiconductor material)■
is provided, and further on this third wide gap region I,
A third conductive region J is provided at a position that has an electric field control effect on a portion of the first semiconductor region A that faces the carrier trapping region C.

With this configuration, the carrier density in the first semiconductor region A can be controlled depending on the potential applied to the third conductive region J, so that the memory content stored in the carrier trapping region C can be controlled. can be read.

Of course, although not shown in FIG. 7, a combination configuration with the embodiment shown in FIG. 6 is possible, and the second conductive region F
Furthermore, a cross-sectional structure having a first portion F- and a second portion F-2 can also be applied as the second conductive region F.

Conversely, when the second conductive region F is provided with a first portion F- and a second portion F-2 that are electrically isolated from each other, a cross-sectional structure as shown in FIG. 8 can be obtained. A semiconductor memory element including therein a field effect transistor structure K having one of the first portion F- and the second portion F-2 as a source, the other as a drain, and the third conductive region J described above as a gate. Obtainable.

In this case, it is clear that the threshold voltage on the drain current vs. gate voltage characteristic of a field effect transistor naturally depends on the polarity of the carriers captured in the carrier trapping region C. It depends on the quantity. Therefore, by having a field effect transistor K with a variable threshold value, it is possible to read out the storage contents in the carrier trapping region C to the outside without causing an undesirable change in the amount of captured carriers in the carrier trapping region C. becomes possible.

In practice, if the thickness of the first semiconductor region A and the first and third wide gap regions B and I is reduced to the order of 100 in a compact configuration, the first portion i in the second conductive region F, .
Even if the distance between the second portion F-2 is similarly reduced to the order of 100 people, the desired transistor operation can be expected, and in the end, an ultra-fine semiconductor memory element with a planar dimension on the order of 100 people can be realized. becomes possible.

Regarding each of the embodiments of the present invention described above, the combination of materials necessary to construct them is, in principle, arbitrary, and various combinations are conceivable; for example, GaAs
, a combination of so-called III-V group compound semiconductor materials such as AlGaAs, hydrogenated amorphous silicon (a-5t:H) and hydrogenated amorphous silicon.
Combinations of hydrogenated tetrahedral amorphous semiconductors such as carbide (a-5iC:H) and crystalline silicon are easy to produce and have high reproducibility and reliability.

When using a combination of H[-V group compound semiconductor materials, GaAs is used in the first semiconductor region A and carrier trapping region C.
Using the first and second wide gap region layers.

It is conceivable to use AlGaAs for one or both of D (at least the one that requires grading at the conduction band edge or valence band edge). In this case, if the composition ratio X in ^1xGa+-x8S, which uses AlGaAs in general notation, is changed along the thickness direction of the region layer to be created, the energy band gap will change. Also, electronic,
Since the barrier to holes (the positions of the conduction band edge and valence band edge on the energy band diagram) also changes, the energy band profile described earlier with reference to Figures 2 to 5 is as follows: Of course, any of the above can be realized.

It is well known that a GaAs layer or an AlGaAs layer can be formed by vapor phase epitaxy, liquid phase epitaxy, molecular beam epitaxy, metal organic vapor phase epitaxy, or the like.

In the combination of a hydrogenated tetrahedral amorphous semiconductor and crystalline silicon, crystalline silicon is used for the first semiconductor region A, and at least the conduction band edge or valence band edge is formed in the first and second wide gap regions B and D. hydrogenated amorphous silicon carbide (a-5iC:H) or hydrogenated amorphous silicon nitride (a-5iN+8) for those who require grading for carrier trapping region C; Silicon (a-5i:H) or hydrogenated amorphous silicon germanium (a-5i:H)
5jGe:H) may be used. Hydrogenated amorphous silicon carbide (a-54C:H) and hydrogenated amorphous silicon nitride (a-5
iN:H), the energy band and
Since the gap and the barrier to electrons and holes (the positions of the conduction band edge and valence band edge) change, we can use this fact to apply any of the structures shown in Figures 2 to 5. , the energy band profile disclosed in the present invention can be obtained.

Each region layer made of these hydrogenated tetrahedral amorphous semiconductors can be fabricated using glow discharge decomposition, photo-CVD, or thermal CVD.
It can be created with D.

From FIG. 9 onward, examples of fabricating a semiconductor memory element constructed according to the present invention will be explained together with the disclosure of specific material examples as described above, to further aid in understanding the present invention.

FIGS. 9A to 9F show the case where an element according to an embodiment of the present invention is made using GaAs-based materials.

First, as shown in FIG. 9A, after cleaning the surface of the insulating GaAs substrate 1 and performing etching or surface treatment in an epitaxial growth apparatus, a first semiconductor layer 10A is formed with a low impurity concentration GaAs to a thickness of approximately 1000 nm. Form as layers. As a result of subsequent steps, a portion of this first semiconductor layer 10A becomes the first semiconductor region A described above.

Subsequently, about 1000 people A
I) Grow as a (Ga, -XAs layer. At this time,
The composition ratio X suddenly changes from O to 0.4 at the interface of the GaAs substrate.
X is then gradually decreased. In this way, an energy band profile relationship as shown in FIG. 4A is obtained between the first semiconductor region or the second conductive region F and the first wide gap region B. In particular, in this example element, as described later,
Since the carrier trapping region is made of GaAs, x=0
．． The height of the barrier on the conduction band end side formed in the first wide gap region B in the portion 4 when viewed from the carrier trapping region is approximately 0.3 eV.

On the first wide gap region layer 20A, in order to form a layer that will become a conductive carrier trapping region C in the future, a GaA film doped with 10'5 to 1016 pieces/cm3 of silicon is formed.
The S layer will grow to a depth of approximately 308 people.

Next, as shown in FIG. 9B, the photoresists 3, 3
G covers the field portion and the GaAs layer 308 etched into a prescribed shape, and a first portion F- is formed by dividing the second conductive region F in the embodiments described up to FIG.
In order to form a region 11 corresponding to , and a region 12 corresponding to the second portion F-, ion implantation is performed as schematically indicated by arrows. The implanted atoms are in both regions 1
1. Select a material, such as a silicon atom, which controls the region portion 10 corresponding to the first semiconductor region A to be n-type between 1.12 and 1.12.

Thereafter, the photoresists 3 and 3G are removed and cleaned from step 5, and if necessary, heat treatment is performed in an As atmosphere to anneal crystal defects generated by ion implantation.

Thereafter, as shown in FIG. 9C, element isolation regions 13 and 14 as shown by imaginary lines are formed outside the conductive regions 11 and 12, if necessary. This can be formed by a method such as removing the photoresist 3.3G and implanting Ar ions or the like into the portions to be the regions 13 and 14 to make the GaAs region layer 10A high in resistance. .

When these interelement isolation regions 13 and 14 are formed, the photoresist used therein is removed and the substrate surface is cleaned, and then the second wide gap region that will form the second wide gap region in the future is The gap region layer 40A is made of AI, Ga+-, A
It is grown epitaxially as an s layer.

At this time, it is desirable to slightly etch the surface of the substrate in the same chamber in which the epitaxial growth is performed, so that in the step shown in FIG. As shown in , it is preferable to leave about 50 GaAs layers remaining.

During the epitaxial growth of the second wide gap region layer 40A in this manner, the composition ratio y of the AI, Ga1-, and As layers was initially changed rapidly from 0 to 0.4, and then,
By gradually decreasing the band profile in the thickness direction, the band profile for the second wide gap region in the embodiment shown in FIG. 4A is obtained. However, the composition ratio X or the manner of its change regarding the first wide gap region layer 208 and the composition ratio y or the manner of its change regarding the second wide gap region layer 40^ may be different even if they are the same. Also good.

Subsequently, on this second wide gap region layer 40, in order to form the first conductive region E and the potential control region G of the carrier trapping region in the future, atoms that will become donors for GaAs, e.g. The conductive layer 50A is epitaxially grown while adding silicon atoms at loI7 to 1619/cI113.

Next, as shown in FIG. 9D, the GaAs conductive layer 50A is selectively etched using existing lithography technology to form a conductive region 50 corresponding to the first conductive region E and a conductive region 50 as shown in FIG. 9F, which will be described later. As shown in FIG. 9, a conductive region 52 (not shown in FIG. 9D) corresponding to a potential control region G is formed in a juxtaposed relationship with this first conductive region E in the same plane (within the same lamination level). Furthermore, a first wide gap region layer 20A and a second wide gap region layer 40 are formed on each conductive region 11.12 corresponding to the first portion F- and second portion F-2 of the second conductive region F, respectively. Contact holes for each of the conductive regions 11 and 12 are opened using existing lithography technology. At this time, carrier capture area C
The layer region 30 that has already been formed is sandwiched in the thickness direction between the layer region 20 corresponding to the first wide gap region B and the layer region 40 corresponding to the second wide gap region B.
In this embodiment, the periphery is the second wide gap region 40
surrounded by However, as mentioned above, the peripheral portion of the carrier capture region C (30) may be surrounded by the first wide gap region 20, and the first and second wide gap regions 20 and 40 may be It may be surrounded by wide gap regions of different materials.

After this step, as shown in FIG. 9E, the substrate 1
The upper element surface is covered with an insulating film such as a silicon nitride film, and the surfaces of conductive regions 11 and 12 constituting the first and second portions F-, F-2 of the second conductive region F, respectively, and the first conductive region Contact holes are made to expose the surfaces of the conductive region 50 constituting the region E and the conductive region 52 (FIG. 9F) constituting the potential control region G, and lead electrodes 71 and 72 are formed in each of them using a metal thin film or the like. , 75, 76 (electrode 76 is shown in FIG. 9F) are provided.

A plan view of an example element of the present invention created in this way is shown in FIG. 9F, but conversely, each cross-sectional view of FIG. 9ANE used in the explanation so far is shown in FIG. In the middle, it can be considered that it is along the cross-sectional line α-α shown by the imaginary line.

As shown in FIG. 9F, in this example element, the occupied plane area of the first conductive layer 9 region A (50) used for injecting or extracting carriers into the carrier trapping region C (30) , potential control region G (5'2) that controls the potential of carrier trapping region C (30)
1 is formed so that the occupied plane area is larger than that of the other parts. The reason why it is desirable to do this has already been stated, so a repeated explanation will be omitted.

The semiconductor memory element of the present invention shown in FIGS. 9E and 9F is as follows:
It satisfies the energy band diagram shown in Figure 4A and has a structure corresponding to the cross-sectional structure shown in Figure 6, but also,
By using the potential control region 52 as a gate, the conductive region 11 as a source, and the conductive region 12 as a drain, it can also be used as a field effect transistor having a memory function. In that case, the layer corresponding to the first semiconductor region A Region 10 becomes a region for forming a channel of the field effect transistor. However, as mentioned above, the regions 20 and 40 corresponding to the first and second wide gap regions B and D are both made of AlGaAs.
If the memory is made of a type of material, the ability to retain memory contents is inferior to that of an insulating film, so a refresh operation is generally required.

FIG. 10A shows an embodiment in which a read-only gate is further provided for the elements of the embodiments shown in FIGS. 9E and 9F.

In the case of this element, a region 10 corresponding to the first semiconductor region A and a region 11 corresponding to the first and second portions F-1 and F-2 of the second conductive region F in the structure shown in FIGS. .1
2, a layer region 130 corresponding to the third wide gap region I, and a lower gate 1 corresponding to the third conductive region J.
10, and its cross-sectional structure is a combination of the structure of the sixth illustrated embodiment and the seventh illustrated embodiment, and the lower gate 11i) is used as a read-only gate. be.

Therefore, the first half of the example of creating this structure is No. 10B,
This can be explained with reference to Fig. C. On an insulating GaAs substrate 1 similar to that used in the embodiment shown in Fig. 9, a buffer layer is formed by gradually decreasing the Ga composition ratio from 1 to 1 Ga. After forming a thin layer of AlAs, an AlAs layer region of approximately 5,000 layers is heteroepitaxially grown as a first separation layer region 100, and A1.4Ga, .
The aAs layer 120 is heteroepitaxially grown to a thickness of about 500 nm, and an opening is made in this layer region 120 by lithography in a region where the lower gate 110 corresponding to the third conductive region J will be formed in the future.

Next, after cleaning the surface of the structure up to this point and slightly etching the surface by in-situ etch back in an epitaxial device, about 500 layers of n" type GaAsN11O were etched. When organic 11i111A such as a photoresist is grown by heteroepitaxial growth, an organic 11i111A such as a photoresist is spin-coated, and only the flat part of the applied organic 11jllll^ is vapor-phase etched, the surrounding area is an n1 type GaAs layer 11.
The organic film component 111 remains only in the recess surrounded by 0A.

Using this remaining organic film 111 as a mask, n + GaA
When selectively etching s[110A, as shown in the tOC diagram, the surface becomes almost flat with the A1°4Ga, 6As layer 120, and the lower gate corresponding to the third conductive region J in FIG. 110 is configured.

After that, the structure thus far was subjected to surface cleaning, and after the surface was slightly etched by in-situ etch back in the epitaxial device, Alo
, 7 Gao, sAs layer 130 is heteroepitaxially grown to a thickness of about 500 nm, and Alo
4Gao and 6ASjl140 are heteroepitaxially grown over a thickness of about 1,000 layers.

Lithography is applied to the Alo, aGao, and sAs layer regions 140 to form a layer region 10 corresponding to the first semiconductor region A and first and second portions F-, F- of the second conductive region F in the future. After making an opening in a portion corresponding to the area that should constitute the conductive regions 11 and 12 corresponding to 2, the layer region 14 is formed by the same procedure as shown in FIG. 10B.
0 and the surface is almost flat, so the low impurity concentration layer region 1
Forms 0A.

After this, by applying the same steps as already shown in FIGS. 9A to 9E, it is possible to obtain the structure of another example element of the present invention, as shown in FIG. 10A. As already mentioned, this structure has a cross-sectional structure that is a combination of the structure shown in Figure 6 and the structure shown in Figure 7, and has the structure shown in Figure 4A in terms of energy band diagram. In addition, the conductive region 110 corresponding to the third conductive region J is used as a read-only gate as a lower gate. Naturally, the above-mentioned function of the third conductive region J can be similarly expected in the element shown in FIG.

As is clear, the elements according to the embodiments of the present invention shown in FIGS. 9E and F or the first OA are different from the materials, conductivity types, composition ratios, and other parameters at the time of formation of each layer region described above, or the manufacturing procedure, etc. By selecting arbitrarily, 1st to 5th
Although it is possible to realize any of the energy band diagram relationships described with reference to the figures, structurally, as shown in FIGS. 9E and 10A, respectively,
When using the conductive region 12 as a drain, if there is a portion between the drain region 12 and the carrier trapping region 30 that overlap each other in plan projection, the drain region 1
When a bias is applied to 2, it cannot be said that there is a possibility that carriers captured in the carrier trapping region 30 may be unexpectedly pulled out, or that carriers may be erroneously injected from the drain region 12.

If there is such a risk, please refer to Figures 9E and 10A.
As shown by imaginary lines 30E in the figure, the drain regions 12 are arranged so that they do not overlap with each other in plan projection with respect to the carrier capture region 30, or are offset from each other in the in-plane direction as a whole. All you have to do is configure it so that there is a relationship.

FIG. 11 shows still another specific example of manufacturing the semiconductor memory element of the present invention, in which a silicon single crystal is used as the substrate 1.

First, as shown in Figure 11A, the existing LOGO
Partially thick oxide film 3 using the 3 (partial oxidation technology) process
A conductive layer region 110 which will become a region corresponding to the third conductive region J in the future, a region corresponding to the third wide gap region An insulating material such as silicon oxide or silicon nitride [9130] is laminated. The conductive layer region 110 can be made of highly impurity-concentrated silicon or silicide that has rectifying properties with the substrate 1, and when this device is used as a field effect transistor, a layer region corresponding to the third conductive region J. 110 can be used as the bottom gate electrode of the field effect transistor structure in the future.

Further, an opening W without the thick oxidation [3] is provided within a distance range where lateral epitaxial growth is possible from the insulating film 130, and a cleaning process and an in-situ etch back in an amorphous silicon deposition chamber are performed. After that, an amorphous silicon layer is formed, and then a heat treatment is performed at 700°C for two and a half hours in a nitrogen atmosphere to promote lateral solid phase epitaxial growth, and single crystal silicon is formed around the opening W. Thin film 108, 10
Form B. On the other hand, a layer 10c that remains in a polycrystalline state is formed in a region far from the opening W. Note that it is also possible to use lateral vapor phase epitaxial growth instead of lateral solid phase epitaxial growth. However, in this case, since the single crystal silicon film grows while being deposited from the opening W to the left and right, the silicon thin films are not deposited over the entire surface of the substrate.

When the lateral solid phase epitaxial growth in the solid phase or gas phase is completed, a silicon nitride film 15 is deposited, and the previously described LOGOS process is applied using this as an oxidation mask to form a portion 101 corresponding to the first semiconductor region A and a second semiconductor region 101. a first conductive region F;
Second part F-1. The parts 11 and 12 corresponding to F-2 are removed and subjected to oxidation treatment. The first and second conductive portions 11 and 12 employ known ion implantation or selective diffusion techniques, and are filled with phosphorus, arsenic, etc. when forming an n-channel device, and boron, etc. when forming a p-channel device. , each can be formed by implanting into a predetermined region portion of the layer region 10A for forming the first semiconductor region.

After this, as shown in FIG. 11B, the above silicon nitride film 15 is removed, and hydrogen plasma treatment is performed in a deposition chamber for a-5iC:1, and further in the same chamber for SiH4,C. +4, a-5io, 8c0.2: by plasma CVD using a mixed gas of H2:
Grow about 500 tl film 7 208. This film 20A will form a region 20 corresponding to the first wide gap region B in the future.

On this structure, a-
5i: HIIi 308 is deposited to a thickness of about 300 layers, and then a process similar to that shown in Figure 10B is applied to selectively form an organic film mask 31 and perform selective etching to capture carriers. A region 30 corresponding to region C is formed.

Next, the organic film mask 31 is removed, and the surface oxide film that is unintentionally formed during the process on the surface of the a-5io, 6C0,2:H film 2OA is transferred to the a-5t:H film 30. Remove by immersion in dilute HF solution, then a-5
Hydrogen plasma treatment was performed in the deposition chamber for iC:H, followed by 5LH4, CI+4, H2 in the same chamber.
a-5iC by plasma CVD using a mixed gas of
:Grow about 500 H films to 40.

This film 40A will form a region 40 corresponding to the second wide gap region in the future.
During the process, the ratio of the amounts of CH4 and SiH was changed from the start to the end of the deposition, and the deposition temperature, hydrogen amount,
Although the optimum range changes depending on the humidity, for example, the ratio (co4/5i84) is gradually changed from 4 to 0. The result is an energy band as shown in Figure 2A.
You will get a diagram.

If the a-5iC:H film 50A is successively deposited on this film 40A, the structure shown in Figure 11C is obtained. Extraction electrodes 71, 7
2 and 75, the device of this embodiment is completed, as shown in FIG. 11D.

In the device of the eleventh illustrated embodiment, the carrier trapping region 3
The height of the barrier formed between the a-5t:H of 0 and the second wide gap region 40 is approximately 0.2 to 0.3 eV for holes and approximately 0.2 to 0.3 eV for electrons under the above growth conditions. is almost 0.1
eV, and the barrier height for holes is formed higher, so information storage in a mode in which holes are injected into the carrier trapping region 3o allows for longer-term memory retention. . Note that if the carrier trapping region 3o is made of amorphous silicon germanium instead of amorphous silicon, the heights of the above barriers will become higher, and the memory retention time will be significantly improved in both hole and electron injection modes. becomes longer.

Regarding carrier injection, the carrier capture region 3
In order to inject holes into zero, it is sufficient to make the first conductive region 50 p+ type, but in order to efficiently inject electrons into the carrier trapping region 30 for erasing, for example, It is conceivable that the first conductive region 50 has a laminated structure of np"-metal electrodes 70, or alternatively a laminated structure of n-1-p""-metal electrodes 70.

Figure 11E shows this component,
One layer may or may not be provided as described above, and therefore, the reference numeral i is shown in parentheses in the drawings. In addition, n-p
* Junctions, n-1-p" junctions, etc. may be collectively considered pn junctions in a broad sense; conversely, the term pn junctions mentioned regarding the first conductive region E in the embodiments up to FIG. This includes all such rectifying junction relationships.

Furthermore, when the semiconductor memory element shown in Figure 11E is used as an n-channel field effect transistor and the conductive region 12 is used as a drain region, when the drain region 12 is positively biased, the Electron injection occurs from the drain region 12 to the carrier trapping region 30, and information is generated! There is also a risk of being a'MA'd.

Therefore, in order to avoid this, as described above, the drain region 12 should not overlap the carrier trapping region 30 in plan projection, as shown by the virtual line 30E in FIG. 11E. Alternatively, they may be shifted from each other in the in-plane direction to form an offset structure. Further, in order to store electrons for a long period of time, it is also good to use a-5iN:H for both the first and second wide gap regions 20 and 40.

A semiconductor memory element having a memory structure similar to that shown in FIG. 11D can also be constructed when the first semiconductor region 10 is made of amorphous silicon. FIG. 12 shows an embodiment in such a case, where on the substrate 1, first,
A lower electrode or third conductive region 100 is formed embedded in the layer region 130 forming the third wide gap region 1, and a thin film of Or, Ni, Ta, etc. can be used for this.

The first semiconductor region 10 formed on the third wide gap region 130 can be made of amorphous silicon, amorphous silicon germanium, or the like.

In addition, a layer region 10^ constituting the first semiconductor region 10
The layer region lid, 12d formed on n
When creating a channel element, it can be made of amorphous silicon or amorphous silicon germanium doped with an impurity such as phosphorus when creating a p-channel element. Conductive electrode 7
1 and 72 also function as extraction electrodes for the source and drain, respectively, of the field effect transistor structure included in this semiconductor memory element, but in particular, the three layers (10^-1id-71) in a stacked relationship serve as sources. constitutes the second part of the second conductive region, and is separated from the three parts facing in the in-plane direction.
Two layers (IOA-126-72) constitute the second part. Further, the laminated structure thereon is the same as that of the element shown in the eleventh figure described above.

By the way, in any of the embodiments described so far, as one aspect according to the present invention, if the second and second wide gap regions B (20) and D (40) are made of a semiconductor material, it is possible to Compared to memory devices, writing and erasing speeds can be significantly increased, but at the expense of memory retention for several years at room temperature.

Of course, this itself is not a problem from the purpose of the present invention, and considering that the limits of miniaturization of existing DRAM devices are already beginning to be seen, the usefulness of the device of the present invention is of course obvious. As mentioned above, in the device of the present invention in which the first and second wide gap regions B (20) and D (40) are made of a semiconductor material, a so-called memory is installed in the peripheral circuit in order to actually operate the device. It is also true that there is a need to provide content playback functionality (refresh functionality). That is, it is necessary to read out the stored contents one bit at a time or one word at a time at fixed intervals determined by various parameters such as the element material, dimensions, bias, etc., and write the same information again.

Therefore, considering an example of a circuit that easily satisfies this requirement, it would be an array configuration as shown in Figures 13A and 13B, for example.

The semiconductor memory element of the present invention used in FIG.
Although the illustrated embodiment is assumed, the circuit shown in No. 13A is suitable for so-called word-batch erasing, and the circuit shown in No. 13B is suitable for bit erasing. Here, for convenience, the mode in which electrons are injected into the carrier trapping region 30 is set as the erase mode.

The erasing operation in the circuit shown in Figure 13A is performed by setting the word line W connecting the electrodes 76 connected to the potential control area of each element to a high level higher than a predetermined value, and connecting it to the area corresponding to the first conductive area E. By setting the erase line WIE connecting the electrodes 75 to a low level below a predetermined value, the elements connected to the erase lines W and H can be erased all at once.

Hereinafter, high level and low level refer to those exceeding and below the respective predetermined values, and will simply be referred to as high level and low level, but in the above case, word line W1+1 is at low level. If so, the elements connected to this will not be erased.

When writing information to an element at an address where bit line B1 and word line W1 intersect, the bit line BI' corresponding to each bit line B is set to high level, and the word line W is set to low level. and the bit line Bk of the element at another address
'(k≠i) is set to low level, and the word line Wj'(j≠
i) to a high level. Furthermore, since the bit line Bk (k≠i) related to the element at the corresponding address is set to a low level,
No extraction of electrons to region 11 occurs in them.

On the other hand, in the case of the array configuration shown in Figure 13B, erasing can be performed bit by bit even on the same word line. In other words, when the DIE line is at a low level and the word line W is at a high level, erasing occurs only in the element whose address is at the intersection of these lines by injecting electrons into the carrier capture region 30, and the other B , E lines are set at high level and the word line W is set at low level, no erase operation occurs in the elements at these other addresses. Writing is the same as described with reference to FIG. 13A.

Although each embodiment of the present invention has been described in detail above, it should be noted that each layer region, such as the first semiconductor region, first, second, and third wide gap regions, may be actually formed by about 100 people. Therefore, ultra-fine design, which was completely impossible with conventional DRAM element structures, can be made practical with the present invention.

[Effects] According to the present invention, in place of conventional DRAM elements whose miniaturization limits have already been seen, the present invention can better meet the demands for ultra-fine miniaturization and is capable of writing electrical information at high speed. A semiconductor memory element that can be erased, erased, or rewritten can be provided. As a result, it is possible to simplify the configuration of the present device and peripheral circuits including the present device, and to reduce the voltage.

6 In addition, since the semiconductor memory element of the present invention essentially includes structural elements of a non-volatile memory, research on the materials, compositions, and various other parameters used in each layer region may be carried out without departing from the spirit of the present invention. , it can be expected that the storage content retention period will be further extended, and of course it also offers the possibility of being used as an EEPROM. Therefore, the present invention is also useful in providing a basic idea and structure to this type of industry, where it is hoped that in the future there will be no distinction between DRAM and EEPROM, at least in terms of element structure. It is very helpful.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a basic configuration example of a physical or geometric structure in a semiconductor memory device of the present invention. FIG. 2 is an energy band diagram of a main part that can be adopted in a semiconductor memory device of the present invention. Explanatory diagrams of the first and second examples. FIG. 3 is an explanatory diagram of third and fourth examples showing other main part energy band diagrams that can be adopted in the semiconductor memory element of the present invention. FIG. 4 is an explanatory diagram of fifth and sixth examples of still other main part energy band diagrams that can be adopted in the semiconductor memory element of the present invention. FIG. 5 is an explanatory diagram of seventh and eighth examples of other main part energy band diagrams that can be adopted in the semiconductor memory element of the present invention. FIG. 6 is an explanatory diagram of a cross-sectional structure of an embodiment of the present invention which is a modification of the first illustrated embodiment. FIG. 7 is an explanatory diagram of an example of a cross-sectional structure in another embodiment of the semiconductor memory element of the present invention. FIG. 8 is an explanatory diagram of the cross-sectional structure of still another embodiment of the semiconductor memory element of the present invention. FIG. 9 is an explanatory diagram of a specific example of manufacturing the semiconductor memory element of the present invention. FIG. 10 is an explanatory diagram with another example of manufacturing the semiconductor memory satin according to the present invention. FIG. 11 is an explanatory diagram of still another fabrication example of the semiconductor memory element of the present invention. FIG. 12 is a schematic configuration diagram of an example device obtained by modifying the fabrication example of the semiconductor memory device of the present invention shown in FIG. 11. FIG. 13 is an explanatory diagram of an example of a circuit in which semiconductor memory elements of the present invention are assembled in an array. It is. In the figure, 1 is a substrate that serves as a physical support substrate for the entire device, A,
10 is a first semiconductor region, B, 20 is a first wide gap region, C930 is a carrier trapping region, D. 40 is the second wide gap region, E, 50 is the first conductive region, F is the second conductive region, F-1, 11 is the first part of the second conductive region, F-2, 12 is the second conductive region. Second part, G.
52 is a potential control region, I, 130 is a third wide gap region, J, 110 is a third conductive region, K is a variable threshold field effect transistor structure portion, CB is a conduction band edge, V
B is the valence band edge. 9 00 taste method ω seaweed 〉 coc. O〉 Ward 465

Claims (47)

[Claims] (1) The first semiconductor region is sandwiched between the first semiconductor region and the carrier trapping region, and has at least a part of the band gap portion which is equal to or larger than the band gap of the carrier trapping region on the energy band diagram. A wide gap region; sandwiched between the carrier trapping region and the first conductive region, and having at least a part of the band gap portion that is equal to or larger than the band gap of the carrier trapping region on an energy band diagram. a second wide gap region; the conduction band edge of the second wide gap region has a gradient in which the energy level increases as it approaches the carrier trapping region, and the valence band edge approaches the carrier trapping region; A semiconductor memory element having a gradient in which the energy level decreases according to the following. (2) The semiconductor memory element according to claim 1, wherein the first conductive region includes a broadly defined pn junction formed in the thickness direction or in-plane direction. (3) The semiconductor memory element according to claim 1 or 2, further comprising a potential control region that is formed to be electrically isolated from the first conductive region and controls the potential of the carrier trapping region. (4) A claim comprising a second conductive region that is in contact with one or both of the first wide gap region and the first semiconductor region, or is in contact with the first semiconductor region and faces the carrier trapping region. The semiconductor memory element according to item 1, 2 or 3. (5) a third wide gap region in contact with the first semiconductor region on a side opposite to the side where the first semiconductor region and the first wide gap region are in contact; and a third wide gap region in contact with the first semiconductor region; and a third conductive region provided in contact with the third wide gap region on the opposite side.
5. The semiconductor memory element according to 3 or 4. (6) The second conductive region has a first part and a second part separated from each other, one of the first and second parts is used as a source, the other as a drain, and the third conductive region is used as a gate. 6. The semiconductor memory element according to claim 5, comprising a field effect transistor structure. (7) The first semiconductor region is sandwiched between the first semiconductor region and the carrier trapping region, and has at least a part of the band gap portion which is equal to or larger than the band gap of the carrier trapping region on the energy band diagram. A wide gap region; sandwiched between the carrier trapping region and the first conductive region, and having at least a part of the band gap portion that is equal to or larger than the band gap of the carrier trapping region on an energy band diagram. a second wide gap region; a second wide gap region that is in contact with one or both of the first wide gap region and the first semiconductor region, or that is in contact with the first semiconductor region and faces the carrier trapping region; a conduction band edge of the first wide gap region has a gradient in which the energy level increases as it approaches the carrier trapping region, and a valence band edge has an energy level that increases as it approaches the carrier trapping region; 1. A semiconductor memory element characterized by having a decreasing slope. (8) The semiconductor memory element according to claim 7, wherein the first conductive region includes a broadly defined pn junction formed in the thickness direction or in-plane direction. (9) The semiconductor memory element according to claim 7 or 8, further comprising a potential control region that is formed to be electrically isolated from the first conductive region and controls the potential of the carrier trapping region. (10) a third wide gap region in contact with the first semiconductor region on a side opposite to the side where the first semiconductor region and the first wide gap region are in contact; and a third wide gap region in contact with the first semiconductor region; and a third conductive region provided in contact with the third wide gap region on the opposite side.
or 9. The semiconductor memory element according to 9. (11) The second conductive region has a first portion and a second portion separated from each other, one of the first and second portions is used as a source, the other as a drain, and the third conductive region is used as a gate. 11. The semiconductor memory element according to claim 10, comprising a field effect transistor structure. (12) A first semiconductor region which is sandwiched between the first semiconductor region and the carrier trapping region and has at least a part of the band gap portion which is equal to or larger than the band gap of the carrier trapping region on the energy band diagram. A wide gap region; sandwiched between the carrier trapping region and the first conductive region, and having at least a part of the band gap portion that is equal to or larger than the band gap of the carrier trapping region on an energy band diagram. a second wide gap region; the conduction band edge of the first wide gap region has a gradient of increasing energy level as it approaches the carrier trapping region; A semiconductor memory element characterized in that the band edge has a gradient in which the energy level increases as the distance from the carrier trapping region increases. (13) The semiconductor memory element according to claim 12, wherein the first conductive region includes a broadly defined pn junction formed in a thickness direction or an in-plane direction. (14) The semiconductor memory element according to claim 12 or 13, further comprising a potential control region that is formed to be electrically isolated from the first conductive region and controls the potential of the carrier trapping region. (15) A second conductive region that is in contact with one or both of the first wide gap region and the first semiconductor region, or that is in contact with the first semiconductor region and faces the carrier trapping region. 15. The semiconductor memory element according to item 12, 13, or 14. (16) a third wide gap region in contact with the first semiconductor region on a side opposite to the side where the first semiconductor region and the first wide gap region are in contact; and a third wide gap region in contact with the first semiconductor region; and a third conductive region provided in contact with the third wide gap region on an opposite side.
16. The semiconductor memory element according to 13, 14 or 15. (17) The second conductive region has a first part and a second part separated from each other, one of the first and second parts is used as a source, the other as a drain, and the third conductive region is used as a gate. 17. The semiconductor memory element according to claim 16, comprising a field effect transistor structure. (18) The first semiconductor region is sandwiched between the first semiconductor region and the carrier trapping region, and has at least a part of the band gap portion which is equal to or larger than the band gap of the carrier trapping region on the energy band diagram. A wide gap region; sandwiched between the carrier trapping region and the first conductive region, and having at least a part of the band gap portion that is equal to or larger than the band gap of the carrier trapping region on an energy band diagram. a second wide-gap region; the valence band edge of the first wide-gap region has a gradient in which the energy level decreases as it approaches the carrier trapping region; and the second wide-gap region The valence band edge of has a gradient in which the energy level decreases as it moves away from the carrier trapping region. (19) The semiconductor memory element according to claim 18, wherein the first conductive region includes a pn junction in a broad sense formed in a thickness direction or an in-plane direction. (20) The semiconductor memory element according to claim 18 or 19, further comprising a potential control region that is formed to be electrically isolated from the first conductive region and controls the potential of the carrier trapping region. (21) A claim comprising a second conductive region that is in contact with one or both of the first wide gap region and the first semiconductor region, or is in contact with the first semiconductor region and faces the carrier trapping region. 21. The semiconductor memory element according to item 18, 19 or 20. (22) a third wide gap region in contact with the first semiconductor region on a side opposite to the side where the first semiconductor region and the first wide gap region are in contact; and a third wide gap region in contact with the first semiconductor region; and a third conductive region provided in contact with the third wide gap region on an opposite side.
22. The semiconductor memory element according to 19, 20 or 21. (23) The second conductive region has a first part and a second part separated from each other, one of the first and second parts is used as a source, the other as a drain, and the third conductive region is used as a gate. 23. The semiconductor memory element according to claim 22, comprising a field effect transistor structure. (24) The first semiconductor region is sandwiched between the first semiconductor region and the carrier trapping region, and has at least a part of the band gap portion which is equal to or larger than the band gap of the carrier trapping region on the energy band diagram. A wide gap region; sandwiched between the carrier trapping region and the first conductive region, and having at least a part of the band gap portion that is equal to or larger than the band gap of the carrier trapping region on an energy band diagram. a second wide gap region; the conduction band edge of the first wide gap region has a gradient in which the energy level decreases as it approaches the carrier trapping region; A semiconductor memory element characterized in that the conduction band edge has a gradient in which the energy level decreases as the distance from the carrier trapping region increases. (25) The semiconductor memory element according to claim 24, wherein the first conductive region includes a pn junction in a broad sense formed in the thickness direction or in-plane direction. (26) The semiconductor memory element according to claim 24 or 25, further comprising a potential control region that is formed to be electrically isolated from the first conductive region and controls the potential of the carrier trapping region. (27) A claim comprising a second conductive region that is in contact with one or both of the first wide gap region and the first semiconductor region, or is in contact with the first semiconductor region and faces the carrier trapping region. 27. The semiconductor memory element according to item 24, 25 or 26. (28) a third wide gap region that is in contact with the first semiconductor region on a side opposite to the side where the first semiconductor region and the first wide gap region are in contact; and a third wide gap region that is in contact with the first semiconductor region; and a third conductive region provided in contact with the third wide gap region on an opposite side.
28. The semiconductor memory element according to 25, 26 or 27. (29) The second conductive region has a first portion and a second portion separated from each other, one of the first and second portions is used as a source, the other as a drain, and the third conductive region is used as a gate. The semiconductor memory element according to claim 28, comprising a field effect transistor structure. (30) The first semiconductor region is sandwiched between the first semiconductor region and the carrier trapping region and has at least a part of the band gap portion which is equal to or larger than the band gap of the carrier trapping region on the energy band diagram. A wide gap region; sandwiched between the carrier trapping region and the first conductive region, and having at least a part of the band gap portion that is equal to or larger than the band gap of the carrier trapping region on an energy band diagram. a second wide gap region; the valence band edge of the first wide gap region has a gradient of increasing energy level as it approaches the carrier trapping region; A semiconductor memory element characterized in that the valence band edge has a gradient in which the energy level increases as the distance from the carrier trapping region increases. (31) The semiconductor memory element according to claim 30, wherein the first conductive region includes a pn junction in a broad sense formed in a thickness direction or an in-plane direction. (32) The semiconductor memory element according to claim 30 or 31, further comprising a potential control region that is formed to be electrically isolated from the first conductive region and controls the potential of the carrier trapping region. (33) A claim comprising a second conductive region that is in contact with one or both of the first wide gap region and the first semiconductor region, or is in contact with the first semiconductor region and faces the carrier trapping region. The semiconductor memory element according to item 30, 31 or 32. (34) a third wide gap region that is in contact with the first semiconductor region on a side opposite to the side where the first semiconductor region and the first wide gap region are in contact with each other; and a third wide gap region that is in contact with the first semiconductor region; and a third conductive region provided in contact with the third wide gap region on the opposite side.
, 31, 32 or 33. (35) The second conductive region has a first part and a second part separated from each other, one of the first and second parts is used as a source, the other as a drain, and the third conductive region is used as a gate. 35. The semiconductor memory element according to claim 34, comprising a field effect transistor structure. (36) The first semiconductor region is sandwiched between the first semiconductor region and the carrier trapping region, and has at least a part of the band gap portion which is equal to or larger than the band gap of the carrier trapping region on the energy band diagram. A wide gap region; sandwiched between the carrier trapping region and the first conductive region, and having at least a part of the band gap portion that is equal to or larger than the band gap of the carrier trapping region on an energy band diagram. a second wide-gap region; the valence band edge of the first wide-gap region has a gradient in which the energy level decreases as it approaches the carrier trapping region; and the second wide-gap region A conduction band edge of has a gradient in which the energy level decreases as it moves away from the carrier trapping region. (37) The semiconductor memory element according to claim 36, wherein the first conductive region includes a pn junction in a broad sense formed in a thickness direction or an in-plane direction. (38) The semiconductor memory element according to claim 36 or 37, further comprising a potential control region that is formed to be electrically isolated from the first conductive region and controls the potential of the carrier trapping region. (39) A claim comprising a second conductive region that is in contact with one or both of the first wide gap region and the first semiconductor region, or is in contact with the first semiconductor region and faces the carrier trapping region. The semiconductor memory element according to item 36, 37 or 38. (40) a third wide gap region in contact with the first semiconductor region on a side opposite to the side where the first semiconductor region and the first wide gap region are in contact; and a third wide gap region in contact with the first semiconductor region; and a third conductive region provided in contact with the third wide gap region on an opposite side.
39. The semiconductor memory element according to 37, 38 or 39. (41) The second conductive region has a first part and a second part separated from each other, one of the first and second parts is used as a source, the other as a drain, and the third conductive region is used as a gate. 41. The semiconductor memory element according to claim 40, comprising a field effect transistor structure. (42) The first semiconductor region is sandwiched between the first semiconductor region and the carrier trapping region, and has at least a part of the band gap portion which is equal to or larger than the band gap of the carrier trapping region on the energy band diagram. A wide gap region; sandwiched between the carrier trapping region and the first conductive region, and having at least a part of the band gap portion that is equal to or larger than the band gap of the carrier trapping region on an energy band diagram. a second wide gap region; the conduction band edge of the first wide gap region has a gradient in which the energy level increases as it approaches the carrier trapping region; A semiconductor memory element characterized in that the electron band edge has a gradient in which the energy level increases as the distance from the carrier trapping region increases. (43) The semiconductor memory element according to claim 42, wherein the first conductive region includes a pn junction in a broad sense formed in a thickness direction or an in-plane direction. (44) The semiconductor memory element according to claim 42 or 43, further comprising a potential control region that is formed to be electrically isolated from the first conductive region and controls the potential of the carrier trapping region. (45) A claim comprising a second conductive region that is in contact with one or both of the first wide gap region and the first semiconductor region, or is in contact with the first semiconductor region and faces the carrier trapping region. 45. The semiconductor memory element according to item 42, 43, or 44. (46) a third wide gap region in contact with the first semiconductor region on a side opposite to the side where the first semiconductor region and the first wide gap region are in contact; and a third wide gap region in contact with the first semiconductor region; and a third conductive region provided in contact with the third wide gap region on an opposite side.
45. The semiconductor memory element according to 43, 44 or 45. (47) The second conductive region has a first part and a second part separated from each other, one of the first and second parts is used as a source, the other as a drain, and the third conductive region is used as a gate. 47. The semiconductor memory element according to claim 46, comprising a field effect transistor structure.