JPS6235572A - Semiconductor nonvolatile memory element - Google Patents

Abstract

PURPOSE:To reduce an applied voltage for writing and to alleviate the condition of the thickness of an insulating layer by interposing a semiconductor charge storage layer between insulating films which vary an energy gap as thickness. CONSTITUTION:This memory element has a structure that an insulating layer 1 which is varied at X of a-Si1-XHX film in a range of 0<=X<0.7 is grown approx. 100nm by a plasma CVD method or a light CVD method on an n-type Si substrate 6, a Ge film 7, an a-Si1-XHX film 1, and an electrode 2 are sequentially laminated thereon. Since the potential barrier of the film 1 continuously varies as the value of the X, a charge implanting speed can be controlled, and this means that, even if the controllability of the insulating film thickness is deteriorated, if the composition of the film is gradually varied, the charge implantation can be performed by the slight variation of an applied voltage. A writing can be performed at a lower voltage than that of the conventional one.

Description

[Detailed Description of the Invention] Summary of the Invention A potential well is formed by sandwiching a semiconductor charge storage layer between insulating films whose energy gap changes with the thickness, and by injecting or releasing charges into this well portion. Writing information.

A semiconductor nonvolatile memory element that is read.

[Technical field] The present invention relates to semiconductor nonvolatile memory devices.

[Prior art] As a semiconductor non-volatile memory element, PAMO
S memory devices and MNOS memory devices are well known.

FIG. 4 shows an example of a FAXOS memory element. F
The AMOS memory element has a floating gate 32 in an insulating film (SiO2) 31 that is not electrically connected anywhere. The thickness of SiO2 under this gate 32 is approximately 100 r+m. In this figure, 36 is n-type S
i-substrate, 35 is a p-type diffusion region formed under the electrode, 3
3 and 34 are drain and source electrodes, respectively.

Charge injection into floating gate 32 for writing is accomplished by increasing the drain voltage to cause avalanche breakdown. Therefore, a voltage of several tens of volts is required for charge injection.

FIG. 5 shows an example of an MNOS memory device.

This MNOS memory element has approximately 2nm on the semiconductor substrate 46.
A very thin 5iO7 film (insulating layer) 41 and about 5O
It has a structure in which an r+n+ Si3N4 film 47 is laminated, and a gate electrode 42 is laminated thereon. 43.44 is an electrode.

45 is a p-type diffusion region.

Charge injection is performed by applying a large negative voltage pulse to the gate electrode 42, so that holes are injected into SiO241 and 513N4.
This is achieved by tunneling into a trap near the interface of 47. Since the tunneling effect depends on the film thickness of SiO241, control of the film thickness of SiO241 is very important and there is a problem that the yield is poor.

[Object of the Invention] An object of the present invention is to provide a semiconductor nonvolatile memory element in which the applied voltage for writing can be lowered and the conditions regarding the thickness of the insulating layer (film) can be relaxed.

[Structure and effects of the invention] A semiconductor nonvolatile memory device according to the present invention.

A potential well is formed by sandwiching a semiconductor charge storage layer between insulating films whose energy gap changes with thickness, and information is written and read by injecting or releasing charges into this well. shall be.

Since the energy gap between the insulating films sandwiching the charge storage layer changes, the height of the potential barrier changes in 11 directions. Therefore, compared to an insulating film with a constant energy gap, there is no need to strictly control the film thickness, which improves yield and allows writing at low voltage.

[Explanation code for the example] FIG. 1 shows an example of a memory element having three terminals.

This memory element is a-8I on an n-type Si substrate 6.
Ge7. a-3t Hl with the same structure.

-x x It has a structure in which the electrodes 2 are stacked one after another. Electrode 3 is Si
After performing p-type diffusion (region 5) on the substrate 6, it is formed by a vapor deposition method or the like. Electrode 4 is also deposited.

The insulating layer (film) is a-81H1, and the charge is -x x It is Ge7 that accumulates. a-3I H film 1.

-X x As mentioned above, the value of X is changing continuously.

As shown in FIG. 3(a), the height of the potential barrier changes continuously in the middle direction, and is highest on the Ge layer 7 side.

The a-81H layer 1 is a potential barrier to prevent electron-hole pairs generated in the Si substrate 6-X x by thermal excitation from being erroneously injected as write charges into the charge storage layer 7, and further accumulates. It also acts to prevent the carrier from easily flowing out.

Therefore, the information has non-volatility.

In addition, since the height of the potential barrier of a-8it-xHxl changes continuously with the value of The injection rate of carriers can be changed. This is due to the use of tunnel effect.

The transmittance T due to the tunnel effect is when the potential barrier is square as shown in Figure 3(b).

It is expressed by the following equation, where E is the energy of the incident electron, U is the height of the energy barrier, is the wave number of the electron in the energy barrier, and L is the width of the energy barrier. Here, it is assumed that U > E.

In order to increase the transmittance T, the second term on the right side of the above equation should be decreased. If E and L are constant, the smaller U is, the smaller K is, and therefore the transmittance T is larger. Also E, U
If is constant, the smaller L becomes, the faster the transmission rate T becomes. Therefore, the transmittance due to the tunnel effect increases as the energy barrier becomes lower and its width narrower.

As mentioned above, the charge injection speed can be controlled by changing the height of the potential barrier, but this means that even if the controllability of the insulating film thickness is poor, if the composition of the insulating film is gradually changed, the applied voltage can be adjusted more or less. This means that charge injection is possible due to change. In other words, in the potential barrier of the form shown in Fig. 3(a), even if the bottom barrier becomes somewhat thick, carriers can pass through the thin part of the upper barrier 1], so that the potential barrier shown in Fig. 3(b)
) It is no longer necessary to strictly control 11+ as in [1] of the conventional potential barrier shown in FIG.

This improves the yield in manufacturing memory elements.

Further, the potential barrier of a memory element having such a structure is several eV at most, and the height of the barrier gradually changes, so writing can be performed at a lower voltage than in the past. Namely.

[11] of the barrier is thinner at the top, allowing carriers to easily pass through due to the tunnel effect, and low voltage driving is possible. The memory device according to the present invention has these two advantages.

Writing to the memory element shown in FIG. 1 is accomplished by applying a voltage between electrodes 2 and 4. Since the injected electrons are accumulated in the Ge layer 7, the lower a-
The surface of the n-S-x x i substrate 6 in contact with the 3I H layer 1 is inverted to p-type. This is because the conductivity type of this inverted p-type portion and the p-shaded region 5 is the same.

In the write state, one large-area p shadow region is created. This is detected as a change in charge capacity between electrodes 3 and 4. In other words, information can be read by detecting changes in charge capacity.

Although the electrodes 2, 3.4 are all of the Brehner type, the electrode 4 may be placed on the back surface of the n-3i substrate 6.

FIG. 2 shows an example of a four-terminal memory element. 1st
Components that are the same as those shown in the figures are given the same reference numerals.

Writing is performed between the electrode 2 and the electrode 8 on the back surface of the substrate 6, but the method of reading information is different from that in the embodiment shown in FIG. In the embodiment of FIG. 2, in the write state, a-
The surface of the n'--X x St substrate 6 in contact with 81H1 is inverted to the p-type, and the p-shade regions 5 of the electrodes 3 and 4 are connected to form one p-shade region.

This means that it can be detected as a 71i current and voltage change between electrodes 3 and 4. In other words, information can be read by detecting changes in current and voltage.

A simple method such as ultraviolet irradiation is sufficient to erase information.

In the second embodiment, a-8I 1-x was used as the insulating layer.
Of course, other compositions in which H is used may also be used.

As explained in detail above, according to the present invention, the energy gap of the insulating film is gradually changed, so even if the controllability of the insulating film thickness is poor, information can be written easily by making some voltage adjustments. Can be done. Therefore, it is possible to eliminate a decrease in yield due to difficulty in controlling the film thickness. Moreover, since the energy barrier caused by the insulating film is several eV, information can be written at low voltage.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of the invention, FIG. 2 is a sectional view showing another embodiment of the invention, and FIG. 3 is a diagram showing a potential barrier. Figures 4 and 5 show conventional examples, and Figure 4 shows F
FIG. 5 is a cross-sectional view of an MNOS memory device. 1... Insulating film, 2... Gate electrode, 3, 4.8...
- Electrode, 5...p shadow region, 6... substrate, 7... semiconductor charge storage layer. Patent applicant Tateishi Electric Co., Ltd. Agent Patent attorney Kenji Ushiku (and one other person) Figure 2 (a) (b) -L-1 Figure 4

Claims (2)

[Claims] (1) A potential well is formed by sandwiching a semiconductor charge storage layer between insulating films whose energy gap changes with thickness, and information is written and read by injecting or releasing charges into this well. ,
Semiconductor non-volatile memory element. (2) The semiconductor nonvolatile memory element according to claim (1), wherein the thickness of the insulating film is approximately several times the de Broglie wavelength of electrons.