JPS58158973A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To produce a strong capacity coupling between a control gate region and a floating gate electrode with small area by controlling the voltage of the floating gate electrode with the voltage of the control gate region of a single crystal Si through a thin oxidized film. CONSTITUTION:An N<+> type control gate region 15 is diffused in a P type Si substrate 11, a thin SiO2 film 18 is formed on the region, and a floating gate electrode 14 made of polycrystalline Si is formed on the film. A P<-> type polycrystalline Si is formed through a gate oxidized film 16 on the electrode, an N<+> type source region 12 and a drain region 13 are formed in the silicon, and the silicon interposed between the regions 12 and 13 is used as a channel region 20. In this manner, the channel conductance of the region 20 is varied by the voltage of the electrode 14, the electrostatic capacity is increased between the electrodes 14 and 15 while reducing the area, and an inexpensive low program voltage memory IC is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a floating gate nonvolatile semiconductor memory in which a read transistor is provided on a floating gate electrode and a control gate electrode is provided in a semiconductor substrate below the floating gate electrode.

Due to advances in microfabrication technology in the semiconductor field, the degree of integration of semiconductor memory has increased by four times every two years.
It is increasing at twice the speed.

However, nonvolatile semiconductor memories, which currently require a large programming voltage of 20 V, are difficult to miniaturize compared to other memories, and it has been difficult to reduce costs by reducing the area of memory integrated circuits (ICs). Therefore, it is desired to realize a non-volatile semiconductor memory with low programming time and pressure.

FIG. 1 shows an example of a conventional nonvolatile semiconductor memory. A P-type semiconductor base number 1 is provided with an N+ source region 2 and a drain region 6, and a floating gate electrode 4 is provided on the channel region between the source region 2 and the drain region 3 via a gate oxide M6. There is. Further, an electrode 5 for controlling the potential of the floating gate electrode 4 by 1 kili is provided via the oxide film 8t of the floating gate electrode 4. The potentials of the source region 2 and drain region 5 are the same as those of the aluminum wirings 2a and 3.
Determined by a. The floating gate electrode 4 is entirely covered with an oxide film so that the charges therein are not volatilized to the outside.

FIG. 2 is an electrical equivalent circuit diagram of FIG. 1 showing capacitive coupling between the floating gate pole 4 and surrounding electrodes. C, G, D
, S, Sub, F, G pi respectively control gate 'I
I pole 5. Drain region5. This is a symbol indicating the source region 2°, the substrate 11, and the floating gate electrode 4. Also, OOG r O
” + CI, Q Bub Vs respectively floating gate electrode, pole 4 and control gate electrode 5. floating gate electrode 4 and drain region 5. floating gate electrode 4 and source region 2, floating gate electrode 4 and substrate 1. It is the value of appearance.Second
Based on the charge neutralization conditions of the electrical equivalent circuit shown in the figure, the potential v1 of the floating gate electrode is expressed by the following equation.

Here, Vaa is the potential sQ' of the control gate electrode and is the amount of charge in the floating gate electrode 4. Further, the potentials of the source region 2 and the substrate 1 were set to zero.

Furthermore, it is assumed that Ic, Oaa)) Go.

As is clear from equation (1), when a large number of single cells are injected into the floating gate electrode 4 (written state), the potential of the floating gate electrode 4 is low, and therefore the threshold voltage Vte for the control gate electrode 5 is It gets expensive. When there are not many electrons in floating gate type &4 (erased state) KI/'iv! In other words, the storage state of the memory can be known by detecting the channel conductance between the source and drain regions.

Next, a writing method, that is, a method of injecting electrons into the floating gate electrode 4 will be explained. 11J11 When a large positive voltage w is applied to the gate electrode 5, the floating gate electrode 40 potential V'? '4V! W#rcHikishachire(
It becomes like this.

Here, the drain region if:・connected to state 8])・
(Then, a strong electric current W-fiE with a magnitude of V;P/, toxF' i is the film thickness of the oxide film 7. Due to this strong electric field, electrons are injected from the drain region 5 to the floating gate electrode 4, tox = 100A.
In this case, practical electron injection is performed at VF: 10V.

Next, the erasing method, that is, the method of flowing out from the electron tube floating gate electrode 4 will be explained.

When the control gate electrode 5 is grounded, the potential Vv of the floating gate electrode 4 becomes the following equation from equation (1).

-Qν V″”QO6+08. b+ C1+CD ””” ”
``'''') Furthermore, an erase voltage Vlt is applied to the drain region 3.
When the voltage is applied, a strong electric field with a magnitude of (Vm Vy)/lox is applied to the thin oxide film 7 between the floating gate 4 and the drain region 5, and electrons are transferred from the floating gate electrode 4 to the drain region 5.
flows out to. As with writing, zox==100A
Practical erasure occurs when vm=10V.

The operation of the conventional floating gate nonvolatile memory has been described above, and the operating voltage and write voltage yw.

It is desirable that the initial value K for reducing the erase voltage Vm be a memory that satisfies the following relationship.

coa) ath The potential vyFi is sensitively controlled by the potential voatc of the control gate electrode 5.

In a memory with the structure shown in Fig. 1, 7 kt) K is the floating gate 11 poles 4 so as to satisfy equation (4).
The oxide film 81 between the floating gate electrode 4 and the control gate electrode 5 may be thinned.
Furthermore, the conductivity of the polycrystalline silicon oxide film is high, and unless it is at least about 1 oooX, there is a risk that information will evaporate. Therefore, in conventional memories, the GO'
It was increased by 1. Therefore, the area of the memory cell is large, making it difficult to reduce the cost of the memory IC.

The present invention has been made to overcome these conventional drawbacks, and provides an inexpensive memory card with a small cell area.
It provides:

The present invention is a memory cell having a structure in which a control gate region is provided in a semiconductor substrate, thereby achieving a large QOG in a small area. For example, FIG. 5 is a cross-sectional view of a memory cell according to the first embodiment of the present invention. A control gate region 15 made of an N+ type scattered layer is formed in the P type semiconductor fund 11. A thin silicon thermal oxide film 18 is formed on the control gate region 15, and a floating gate electrode 14 made of polycrystalline silicon is formed thereon.
Form a meeting. Further, a polycrystalline layer is provided via a gate oxide film 16, and an N++ diffused source region 12 is provided within the polycrystalline layer.
and a drain region 15. The P- polycrystalline layer between the source region 12 and the drain region 130 is the channel region 2.
0, the channel conductance of the channel region 20 is
It changes depending on the potential of the floating gate electrode 14. When the floating gate electrode 1401 has a positive potential with respect to the source region 12, the channel conductance becomes high. The potential of the floating gate electrode 14 is determined by the potential of the control gate region 15 through the thin gate oxide film 1B1fr. II will be controlled.

Since the oxide film 18Fi is a thermal oxide film of single crystal silicon, the charges accumulated in the floating gate electrode 14 will not volatilize even if it is as thin as 100χ.
A memory cell with the following structure is provided in the semiconductor base 15, and the silence between the control gate region 15 and the floating gate electrode 140 can be made small in area and large in thickness.
It becomes possible to provide an inexpensive low program burden memory IC.

The first embodiment shown in FIG. 5 is a cross-sectional view of a memory cell in which charges are injected and discharged into the floating gate electrode 14 through a thin oxide film 17 between the drain region 15 and the floating gate electrode 14. Reading is carried out by the conductance of the channel 20 being high and low when a heavy pressure is applied to the control gate region 15.

If there are many electrons in the floating gate electrode 14,
It has low conductance. Injection (writing) of electrons into the floating gate electrode 14 is performed by applying a high voltage to the control gate region 15 with respect to the drain region 13 . An electric field due to this high voltage is applied to the oxide film 17, and electrons are injected from the drain region 13 through the floating gate to the pole 14. Next, the outflow (erasing) of electrons from the floating gate W 14 to the drain region 13 is performed by applying a high voltage to the drain region 13 with respect to the control gate region 15 . Similar to writing, a strong electric field in the opposite direction to that during writing is applied to the oxide film 17, and electrons flow from the floating gate rod 14 to the drain region 15.

As shown in FIG. 5VC, in the present invention, the floating gate has a structure in which the potential of the pole 14 is controlled by the potential of the control gate region 15 via the thin oxide film 18 of single crystal silicon, so even a small if3 product can be used. A strong capacitive coupling can be established between the control gate region 15 and the floating gate electrode 14. This is because the oxide film 18 is a thermal oxide film of monocrystalline silicon, which is a thin oxide film with very good insulating properties. This is because a film can be formed.

FIG. 4 is a sectional view of a nonvolatile memory according to a second embodiment of the present invention. The reading method is the same as in the embodiment W41, but the method of injecting electrons into the floating gate electrode 24 is different. When a positive voltage, which is a reverse bias, is applied to the control gate region 25 of the P-type substrate 21, the control gate region 25
The floating gate electrode 24, which is strongly capacitively coupled to
Semiconductor substrate under:! For example, when a thin oxide film has a thickness f100AK- and a voltage of 6cm is applied to the control gate region 25, the surface potential of the semiconductor surface 50 becomes approximately 5V81j lower than the potential inside the substrate. . In this state, when electrons, which are sVC minority carriers in the substrate, are injected, the electrons are accelerated by an electric field on the semiconductor surface 50 and enter the floating IF pole 24.

This injection method is generally called bipolar injection. The minority carriers are as shown in Fig. 4 (, P-type conductor group 1ii
By providing a KN-type injector region 27 on the surface of 21 and applying a forward voltage to the injector region, the C
−] to be. Also, light? Irradiating the semiconductor substrate 21
It can also be obtained by C.

Figure 5 is a third example of implementing the present invention into a channel-injected non-volatile memory. An N+ diffusion layer 37 is provided on the surface of the P-type semiconductor substrate 31, extending from the control gate region 55, and the floating gate electrode 34 is formed by insulating films 41 and 58.
The capacitance per unit area of the insulating film 41, which is formed so as to bridge through the insulating film 38, is smaller than that of the insulating film 38. When a positive pressure is applied to the control gate region 55 against the substrate 51, the insulation 1! [A large surface potential difference occurs on the surface of the semiconductor substrate under the intersection of 41 and 34. Therefore, when the inversion layer charge flows from the IJ+ diffusion layer toward the control gate region 35, electrons are accelerated by the electric field at a portion where a one-potential difference occurs on the surface, and enter the floating gate electrode 34-\as shown by arrow B. This injection is generally called channel injection.

As shown in FIGS. 5, 4, and 5, the present invention can be fully implemented in nonvolatile memories using various implantation methods.

The present invention improves the capacitive coupling between the control gate electrode and the floating gate electrode by making the positional relationship between the control gate electrode and the memory transistor for reading information upside down compared to the conventional structure. enable you to become stronger,
As a result, it has become possible to manufacture an inexpensive nonvolatile memory with a small surface area only by using a low programming voltage.

Although the present invention has been described only in the case where the readout transistor is provided on a P-type substrate and the conductivity type of the readout transistor is N-type, it goes without saying that the present invention is not limited to this.

In addition, No. 1 used to explain the present invention. Second. In the fifth embodiment, the structure is such that electrons or holes injected into the floating gate electrode are supplied from the substrate side. However, it goes without saying that the present invention can also be applied to a structure in which a charge is injected into the floating gate electrode from the readout F transistor above the floating gate electrode.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional floating gate nonvolatile semiconductor memory, and FIG. 2 is an electrical equivalent circuit diagram showing a capacitive coupling state around the floating gate electrode of FIG. FIG. 3 is a cross-sectional view of a tunnel-injected large-sized nonvolatile semiconductor memory according to the first embodiment of the present invention, and FIG. 4 is a cross-sectional view of a bipolar injection-type nonvolatile semiconductor memory according to the second embodiment of the present invention. FIG. 5 is a sectional view of a channel injection type nonvolatile semiconductor memory according to a third embodiment of the present invention. 1.11, 21.31... Semiconductor substrate 2.12
, 22.32... Source region 5.15, 25.
55...Drain region 4.14, 24.34.
...Floating gate electrode 5.15, 25, 35...
・・・Control gate electrode or region 27 ・・・－・・・・・・・・・・・・・・・Injector and above Applicant Daini Seiko Co., Ltd. Figure 1 Figure 2 S 5ub D Figure 3 1 Figure 4 Figure 5

Claims (5)

[Claims] (1) A control gate region of a second conductivity type different from the first conductivity type provided on the surface portion of the semiconductor substrate of the first conductivity type, and a first gate insulation at least on the control gate region! I
It consists of a floating gate electrode provided through A, and a readout transistor provided on the floating gate electrode with a second gate insulating film interposed therebetween, and the readout transistor is connected to the control gate region WJ. A non-volatile semiconductor memory in which the threshold voltage varies by t% depending on the W loading amount in the floating gate electrode. (2) by applying a strong electric field to the second gate insulating film between the drain region or source region of the read transistor and the floating gate II pole;
It is possible to inject or drain charges to the floating gate electrode. Claims w1 include 'fr% ruts'
．． Non-volatile semiconductor memory described in item 1. (3) A @5 gate insulating film is provided on the front semiconductor substrate surface (σ) in contact with the control gate region, the floating gate electrode is provided on the fifth gate insulating film, and the floating gate electrode is provided on the control gate region. A W42 type injector region f is provided on the semiconductor substrate surface apart from the semiconductor substrate, and a first voltage which is a reverse voltage with respect to the semiconductor substrate is applied to the control gate region to insulate the fifth gate By forming a strong electric field on the surface of the semiconductor substrate under the film and injecting minority carriers from the injector into the strong electric field portion, it was possible to inject -g of the minority carriers into the floating gate electrode. thing? A nonvolatile semiconductor memory according to claim 1, characterized in that: (4) providing a fourth gate isolation film on the surface of the semiconductor substrate in contact with the control gate region;
A fifth gate insulating film having a smaller capacity per unit product than the fourth gate insulating film is provided in contact with the gate insulating film,
The floating gate electrode is provided on the fourth and fifth gate insulating films, and a second conductivity type diffusion region is provided on the surface of the semiconductor substrate under the floating gate electrode and the fifth gate insulating film, By fully applying a second voltage having the same polarity as the first voltage to the control gate electrode, a channel current 1i is caused to flow between the diffusion region and the control gate region, and the fourth gate insulating film and the Claim 1 according to claim 1, wherein part of the charge of the channel current can be injected into the floating gate electrode from the surface of the semiconductor substrate in contact with the fifth gate insulating film. Non-volatile semiconductor memory. (5) The first gate insulating film has a thickness of 200! The silicon dioxide film must have the following thickness 1frll! A nonvolatile semiconductor memory according to any one of claims 1 to 4.