JPS58154273A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a non-volatile memory wherein error wiring is not generated, and electrical writing and erasure can be performed, by providing the electrode for erasure on a floating gate via a thin insulation film. CONSTITUTION:The floating gate 14 is superposed on only the thin insulation film and a drain region 13 by eliminating an overlap with a source region. The electrode 17 for erasure is provided on the thin insulation film on the floating gate 14. When the electrode 17 for erasure is put into a high potential to the drain region 13, the potential of the floating gate 14 is attracted, by capacity coupling, to the potential of the drain region 13 wherein the area of superposition part is large. As a result, the electrode 17 for erasure becomes into a high potential to the floating gate 14, then tunnel electrons flow into the electrode 17 for erasure from the floating gate 14 as shown by the arrow D, and accordingly erasure is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention allows writing and erasing to be carried out by mouth, and w4! F
Don't make a fuss! ↑Regarding volatile semiconductor memory.

Sub-9 Electrically writable and erasable channels Even if you set the selection gate that determines whether or not to write to each memory to a buy-accept condition that does not cause writing, data will still be written to the memory. The danger was great. The reason for this can be explained using the cross-sectional view of an example of a conventional non-volatile semi-vacuum memory manufactured by Charle Western Co., Ltd. shown in Figure 1! ! - to do. @1 In the figure, 1 is a P-type semiconductor substrate, and near the surface thereof, a source region 2 and a region 3 are formed.
In the channel between the drain regions, the channel 6 on the source region side and the channel 7 on the drain region side are connected in series.
It is thicker than the gate insulating film 9 shown below. -Thin insulating film 9. is also provided on the source region 2, and a selection gate electrode 5 is provided on the thick insulating film 8. In the conventional non-volatile semiconductor memory shown in FIG. 1, when a constant voltage VD is applied to the drain region 3 as the drain voltage, if no electrons enter the floating gate 4, a channel 7 is formed under the floating gate. be done. At this time, when the read voltage MA wt is applied to the selection gate 5, the channel 6 also has a high conductance KtJI, a channel is formed between the source region 2 and the drain region 30, and the transistor returns to the zero violet state on the 10th day.

However, even if VD is applied to the drain region 3, if the 111m electrons in the floating gate 4 are injected, the channel 7 will not be formed and the Mo1) transition will be in the 011 state.

The above is the conventional reading method for the nonvolatile semiconductor memory 41J. When writing, drain region 3 and selection game)
When 5 is placed at a high potential with respect to the source region 2 and substrate 1, source and drain channels 6.7 are formed. Electrons flow out from the source region 2 along the channel 6. At this time, the floating gate 4 is strongly attracted to the potential of the drain region 3 due to capacitive coupling and is at a high potential, so the channel 7
The surface of the spoon is inverted and its potential is approximately equal to the potential of the drain region 3. Channel 6 is also inverted and its surface potential is approximately equal to the source potential, so that the potential of channels 6 and 7 is approximately equal to the source potential. A strong electric field is generated near the boundary IO.The electrons are strongly accelerated here, and some of them enter the floating gate as shown by the arrow, completing the writing.In addition, when erasing, the source region 2 is connected to the drain region 3. This applies a high electric field to the thin isolation [j19] between the p1 floating gate 4 and the source region 20, and the electrons move as shown by arrow B (
Erasing is performed using tunnel electrons.

However, as explained above, in the memory IJ in which all reading, writing, and erasing operations are performed electrically,
When the potential of the drain region 3 is made higher than that of the source region 2 during writing, at the same time a floating gate, 4. Tooney, region 1, 2, the potential is □, and the electron at arrow 0 is a tunnel current °
Therefore, even if the selection gate 5 is set to the same potential as the source region 2 to prevent writing, writing may occur. Figure 3 shows two thin gate oxide films 88m,
Thick gate oxide l1g1050m, substrate concentration 7*6
These are experimental results for explaining the above phenomenon for a sample of X to"'am". FIG. 3 shows the change in the threshold value of the MoI transistor with respect to the selection gate voltage when a write voltage is applied to the source region 2 and the drain region for av and to seconds. Ideally, when the selection gate threshold is about 2V or less, no programming is performed and there should be no change in the transistor threshold, but the threshold changes by 0.5V for the reason described above. This may cause erroneous writing due to K.

In the present invention, an erasing electrode is provided on the floating gate with a thin insulating film interposed therebetween in order to prevent the above-mentioned writing errors.

FIG. 2 is a cross-sectional view of the nonvolatile semiconductor memory of the present invention having an erasing electrode.
14 differs from the conventional one in that it overlaps with the source region I2 (it overlaps only on the thin insulating film and the drain region 13).
It is provided on the upper thin insulating film. The erasing method is shown below. When the erasing electrode 17 is set at a high potential with respect to the drain region 13, the potential of the floating gate 14 is capacitively coupled to the potential of the drain region 13, which has a large area where the potentials match. p is attracted. As a result, the erasing electrode 17 is at a high potential with respect to the floating gate 14, and tunnel electrons flow from the floating gate 14 to the erasing electrode 17 as shown by the arrow, completing erasing. No. st! i1, thin gate ant film 8
8μm, thick gate oxide film 1050μm, substrate concentration 6°7X
67% l according to the invention for a sample of 10"51-"
10 for select gate bias after writing for O seconds
The figure shows the change in the threshold value of the transistor.

Thus, according to the present invention, the erroneous I! A nonvolatile memory that can be electrically written to and erased without causing any data is realized.

Description of the Invention Although a KP type semiconductor substrate is used, it goes without saying that the present invention is not limited to this.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an embodiment of a conventional non-volatile semiconductor memory, FIG. 2 is a sectional view of an embodiment of a non-volatile semiconductor memory according to the present invention, and FIG. 3 is a thin gauge oxide I [88 mm, thick Gate acid (1
1, al1050A, In concentration 6 * 7 x 10”
1, 11, , semiconductor substrate 2. cps-” sample, the threshold 1i [changes] after writing for 6 mm and 10 seconds for the conventional one and the M08) plunger according to the present invention. 12., Source region 3.13., Drain region 4, 14, , Floating gate electrode 5.15., Selection gate electrode 6.7., Channel region 8.9., Gate insulator, 1°10,... , electron injection region 16 @II @II erasing electrode
Applicant: Koji Seikosha Co., Ltd. Agent, Patent Attorney Mogami, etc.

Claims (1)

[Claims] There is a distance t near the surface of the #Il conductivity type semiconductor substrate.
- source and drain regions of a second conductivity type different from the first conductivity type provided separately; a gate isolation*a provided on the drain region; and a semiconductor substrate surface between the source and drain regions. a first channel region; and the II
a second gate insulator provided on the I channel region; a second channel region other than the first channel region between the source and drain regions; and a third gate insulator provided on the second channel region. a selection gate electrode provided on the third gate insulating film, a floating gate electrode provided on the first gate insulating film and the second gate insulating film, and a selection gate electrode provided on the floating gate electrode. a nonvolatile semiconductor memory comprising a fourth gate insulating film and an erasing electrode provided on the fourth gate insulating film;