JPS63306598A - Erasing system for non-volatile memory cell - Google Patents

Abstract

PURPOSE:To reduce characteristic deterioration by electrically making a drain area to a floating state when erasing operation is executed with the aid of impressing positive high voltage on a source area. CONSTITUTION:When the erasing operation is executed, erasing potential VPE is impressed to a grounding line GL by making a QS1 to be in a conductive state and a QS2 to be a non-conductive state. Then earth potential VSS, for example OV is impressed to a word line WL. At this time, by electrically cutting off a data line DL which is dropped to the earth potential VSS from a Y decoder 14 with the aid of making a QD in a non-conductive state, the erasing operation is executed in the floating state of the drain area of a memory cell. When the data line DL is electrically cut off from the Y decoder 14 and in the floating state including the drain area connected with it, as the potential of the drain area rises by channel current and that works in the direction of reducing the channel current, the occurrence and the injection of hot hole can be controlled at a sufficient low level when the erasing operation proceeds.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an erasing method for nonvolatile memory cells, and particularly to a voltage application method suitable for improving the controllability and reliability of erasing operations.

[Conventional technology]

Conventionally, regarding nonvolatile memory cells that can be electrically erased, for example, IE, Journal of Solid State Circuits, Nisshi 18 (1983), pp. 532 to 538 (IE
EE, Journal of Solid-5t
ate C1rcuits, SC-15 (1983)
pp 532-538).

The memory cell is composed of a MISFIET having a floating gate electrode and a control electrode.

A write/erase operation is performed by tunneling electrons from the substrate into the floating gate through the thin oxide film under the floating gate or tunneling electrons from the floating gate to the substrate. At this time, the thin oxide film has an IOMV/c! It is necessary to apply a high electric field of m or more, but in order to realize this situation with an externally applied voltage as low as possible, it is necessary to increase the overlapping area of the floating gate electrode and the control gate electrode.

As described above, the cell area of the memory cell is approximately five times larger than that of an ultraviolet erase type EPROM cell having the same floating gate electrode and control gate electrode, which is disadvantageous in promoting high integration and large capacity.

On the other hand, memory cells that can maintain the electrical erase function and have a cell area as small as an EFROM cell,
1985 International Electronic Devices Association Technical Digest, pages 616 to 619 (Technical Dig
est of International Elec
tronDevice Nesting (1985
), pp616-619).

This cell has basically the same structure as a conventional EPROM cell. It is characterized in that the gate oxide film under the floating gate electrode is a thin tunnel oxide film covering the entire channel surface. In conventional EPROM cells, erasing is performed by ultraviolet irradiation, but in this cell, a tunnel oxide film of 10 MV/cm between the floating gate electrode and the source region is used.
Electrical erasure is performed by applying a high electric field of
Specifically, a high positive voltage is applied only to the source region while the control gate electrode, drain region, and semiconductor substrate are grounded. At this time, since the coupling capacitance between the source region and the blowing gate electrode is small, a high electric field can be efficiently applied to the tunnel oxide film without intentionally increasing the overlapping area between the floating gate electrode and the control gate electrode. can do. That is,
Electrical erasing is possible with a cell area comparable to that of conventional EPROM cells. On the other hand, regarding writing, a high electric field is generated within the semiconductor substrate at the end of the drain region to perform hot carrier writing, which is exactly the same as in the case of conventional EPROM cells.

[Problem that the invention seeks to solve]

In the above conventional erasing method, as the erasing operation progresses, when the threshold voltage v0 of the memory cell decreases to around Vtb in a thermal equilibrium state (the bloating gate electrode is electrically neutral), the floating gate electrode Fowlar Nordheim (Fowlar) of electrons from to the source region
-Nordheim) In addition to tunnel emission, hot hole injection from the semiconductor substrate to the floating gate electrode becomes significant, resulting in a problem that the controllability and reliability of the erase operation are impaired.

This situation will be briefly explained below using FIGS. 5 to 7.

5 and 6 are cross-sectional views of the above memory cell, in which the p-type semiconductor substrate 1. Tunnel oxidation II2. Floating gate electrode 39 interlayer insulation llI4. Control gate electrode5. n◆ type semiconductor region (part of source region)6. n◆
type semiconductor region (drain region)7. n-type semiconductor region (
Part of the source area) MISF[! It is composed of T. Control gate electrode5. Drain region7. By applying a positive high voltage Vs to the source region 6 with the p-type semiconductor substrate 1 grounded, electron tunneling 9 is performed from the floating gate electrode 3 to the source region 6.
occurs, and an erase operation is performed.

At the initial stage of erasing, a large amount of electrons are retained in the floating gate electrode 3 as shown in FIG.
Even if a high voltage is applied to the source region 6, no channel current flows.

As shown in FIG. 7, when the erasing progresses and the floating gate electrode 3 approaches an electrically neutral state, a channel current 10 flows due to the capacitive coupling between the source region 6 and the floating gate electrode 3. start. This channel current becomes a 10 ffi species, causing an avalanche in the high electric field region at the end of the source region, and some of the hot holes generated as shown by reference numeral 11 become tunnel oxidized IP! Injected into I2.

Injection of hot holes significantly deteriorates the g quality of the tunnel oxide film by accelerating the generation of interface states, which poses a major problem in terms of the reliability of erasing operations, including the number of rewrites possible.

In addition, the injected hot holes are retained in the floating gate electrode and increase its potential.
The erase operation will proceed with the ler-Nordheim tunnel emission. At this time, as shown in FIG. 7, the erasing speed is rapidly accelerated (section 12), making it extremely difficult to maintain controllability of Vth.

An object of the present invention is to provide a memory cell comprising a MISFET having a floating gate electrode and a control gate electrode, and using a thin tunnel oxide film as the gate oxide film.
An object of the present invention is to provide an electrical erasing method with excellent controllability of threshold voltage.

Another object of the present invention is the above memory cell.

The object of the present invention is to provide a highly reliable electrical erasing method with little characteristic deterioration.

[Means for solving problems]

The above purpose is to perform an erase operation by applying a positive high voltage Vs to the source region in a memory cell made of 15FEτ having a floating gate electrode and a control gate electrode and using a thin tunnel oxide film as the gate oxide film. ,
This is achieved by leaving the drain region electrically floating.

The above object can also be achieved by making the potential of the drain region substantially the same as the Vs during the erasing operation.

[Effect]

According to the above means, even if the potential of the floating gate electrode increases with the erase operation and the erase progresses to a state where an inversion channel begins to be formed under the floating gate electrode, a steady channel current does not flow. Generation and injection of hot holes caused by current can be suppressed.

This prevents a sudden increase in erasing speed, making it possible to realize an erasing operation with high controllability. Furthermore, since deterioration of the quality of the tunnel oxide film due to hot hole injection is suppressed, it is possible to realize an erase operation with excellent reliability such as the number of rewrites possible.

〔Example〕

(Example 1) Hereinafter, a first example of the present invention will be described using FIGS. 1 to 3.

Fig. 1 is an equivalent circuit diagram realizing the erasing method of this embodiment, Figs. 2 and 3 show the erasing characteristics by the above erasing method, Fig. 2 shows the erasing time dependence of the threshold voltage Vtb, and Fig. 3 shows the dependence of the write/erase level on the number of rewrites.

First, the operation of the erasing method in this embodiment will be explained using FIG.

FIG. 1 mainly consists of a memory cell array circuit and peripheral circuits that drive it. 13 and 14 are an X medecoder and a Y decoder, and 15 is a sense amplifier.

Ql is a nonvolatile memory cell capable of electrical writing and erasing operations, and is composed of a MISFET having a floating gate electrode and a control gate electrode, and a thin tunnel oxide film as the gate oxide film. The control gate electrode is connected across the word line WL. In addition, the drain region is connected to the data line DL, and the source region is connected to the ground line OL.
A, Q, and Qmt connected to the respective terminals are switch elements for switching the potential of the ground line OL when writing/reading information and when erasing information. Also.

Similarly, Qo is a switch element for switching the potential (or state) of the data line DL when writing/reading information and when erasing information.

During the erase operation, the erase potential 72 is applied to the ground line GL by making Qsx conductive and Qsx non-conductive. Further, a ground potential V, . . ., Ov, for example, is applied to the word line WL. At this □ time, the data line DL, which has been lowered to the ground potential Vsa in advance.

By making Qo non-conductive and electrically disconnecting it from the Y decoder, an erase operation is performed with the drain region of the memory cell floating.

Now, the total capacitance CT seen from the floating gate electrode
The ratio of the capacitance Cra between the floating gate electrode and the control gate electrode (coupling ratio) to
is about 0.6, the increase in threshold voltage due to write operation ΔV
Assuming t- is about 4v.

The floating gate electrode potential Vr at the initial stage of the erase operation is about -2V. When the thickness of the tunnel oxide film is 10 nm, the erase potential VpI! When 11v is applied to the ground line GL (ie, the source region).

An electric field of about 13 MV101 is applied to the tunnel oxide film at the beginning of the erase operation. At this time, the erase operation is 1 mg to 10
It will be completed in about 5 m5.

At the beginning of the erase operation, the potential VF of the floating gate electrode is about 12V, while the potential of the drain region is Ov, so the surface of the channel region is in an accumulation state and no channel current flows. As VF increases as erasing progresses, the state of the channel surface changes from a depletion state to a weakly inverted layer, and eventually a channel current begins to flow. Here, if the drain region is grounded and its potential is fixed as described in the prior art, the channel current increases rapidly as erasing progresses, and this channel current causes hot holes to be generated. The occurrence and injection of the data have a non-negligible adverse effect on the controllability and reliability of the erase operation.In order to solve this problem, as in this embodiment, the data line DL is electrically disconnected from the Y recorder 14,
If the drain region, including the drain region connected to it, is in a floating state, the potential of the drain region increases due to the channel current, and this works in the direction of decreasing the channel current, so even if erasing progresses, the hot hole generation and injection can be suppressed to sufficiently low levels.

FIG. 2 shows the dependence of Vth on erasing time in the erasing method of this embodiment. The tunnel oxide film thickness of the MISFET constituting the memory cell is 1 nm, the coupling ratio is o, 6. At thermal equilibrium, vt- is 1. O.V.
, the erase potential VpH is 11. It is OV. Conventional elimination method 1
7 (a method in which erasing is performed with the data line DL grounded), the erase characteristic 16 of the one-line method has no sudden drop in Vt- and has excellent controllability.

FIG. 3 shows the erasing method of this embodiment. In the 0-line erase method, which shows the dependence of write/erase characteristics on the number of rewrites, the erase level hardly changes even after several hundred rewrites (erase level 18), and compared to the conventional method (erase level 19). ) As explained above, according to the erasure method of this embodiment,
It has excellent controllability of the erase level, and can realize a highly reliable erase operation in terms of the number of times it can be rewritten.

Finally, regarding the memory cell array circuit and peripheral circuit shown in FIG. Let us explain the operation when writing information and when continuing to write information.

By making the Qo conductive state, the data line DL is electrically connected to the Y decoder 14, and is set to a write potential Vpwz, for example, 6V during a write operation, and a continuous potential, for example, 6V during a read operation.
For example 1. Ov is applied.

Driven by word line WLLtX decoder 13.

During a write operation, the write potential Vpwx is, for example, 11v.

During a read operation, power supply potential VOO1, for example 5V, is applied. Regarding the grounding line GL, Qgx is set to non-conducting state I11.
．． By making Qss conductive, during write operation,
In any case during the read operation, the ground potential Vss, for example, Ov, is applied, and a voltage of 0 or more is applied to perform the read operation, with the determination condition being the presence or absence (or magnitude) of the write operation channel current due to hot carrier injection. .

(Example 2) A second example of the present invention will be described below with reference to FIG.

FIG. 4 is an equivalent circuit diagram realizing the erasing method of the first embodiment. Like FIG. 1 of the first embodiment, the circuit is roughly divided into a memory cell array circuit and peripheral circuits that drive it. What is different from the equivalent circuit diagram in FIG. 1 is that the switch element for switching the potential of the data line DL is Qozt
It consists of two Qot transistors.

A feature of the erasing method shown in this embodiment is that both the source region and drain region of memory cell Q are supplied with the same erase potential VpI.
! is applied. As a result, even if the erase operation progresses, no channel current flows.

Undesirable hot hole generation and injection phenomena can be avoided.

The circuit operation for realizing the erase method of this embodiment is as follows. That is, the switch element Qsx*Qot
The same erase potential VPE is applied to both ground line OL and data line DL by making Q sx p Q ox conductive and non-conducting. A ground potential Vss, for example Ov, is applied to the word line WL.

The ground line GL has the source region of the memory cell and the data line DL.
Since the same drain regions are respectively connected to the same drain regions, erasing operation can be realized with the source and drain regions at the same potential.

As explained above, according to the erasing method of this embodiment,
Since the generation of undesirable hot holes and the injection phenomenon can be avoided, it is possible to realize an erase operation with excellent controllability of the erase level and high reliability for rewriting.

Finally, we will explain the circuit operation when writing and reading information - By setting QDs to a non-conducting state and Qoz to a conducting state, the data line DL is electrically connected to the Y decoder 14, and the data line DL is electrically connected to the Y decoder 14, During operation, the write potential Vpwt is set to, for example, 6V, and during read operation, the read potential is set to, for example, 1. O
V is applied. '7-D WL is driven by the X decoder 13, and a write potential Vpwx, for example 11V, is applied during a write operation, and a power supply potential Vcc, for example 5V, is applied during a read operation. Regarding the ground line GL, by making Qsz non-conductive and Qsz conductive, the ground potential Vss is maintained in both the i-in operation and the read operation.

For example, by applying a voltage of 0 or more such as Ov, a write operation by hot carrier injection and a read operation using the presence or absence (or magnitude) of a channel current as a determination condition are performed.

〔Effect of the invention〕

According to the present invention, in a nonvolatile memory cell composed of a MISFET having a floating gate st@ and a control gate electrode and using a thin tunnel oxide film as the gate oxide film, an electrical erase operation by Fouler-Nordheim tunnel emission of electrons is performed. During the erase operation, the generation of undesirable hot holes and the injection phenomenon can be suppressed, so that it is possible to realize an erase operation with high controllability and reliability.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram realizing the erasing method of the first embodiment, FIGS. 2 and 3 are erasing characteristic diagrams using the erasing method of the first embodiment,
FIG. 4 is an equivalent circuit diagram realizing the erasing method of Example 2, FIGS. 5 and 6 are cross-sectional views of memory cells explaining the problems of the conventional erasing method, and FIG. 7 is a diagram of erasing characteristics using the conventional erasing method. It is. 1...p-type semiconductor substrate, 2...tunnel oxide film, 3
...Floating gate electrode, 4...Interlayer insulating film, 5...Control gate electrode, 6...n◆ type impurity region (constituting part of the source region), 7...n
10-type impurity region (constituting the drain region), 8...
n-type impurity region (constituting part of the source region), 9
... F-N tunnel emission of electrons, 10... Channel current of electrons, 11... Hot hole injection, 12...
Rapid decrease in Vth due to hot hole injection, ], 3.
...X decoder, 14...Y decoder, 15... sense amplifier, Q, ... memory cell, DL... data line, WL... word line, OL... ground line, Qas,
Qsx... Ground line potential switching element, 0
Opening: Data line grounded state changeover switch element, Q
ohQos... Data line potential switching element, 16... Erasing characteristics when the drain region is in the bloating state, 17... Grounding characteristics when the drain region is grounded. 18... Erasing level when the drain region is in a floating state, 19... Erasing level when the drain region is grounded
I21 * +, 'Machi=de? (#) 1!3 figure/to 1oo
1ao. Number of times of testing, (times) 5121 0v % & figure v Answer figure AhyJr (Ninza Junru) /2 :r-=zLi)-+ua"J 6-qtII
Turtle, good body T

Claims (1)

[Claims] 1. Consisting of an insulated gate field effect transistor (MISFET) having a floating gate electrode on a gate insulating film and a control gate electrode stacked thereon via an interlayer insulating film. In a nonvolatile memory cell, when a predetermined voltage is applied to either the drain region or the source region of the MISFET and the information charge stored in the floating gate electrode is extracted to the voltage application region, the other region is electrically An erasing method for nonvolatile memory cells characterized by leaving them in a floating state. 2. In a nonvolatile memory cell consisting of a MISFET, substantially the same predetermined voltage is applied to both the drain region and the source region of the MISFET to transfer information charges stored in the floating gate electrode to both regions. A method for erasing nonvolatile memory cells characterized by extraction.