JPH0434967A - Mos integrated circuit device - Google Patents

Abstract

PURPOSE:To avoid the breakdown of the junction of a substrate with a diffused layer when a protective resistor circuit is impressed with an overvoltage such as static electricity etc. by a method wherein a well region in the same conductivity type as that of the diffused layer is provided in the bent parts of the protective resistor formed of the diffused layer. CONSTITUTION:The pad 1 of a terminal and the leading-out aluminum 7 from the pad 1 is connected to the protective resistor 3 formed of an N type diffused layer by a contact 2 on a P type substrate 6. The first and second N type well regions 5a, 5b in the same conductivity type as that of the N type diffused layer are formed in the first and second bent parts 4 of the protective resistor 3. Resultantly, the protective resistor 3 formed of the N type diffused layer is composed of a resistor R1 between an input terminal and the first well region, another resistor R2 between the first and second cell regions and the other resistor R3 between the second well and an inner circuit 10. In such a constitution, since the well regions 5a, 5b are provided in the bent parts 4 of the protective resistor 3, when the protective resistor circuit is impressed with any overvoltage such as static electricity etc., the current concentration can be relieved in the deep well region 5 situated in the bent parts 4 of the shallow diffused layer.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a MOS integrated circuit device, and in particular to a protective resistor formed of a substrate to which an excessive voltage such as static electricity is applied from the outside and a diffusion layer of opposite conductivity type. The present invention relates to a MOS integrated circuit device comprising:

[Conventional technology]

Conventionally, protective resistor circuits installed in MOS integrated circuit devices to which excessive voltages such as static electricity are applied are generally long and thin in order to obtain a resistance value of 1 to 2 Ω, and the shape is limited by the area on the chip. It had a bent shape in order to make effective use of it. And the circuit scale of MO3 integrated circuits is expanding year by year.
The chip area is increasing as tens of blades to millions of elements are incorporated. For example, the capacity of semiconductor memory has expanded to 256K, IM, and 4Mbit over the past few years, and the chip area has also increased by about 1.5 times, reaching 60 to 70mm2 in the case of functional memory (ASIC'). ing. In order to suppress such an increase in the size of the chip, the protective resistor circuit formed of the diffusion layer has a shape in which the diffusion layer portion is bent at 90 degrees or 45 degrees so as not to affect the chip area.

Figure 3 is a plan view of a conventional example, where 1 is a pad (aluminum), 2 is a contact, and 3 is an N-type diffusion layer (protective resistor).
and 7 is the drawn aluminum of the pad. 4a
is bent at 45 degrees at the bend of the N-type diffusion layer, and the bend at 4b is bent at 90 degrees. Mana 10 is an internal circuit.

[Problem to be solved by the invention]

As mentioned above, the protection resistor circuit of the conventional MOS type integrated circuit device has its diffusion layer bent at 90 degrees or 45 degrees, so when an excessive voltage due to static electricity is applied from the outside, the diffusion layer is bent. There is a disadvantage that current concentration occurs in the part, causing destruction at the junction between the substrate and the diffusion layer.
Approximately 800 when applied according to IL standards (electrostatic breakdown test)
It was destroyed at ~1500V.

An object of the present invention is to provide a MOS device that can prevent destruction of the junction between a substrate and a diffusion layer due to current concentration flowing through the curved portion of a protective resistance circuit formed of a diffusion layer by applying a high voltage due to static electricity from the outside. An object of the present invention is to provide a type integrated circuit device.

[Means to solve the problem]

The MOS type integrated circuit device of the present invention is a MOS type integrated circuit device having a band-shaped high concentration region of opposite conductivity type formed on a semiconductor substrate of negative conductivity type for connecting an input terminal and an internal circuit. The high concentration region has first and second bent portions, the first and second bent portions each have first and second well regions of the same conductivity type as the high concentration region, and A high concentration region is arranged between the input terminal and the first well region R1, and between the first and second well region R2.
, the structure is characterized in that the second well region and the internal circuit have a resistance value of R9.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a plan view of one embodiment of the present invention, and FIG. 2 is a sectional view thereof.

As shown in FIGS. 1 and 2, a terminal pad 1 on a P-type substrate 6 and its drawn-out aluminum 7 are connected by a contact 2 to a protective resistor 3 formed of an N-type diffusion layer. The first diffusion layer of the protective resistor 3. The second bent portion 4 includes first and second N-type well regions 5a having the same conductivity type as the N-type diffusion layer.

5b is formed. As a result, the protective resistor 3 formed by the N-type diffusion layer has a resistance R1 between the input terminal and the first well region, a resistance R2 between the first and second well regions, and a resistance R2 between the first and second well regions.
It is constituted by a resistor R9 between the well and the internal circuit. According to this embodiment, since the well region is provided at the bending part of the protective resistor 3, when an excessive voltage such as static electricity is applied to the protective resistor circuit, the current concentration is caused by the shallow diffusion layer into the substrate. It is relaxed in the deep well region in the bent portion, and can prevent the bond between the substrate and the diffusion layer from breaking.

Note that, according to the present invention, when the resistance value is 1Ω, it can sufficiently withstand an application of about 2500V to 3000V according to the MIL standard.

〔Effect of the invention〕

As explained above, the present invention provides a protective resistor formed of a substrate to which an external supply voltage is input and a diffusion layer of a conductivity type opposite to that diffusion layer and a protective resistor that is bent at an angle of 90 degrees or 45 degrees. By providing well regions of the same conductivity type, when an excessive voltage such as static electricity is applied to the protective resistor circuit, current concentration will occur in the deep well region located at the bent part of the shallow diffusion layer into the substrate. This has the effect of preventing bond breakdown between the substrate and the diffusion layer.

[Brief explanation of drawings]

FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2 is a sectional view taken along the line AA' in FIG. 1, and FIG. 3 is a plan view of an example of a conventional MOS integrated circuit device. DESCRIPTION OF SYMBOLS 1... Pad (aluminum) 2... Contact, 3... N type diffusion layer (protective resistor), 4... Bent part of N type diffusion layer, 5... N type well region, 6... ...P-type board, 7... Pad drawer aluminum, 8...
Insulating film, 9...Field oxide film, 1o...Internal circuit.

Claims (1)

[Claims] In a MOS integrated circuit device having a strip-shaped high concentration region of an opposite conductivity type formed on a semiconductor substrate of one conductivity type to connect an input terminal and an internal circuit, the high concentration region is connected to a first and a second conductivity type. The first and second bent portions each have a first conductivity type of the same conductivity type as the high concentration region.
and a second well region, the high concentration region is R_1 between the input terminal and the first well region, and the first and second well regions are connected to each other.
A MOS type integrated circuit device characterized in that the resistance value is R_2 between the second well region and R_3 between the second well region and the internal circuit.