JPH04349656A - Semiconductor device - Google Patents

Abstract

PURPOSE:To implement a miniaturization and a weight reduction. CONSTITUTION:A given circuit is structured by providing GaAs FETs 14a and 14b for a semiconductor element, capacitors 16c and 22, and others for a circuit element. The capacitor 22 in the power terminal part 20 inserted in parallel to the power source wires of the circuit is arranged to pinch a dielectric layer 24 with a lower electrode board 25 and an upper electrode board 25 in the thickness direction of an insulating substrate 12 on a part where the insulting substrate 12 and a power source terminal 21 are formed. Also, the power source terminal 21 is fixed to the upper electrode board 25 of the capacitor 22. A space on the insulating substrate 12 can be shared by the capacitor 22 and power terminal 21 for installation thereby to reduce the mounting area for the power terminal part 20. Thus, the miniaturization and weight reduction of an apparatus can be easily implemented.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device formed, for example, as a high frequency module or a hybrid integrated circuit.

0003

2. Description of the Related Art As is well known, semiconductor devices have become increasingly compact and highly integrated, and as a result, various devices are becoming smaller and more multifunctional than ever before. Under these circumstances, for example, in mobile phones, circuit elements and semiconductor elements such as chip resistors and chip capacitors are brazed onto a single ceramic substrate on which a wiring pattern is formed, and transmitting power modules and the like are manufactured. Semiconductor devices are configured to support miniaturization and multifunctionality. On the other hand, this power module is provided with a chip capacitor between the power line and ground in order to prevent noise from the power line and as a countermeasure against oscillation.

[0004] The prior art will be explained below with reference to FIG. The drawings illustrate a transmitting power module for a mobile phone, and FIG. 5 is a plan view of the main parts. In the figure, 1 is a GaAsFET which is a semiconductor element, and 2 is a horizontal chip capacitor which is a circuit element. It is brazed to a copper foil wiring pattern 4 formed above. Further, 5 is an input terminal, 6 is an output terminal, and 7 is a power terminal section including a power terminal 8 and a chip capacitor 2. The power terminals 8 are brazed to the upper surface of a power terminal bed 8a arranged by patterning copper foil on one side of the ceramic substrate 3.
A mounting flange 9 made of, for example, copper (Cu) or aluminum (Al) is brazed to the lower surface of the ceramic substrate 3.

[0005] And the chip capacitor 2 of the power terminal section 7
are brazed at both ends to capacitor terminal beds 2a and 2b formed by patterning copper foil,
One capacitor terminal bed 2a and power terminal bed 8
It is connected to a by a lead wire 10. A through hole 11 whose inner surface is metallized is formed in the other capacitor terminal bed 2b, and the through hole 11 connects the capacitor terminal bed 2b to a ground portion on the back surface of the ceramic substrate 3.

However, in the above conventional technology,
In order to provide a capacitor for noise suppression and oscillation prevention between the power supply line and ground, a chip capacitor 2 and a capacitor terminal bed 2a, 2 are mounted on a ceramic substrate 3.
b has to be provided, making it difficult to miniaturize the power supply terminal section 7. In addition, when a more integrated and complex circuit configuration is required due to the demand for multi-functionality, the number of elements 1, 2, etc. to be mounted on the ceramic substrate 3 will increase, and the number of power supply terminals 8 will increase. At the same time, the chip capacitor 2 and capacitor terminal beds 2a and 2b
As the number of terminals increases, the mounting area occupied by the power supply terminal section 7 also increases, which naturally limits the ability to achieve multi-functional miniaturization and weight reduction.

[0007]

[Problems to be Solved by the Invention] The present invention has been made in view of the above-mentioned situation where it is difficult to realize miniaturization and weight reduction, and its purpose is to improve the configuration of each element of the power terminal section. Another object of the present invention is to provide a semiconductor device that is smaller and lighter by reducing the mounting area of the power supply terminal portion.

[Configuration of the invention]

[0009]

[Means for Solving the Problems] A semiconductor device of the present invention includes:
In a device in which a semiconductor element and a circuit element are provided on a substrate to form a predetermined circuit, at least one power terminal portion of the circuit has a bipolar plate in the thickness direction of the substrate in the portion where the power terminal is formed. The device is characterized in that a capacitor is provided with a dielectric layer sandwiched therebetween, and a power supply terminal is formed integrally with one of the plates of the capacitor.

0010

[Operation] In the semiconductor device configured as described above, the capacitor of the power terminal section is inserted in parallel with the power line, and the bipolar plates sandwich the dielectric layer in the thickness direction of the substrate in the power terminal formation section of the substrate. In addition, the power supply terminal is fixed to the capacitor's plate, so that the space for the capacitor and the space for the power supply terminal can be shared on the board.
As a result, the mounting area of the power supply terminal portion can be reduced, and the device can be easily made smaller and lighter.

[0011]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First, a first embodiment will be explained with reference to FIGS. 1 to 3. This embodiment is made for a transmitting power module for a mobile phone like the above-mentioned conventional example, and FIG. 1 is a plan view of the main part, and FIG. 2 is a view taken in the direction of arrow A-A in FIG. FIG. 3 is a partial cross-sectional view, and FIG. 3 is a circuit diagram. In the figure, reference numeral 12 denotes an insulating substrate formed of a ceramic material or the like with a thickness of 0.635 mm, and a predetermined wiring pattern 1 is formed on the upper surface of the insulating substrate 12 to form the circuit shown in FIG.
3 is formed. 14a, 14b are GaAsFETs of semiconductor elements, and GaAsFETs 14a, 14
15d and chip capacitors 16a, . . . , 16d, which are circuit elements, are fixed at predetermined positions on the wiring pattern 13 by brazing their respective terminals. In addition, 13a,..., 13f
indicates a microstrip line formed by the wiring pattern 13, and 17 is a mounting flange made of a metal material such as Cu or Al, which is brazed to a part of the lower surface of the insulating substrate 12.

Further, a plurality of power terminal portions 20 are provided along one side of the insulating substrate 12 so as to be sandwiched between the input terminal 18 and the output terminal 19. These power supply terminal parts 20 each have a capacitance of 100 with respect to the power supply terminal 21.
A capacitor 22 of about 0 pF is provided, and the capacitor 22 is formed in the thickness direction of the insulating substrate 12. That is, the capacitor 22 is formed by patterning a copper foil on the insulating substrate 12 so that the lower plate 23 becomes a common plate for a plurality of capacitors 22, and the lower plate 23 is connected to a grounding part (not shown). ing. Further, directly above the lower electrode plate 23, a dielectric layer 24 is provided to have a predetermined area and a predetermined thickness of, for example, 100 μm or less, and further, directly above the dielectric layer 24, an upper electrode A plate 25 is formed, and a power terminal 21 is attached to the upper surface of the upper electrode plate 25 by brazing and integrated. One end of a lead wire 26 is brazed to the upper surface of the upper electrode plate 25, and the other end of the lead wire 26 is brazed to a power input unit base 27 formed as a part of the wiring pattern 13. ing.

According to the first embodiment configured as described above, the capacitor 22 provided in the power supply terminal section 20 is
At the position where the power terminal 21 is formed, the insulating substrate 12
The bipolar plates 23 and 25 and the dielectric layer 24 are stacked so as to take up a mounting area of approximately the same size as the polar plates 23 and 25 in the thickness direction. Therefore, the area for mounting the capacitor 22, which was conventionally required separately from the power supply terminal 21, is no longer required, and the power supply terminal section 20 can be configured with a smaller area, making it possible to reduce the size and weight of the device. In addition, more elements can be mounted on the insulating substrate 12 per the same area, and it is also possible to implement more complex circuit configurations where the number of elements and the like and the number of power supply terminals 12 has increased due to the demand for multifunctionality. , it is possible to easily handle this by integrating devices. Further, in the power terminal section 20, each capacitor 22 has a common lower plate 23 connected to the ground, and a dielectric layer 24 is provided thereon in a common manufacturing process or in the same manufacturing process, and an upper plate 25 is provided. Since it can be formed by providing a capacitor 22, it is easy to manufacture and the characteristics can be easily made uniform.Furthermore, since the capacitor 22 can be connected directly to the power supply line without running extra wiring, the performance of the device can be improved. be able to.

Next, a second embodiment will be explained with reference to FIG. Note that this embodiment uses MMIC (Monolithic
This was done for a Microwave IC package, and FIG. 4 is a cross-sectional view. In the figure, 28 is M
The MIC is placed on the upper surface of a metal stem 29 that serves as a substrate. Reference numeral 30 denotes an input terminal fixed to the upper surface of an insulating layer 31 layered on one side of the upper surface of the stem 29, and the input terminal 30 and the corresponding input terminal 32 of the MMIC 28 are connected by a bonding wire 33. Also 34
is a power terminal section, which includes a capacitor 35 and a power terminal 36. The capacitor 35 is provided with a lower electrode plate 37 fixed to the other side of the upper surface of the stem 29. The capacitor 35 has a lower electrode plate 37 and a dielectric layer 3 in the thickness direction of the stem 29.
8. A dielectric layer 38 is sandwiched between an upper electrode plate 39 and both electrode plates 37 and 39, and a power terminal 36 is fixed to the upper surface of the upper electrode plate 39. Furthermore, power terminal 36 and M
The corresponding power terminal 40 of the MIC 28 is connected by a bonding wire 41. And stem 29
A capacitor 35 is provided between the power supply line and the ground by connecting it to ground.

According to the second embodiment configured as described above, the capacitor 35 provided in the power supply terminal section 34 is
At the position where the power supply terminal 36 is formed, the bipolar plates 37, 39 and the dielectric layer 3 are arranged so that the mounting area is approximately the same size as the polar plates 37, 39 in the thickness direction of the stem 29.
8 are stacked on top of each other. For this reason, the power terminal 36
Since a separate mounting area is not required for the capacitor provided between the capacitor and the ground, the power supply terminal section 34 can be configured with a smaller area, and the device can be made smaller and lighter. Furthermore, even if the number of power supply terminals 36 and the like increases due to multifunctionalization, the size of the device can be kept small and it can be easily integrated.

It should be noted that the present invention is not limited to the above-described embodiments, but can be implemented with appropriate modifications within the scope of the gist.

[0018]

[Effects of the Invention] As is clear from the above description, the present invention reduces the mounting area of the power supply terminal by providing the capacitor of the power supply terminal in the thickness direction of the board in the part where the power supply terminal is formed. The device can be made smaller and the device can be made smaller and lighter.

[Brief explanation of drawings]

FIG. 1 is a plan view of essential parts showing a first embodiment of the present invention.

FIG. 2 is a partial cross-sectional view taken along the line A-A in FIG. 1;

FIG. 3 is a circuit diagram of a first embodiment of the present invention.

FIG. 4 is a sectional view showing a second embodiment of the invention.

FIG. 5 is a plan view of main parts showing a conventional example.

[Explanation of symbols]

12...Insulating substrate (substrate) 14a, 14b...GaAsFET (semiconductor element) 1
6c, 22...Capacitor (circuit element) 20...Power terminal portion 21...Power terminal 23...Lower electrode plate 24...Dielectric layer 25...Upper electrode plate

Claims (1)

[Claims] [Claim 1] A device comprising a semiconductor element and a circuit element provided on a substrate so as to form a predetermined circuit,
At least one power supply terminal portion of the circuit is provided with a capacitor formed of bipolar plates sandwiching a dielectric layer in the thickness direction of the substrate in the part where the power supply terminal is formed, and one of the polar plates of the capacitor. A semiconductor device, wherein the power supply terminal is formed integrally with the semiconductor device.