JP3032038B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3032038B2
JP3032038B2 JP12158191A JP12158191A JP3032038B2 JP 3032038 B2 JP3032038 B2 JP 3032038B2 JP 12158191 A JP12158191 A JP 12158191A JP 12158191 A JP12158191 A JP 12158191A JP 3032038 B2 JP3032038 B2 JP 3032038B2
Authority
JP
Japan
Prior art keywords
power supply
capacitor
supply terminal
electrode plate
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP12158191A
Other languages
Japanese (ja)
Other versions
JPH04349656A (en
Inventor
義弘 木下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP12158191A priority Critical patent/JP3032038B2/en
Publication of JPH04349656A publication Critical patent/JPH04349656A/en
Application granted granted Critical
Publication of JP3032038B2 publication Critical patent/JP3032038B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】［発明の目的］[Object of the Invention]

【０００２】[0002]

【産業上の利用分野】本発明は、例えば高周波用モジュ
ールや混成集積回路として形成された半導体装置に関す
る。The present invention relates to a semiconductor device formed as, for example, a high-frequency module or a hybrid integrated circuit.

【０００３】[0003]

【従来の技術】周知の通り、半導体装置の小形高集積化
には目覚ましいものがあり、これに伴い各種機器の小型
化や多機能化が従来以上のテンポで進んでいる。このよ
うな中で、例えば携帯用電話機においても、配線パター
ンが形成された１つのセラミック基板上にチップ抵抗や
チップコンデンサ等の回路素子及び半導体素子をろう付
けして送信用パワーモジュ−ル等の半導体装置を構成し
て、小型化や多機能化に対応するようにしている。一
方、このパワーモジュールには電源ラインからの雑音を
防止するためと発振対策のために、電源ラインと接地の
間にチップコンデンサが設けられている。2. Description of the Related Art As is well known, there are remarkable miniaturization and high integration of semiconductor devices, and accordingly, miniaturization and multifunctionalization of various devices are progressing at a higher tempo than before. Under these circumstances, for example, in a portable telephone, a circuit element such as a chip resistor or a chip capacitor and a semiconductor element are brazed on one ceramic substrate having a wiring pattern formed thereon, and a transmission power module or the like is formed. A semiconductor device is configured to cope with miniaturization and multifunctionalization. On the other hand, in this power module, a chip capacitor is provided between the power supply line and ground to prevent noise from the power supply line and to prevent oscillation.

【０００４】以下、従来技術を図５を参照して説明す
る。図面は携帯用電話機の送信用パワーモジュ−ルを例
示するもので、図５は要部平面図である。図において１
は半導体素子のＧａＡｓＦＥＴで、２は回路素子の横型
のチップコンデンサであり、各素子１，２は図示しない
他のチップ抵抗等の回路素子と共にセラミック基板３上
面に配置され、セラミック基板３上に形成された銅箔の
配線パターン４にろう付けされている。また５は入力端
子、６は出力端子であり、７は電源端子８とチップコン
デンサ２とを備えた電源端子部である。なお電源端子８
はセラミック基板３の一辺に銅箔をパターニングして配
列された電源端子ベッド８a上面にろう付けされてお
り、セラミック基板３の下面には、例えば銅（Ｃｕ）も
しくはアルミニウム（Ａｌ）の取付フランジ９がろう付
けされている。[0004] The prior art will be described below with reference to FIG. The drawing illustrates a transmission power module of a portable telephone, and FIG. 5 is a plan view of a main part. 1 in the figure
Is a GaAs FET of a semiconductor element, 2 is a horizontal chip capacitor of a circuit element, and each of the elements 1 and 2 is arranged on the upper surface of the ceramic substrate 3 together with circuit elements such as other chip resistors (not shown) and formed on the ceramic substrate 3. The wiring pattern 4 of the copper foil is brazed. Reference numeral 5 denotes an input terminal, reference numeral 6 denotes an output terminal, and reference numeral 7 denotes a power supply terminal portion including a power supply terminal 8 and a chip capacitor 2. Power supply terminal 8
Is brazed to the upper surface of a power supply terminal bed 8a in which copper foil is patterned and arranged on one side of the ceramic substrate 3, and a mounting flange 9 made of, for example, copper (Cu) or aluminum (Al) is formed on the lower surface of the ceramic substrate 3. Is brazed.

【０００５】そして電源端子部７のチップコンデンサ２
は、その両端を銅箔をパターニングして形成したコンデ
ンサ端子ベッド２a ，２b にろう付けされており、一方
のコンデンサ端子ベッド２a と電源端子ベッド８aとは
リード線１０によって接続されている。また他方のコン
デンサ端子ベッド２b には内面がメタライズ化されたス
ルーホール１１が形成されていて、このスルーホール１
１によってコンデンサ端子ベッド２b はセラミック基板
３の裏面の接地部に接続されている。The chip capacitor 2 of the power supply terminal 7
Are soldered to capacitor terminal beds 2a and 2b formed by patterning copper foil at both ends, and one capacitor terminal bed 2a and the power supply terminal bed 8a are connected by a lead wire 10. In the other capacitor terminal bed 2b, a through hole 11 having an inner surface metallized is formed.
1, the capacitor terminal bed 2b is connected to the ground portion on the back surface of the ceramic substrate 3.

【０００６】しかしながら上記の従来技術においては、
雑音抑止及び発振防止のためのコンデンサを電源ライン
と接地との間に設けるために、セラミック基板３上にチ
ップコンデンサ２及びコンデンサ端子ベッド２a ，２b
を設けなければならず電源端子部７の小型化を困難なも
のにしている。また多機能化の要求によってより集積化
した複雑な回路構成となる場合には、これに対応するた
めにセラミック基板３へ搭載する各素子１，２等が増
し、電源端子８の数が増すようになり、同時にチップコ
ンデンサ２及びコンデンサ端子ベッド２a ，２b の数が
増して電源端子部７の専有する実装面積が増すことにな
って、同様に多機能小型化及び軽量化を実現するのに自
ずと限度が生じてくる。[0006] However, in the above prior art,
In order to provide a capacitor for suppressing noise and preventing oscillation between the power supply line and the ground, a chip capacitor 2 and capacitor terminal beds 2a, 2b are provided on a ceramic substrate 3.
This makes it difficult to reduce the size of the power supply terminal 7. In the case where a complicated circuit configuration becomes more integrated due to a demand for multi-functionality, the number of elements 1, 2 and the like mounted on the ceramic substrate 3 is increased to cope with this, and the number of power supply terminals 8 is increased. At the same time, the number of the chip capacitors 2 and the capacitor terminal beds 2a and 2b increases, and the mounting area occupied by the power supply terminal unit 7 increases. Similarly, it is naturally necessary to realize multifunctional miniaturization and weight reduction. Limits arise.

【０００７】[0007]

【発明が解決しようとする課題】上記のような小型化及
び軽量化の実現が困難な状況に鑑みて本発明はなされた
もので、その目的とするところは電源端子部の各素子の
構成を変え、電源端子部の実装面積を小さくするように
して、小型化及び軽量化を実現した半導体装置を提供す
ることにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances in which it is difficult to realize the miniaturization and weight reduction. Another object is to provide a semiconductor device which is reduced in size and weight by reducing the mounting area of a power supply terminal portion.

【０００８】［発明の構成］[Structure of the Invention]

【０００９】[0009]

【課題を解決するための手段】本発明の半導体装置は、
基板上に、所定の回路が形成されるよう半導体素子及び
回路素子を設けてなるものにおいて、回路の少なくとも
一つの電源端子部には、電源端子の形成部分上に下極板
が固着され、かつ該下極板と上極板の間に誘電体層を挟
んで形成したコンデンサが前記基板の厚さ方向に設けら
れていると共に、該コンデンサの前記上極板上に前記電
源端子が一体化するように形成されており、さらに前記
上極板と前記半導体素子もしくは回路素子とがリード線
によって接続されていることを特徴とするものである。According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device and a circuit element are provided on a substrate so that a predetermined circuit is formed. At least one power terminal portion of the circuit has a lower electrode plate on a portion where the power terminal is formed.
Are fixed, and a dielectric layer is sandwiched between the lower electrode plate and the upper electrode plate.
Capacitors formed in the thickness direction of the substrate
And the electrode on the upper plate of the capacitor.
The source terminal is formed so as to be integrated, and
The upper electrode plate and the semiconductor element or circuit element are lead wires
The connection is characterized by the following.

【００１０】[0010]

【作用】上記のように構成された半導体装置は、電源ラ
インに並列に挿入する電源端子部のコンデンサを、その
両極板が基板の厚さ方向に誘電体層を挟むようにして基
板の電源端子の形成部分に形成すると共に、コンデンサ
の極板に電源端子を固着し、さらに電源端子と所定回路
を構成する半導体素子もしくは回路素子とがリード線に
よって接続される構成としており、これによりコンデン
サを設けるスペースと電源端子を設けるスペースとが基
板上で共用できて電源端子部の実装面積が小さくでき、
製造も容易であることから装置の小型化及び軽量化が容
易に実現できることになり、また電源ラインからの雑音
は電源端子からコンデンサに流れやすくなり、リード線
によって接続された半導体素子もしくは回路素子には流
れにくくなって雑音防止がより効果的となる。In the semiconductor device constructed as described above, the capacitor of the power supply terminal portion inserted in parallel to the power supply line is formed by forming the power supply terminal of the substrate such that both electrode plates sandwich the dielectric layer in the thickness direction of the substrate. and forming the portion to secure the power supply terminal to the electrode plate of the capacitor, and a semiconductor device or circuit element further forming the power supply terminal and a predetermined circuit and configured to be connected by leads, thereby capacitor
The space for installing the power supply and the space for
It can be shared on a board, and the mounting area of the power supply terminal can be reduced.
Since the production is easy, miniaturization and weight reduction of the device are acceptable.
The noise can be easily realized, and the noise from the power supply line can easily flow from the power supply terminal to the capacitor, so that the noise hardly flows to the semiconductor element or the circuit element connected by the lead wire, and the noise can be more effectively prevented.

【００１１】[0011]

【実施例】以下、本発明の実施例を図面を参照して説明
する。Embodiments of the present invention will be described below with reference to the drawings.

【００１２】先ず、第１の実施例を図１乃至図３により
説明する。なお、本実施例は上記の従来例と同じく携帯
用電話機の送信用パワーモジュールについて成されたも
ので、図１は要部平面図であり、図２は図１のＡ−Ａ矢
視方向の部分断面図であり、図３は回路図である。図に
おいて１２は例えば厚さ０．６３５ｍｍのセラミック材
料等で形成された絶縁基板で、絶縁基板１２の上面には
図３に示す回路を形成するように所定の配線パターン１
３が形成されている。１４a ，１４b は半導体素子のＧ
ａＡｓＦＥＴであり、ＧａＡｓＦＥＴ１４a，１４b は
回路素子のチップ抵抗１５a ，…，１５d 及びチップコ
ンデンサ１６a ，…，１６d と共に配線パターン１３の
所定の位置にそれぞれの端子をろう付けによって固定さ
れている。なお、１３a，…，１３f は配線パターン１
３が形成するマイクロストリップ線路を示し、１７は絶
縁基板１２の下面側の一部にろう付けされた、例えばＣ
ｕやＡｌの金属材料でなる取付フランジである。First, a first embodiment will be described with reference to FIGS. This embodiment is directed to a transmission power module of a portable telephone as in the above-described conventional example. FIG. 1 is a plan view of a main part, and FIG. 2 is a view in the direction of arrows AA in FIG. FIG. 3 is a partial sectional view, and FIG. 3 is a circuit diagram. In the drawing, reference numeral 12 denotes an insulating substrate formed of, for example, a ceramic material having a thickness of 0.635 mm, and a predetermined wiring pattern 1 is formed on the upper surface of the insulating substrate 12 so as to form the circuit shown in FIG.
3 are formed. 14a and 14b are G of the semiconductor element.
Each of the GaAs FETs 14a, 14b is fixed to a predetermined position of the wiring pattern 13 by brazing together with chip resistors 15a,..., 15d of circuit elements and chip capacitors 16a,. .., 13f are wiring patterns 1
Reference numeral 3 denotes a microstrip line formed, and reference numeral 17 denotes, for example, C brazed to a part of the lower surface side of the insulating substrate 12.
The mounting flange is made of a metal material such as u or Al.

【００１３】また、絶縁基板１２の一辺に沿った部分に
は入力端子１８及び出力端子１９に挟まれるようにして
複数の電源端子部２０が設けられている。これらの電源
端子部２０はそれぞれ電源端子２１と静電容量が１００
０ｐＦ程度のコンデンサ２２を備えており、コンデンサ
２２は絶縁基板１２の厚さ方向に形成されている。すな
わちコンデンサ２２は、下部極板２３を絶縁基板１２上
に銅箔をパターニングして複数のコンデンサ２２に共通
の極板となるように形成され、この下部極板２３を図示
しない接地部に接続している。また下部極板２３の直上
には、例えば１００μｍ以下の所定の厚さで所定の面積
を有するように設けられた誘電体層２４が成層されてお
り、さらに誘電体層２４の直上には上部極板２５が形成
されて構成されていて、上部極板２５の上面には電源端
子２１がろう付けにより取り付けられ一体化されてい
る。そして上部極板２５の上面にはリード線２６の一端
部がろう付けされており、またリード線２６の他端部は
配線パターン１３の一部として形成された電源入力部ベ
ース２７にろう付けされている。Further, a plurality of power supply terminal portions 20 are provided in a portion along one side of the insulating substrate 12 so as to be sandwiched between the input terminal 18 and the output terminal 19. Each of these power supply terminals 20 has a capacitance of 100 and a power supply terminal 21.
A capacitor 22 of about 0 pF is provided, and the capacitor 22 is formed in the thickness direction of the insulating substrate 12. That is, the capacitor 22 is formed by patterning a copper foil on the lower electrode plate 23 on the insulating substrate 12 so as to be a common electrode plate for the plurality of capacitors 22. The lower electrode plate 23 is connected to a grounding portion (not shown). ing. A dielectric layer 24 having a predetermined thickness of, for example, 100 μm or less and having a predetermined area is formed immediately above the lower electrode plate 23, and an upper electrode is formed immediately above the dielectric layer 24. The power supply terminal 21 is attached to the upper surface of the upper electrode plate 25 by brazing and is integrated therewith. One end of a lead wire 26 is brazed to the upper surface of the upper electrode plate 25, and the other end of the lead wire 26 is brazed to a power input base 27 formed as a part of the wiring pattern 13. ing.

【００１４】上記のように構成された第１の実施例によ
れば、電源端子部２０に設けられるコンデンサ２２は、
電源端子２１が形成される位置において、絶縁基板１２
の厚さ方向にその極板２３，２５の大きさと略同じ大き
さの実装面積をとるように両極板２３，２５と誘電体層
２４が積み重ねられて形成される。このため従来は電源
端子２１とは別に必要としていたコンデンサ２２の実装
用の面積が不要となり、より小さい面積部分で電源端子
部２０は構成できることになり、装置の小型軽量化が実
現できる。また同じ面積当たりではより多くの素子等が
絶縁基板１２上に実装できることになり、多機能化の要
求によって各素子等の数が増し電源端子１２の数が増し
たより複雑な回路構成に対しても、装置を集積化して容
易に対応することができる。さらに電源端子部２０は各
コンデンサ２２が接地部に接続される下部極板２３を共
通にし、その上に共通の製造過程、あるいは同一の製造
過程の中で誘電体層２４を設け上部極板２５を設けるこ
とで形成できるため、製造が容易であると共に容易に特
性を揃えることができ、さらにまたコンデンサ２２を余
分な配線を引き回さず直接電源ラインに接続できるた
め、装置の性能向上を図ることができる。According to the first embodiment configured as described above, the capacitor 22 provided at the power supply terminal 20 is
In the position where the power terminal 21 is formed, the insulating substrate 12
The two electrode plates 23, 25 and the dielectric layer 24 are formed so as to have a mounting area substantially the same as the size of the electrode plates 23, 25 in the thickness direction. For this reason, the mounting area for the capacitor 22 which has conventionally been required separately from the power supply terminal 21 is not required, and the power supply terminal section 20 can be configured with a smaller area, and the device can be reduced in size and weight. In addition, more elements and the like can be mounted on the insulating substrate 12 in the same area per unit area, and even for a more complicated circuit configuration in which the number of each element and the like and the number of the power supply terminals 12 increase due to the demand for multifunctionality. In addition, the device can be easily integrated by integrating the devices. Further, the power supply terminal section 20 has a common lower electrode plate 23 to which each capacitor 22 is connected to the grounding section, on which a dielectric layer 24 is provided in a common manufacturing process or in the same manufacturing process. , The characteristics can be easily manufactured and the characteristics can be easily adjusted. Further, since the capacitor 22 can be directly connected to the power supply line without routing extra wiring, the performance of the device is improved. be able to.

【００１５】次に、第２の実施例を図４により説明す
る。なお、本実施例はＭＭＩＣ（Monolithic Microwave
IC ）パッケージについて成されたもので、図４は断面
図である。図において２８はＭＭＩＣで、基板となる金
属性のステム２９の上面に載置されている。３０はステ
ム２９の上面の一辺部に成層された絶縁層３１の上面に
固着された入力端子で、入力端子３０とＭＭＩＣ２８の
対応する入力端子３２とはボンディングワイヤ３３によ
って接続されている。また３４は電源端子部で、コンデ
ンサ３５と電源端子３６を備えている。コンデンサ３５
はステム２９の上面の他の一辺部に下極板３７を固着し
て設けられている。コンデンサ３５はステム２９の厚さ
方向に下極板３７、誘電体層３８、上極板３９と両極板
３７，３９で誘電体層３８を挟むような形態に形成され
ており、上極板３９の上面に電源端子３６が固着されて
いる。さらに電源端子３６とＭＭＩＣ２８の対応する電
源端子４０とはボンディングワイヤ４１によって接続さ
れている。そして、ステム２９を接地するように接続す
ることにより電源ラインと接地との間にコンデンサ３５
が設けられる。Next, a second embodiment will be described with reference to FIG. In this embodiment, the MMIC (Monolithic Microwave
FIG. 4 is a cross-sectional view of an IC) package. In the figure, reference numeral 28 denotes an MMIC which is mounted on the upper surface of a metal stem 29 serving as a substrate. Reference numeral 30 denotes an input terminal fixed to the upper surface of an insulating layer 31 formed on one side of the upper surface of the stem 29. The input terminal 30 is connected to the corresponding input terminal 32 of the MMIC 28 by a bonding wire 33. Reference numeral 34 denotes a power supply terminal portion, which includes a capacitor 35 and a power supply terminal 36. Capacitor 35
The lower electrode plate 37 is fixedly provided on the other side of the upper surface of the stem 29. The capacitor 35 is formed such that the lower electrode plate 37, the dielectric layer 38, the upper electrode plate 39 and the both electrode plates 37, 39 sandwich the dielectric layer 38 in the thickness direction of the stem 29. A power terminal 36 is fixed to the upper surface of the power supply terminal. Further, the power supply terminal 36 and the corresponding power supply terminal 40 of the MMIC 28 are connected by a bonding wire 41. By connecting the stem 29 to the ground, the capacitor 35 is connected between the power supply line and the ground.
Is provided.

【００１６】上記のように構成された第２の実施例によ
れば、電源端子部３４に設けられるコンデンサ３５は、
電源端子３６が形成される位置において、ステム２９の
厚さ方向にその極板３７，３９の大きさと略同じ大きさ
の実装面積をとるように両極板３７，３９と誘電体層３
８が積み重ねられて形成される。このため電源端子３６
と接地との間に設けられるコンデンサのために別に実装
用の面積を必要としなくなり、より小さい面積で電源端
子部３４は構成できることになり、装置の小型軽量化が
実現できる。また多機能化して電源端子３６等の数が増
しても装置の大きさが小さいままで容易に集積化して対
応することができる。According to the second embodiment configured as described above, the capacitor 35 provided at the power supply terminal 34 is
At the position where the power supply terminal 36 is formed, the bipolar plates 37 and 39 and the dielectric layer 3 are arranged so as to have a mounting area in the thickness direction of the stem 29 substantially equal to the size of the plates 37 and 39.
8 are stacked and formed. Therefore, the power supply terminal 36
A separate mounting area is not required for the capacitor provided between the power supply terminal and the ground, and the power supply terminal section 34 can be configured with a smaller area, so that the device can be reduced in size and weight. Further, even if the number of power supply terminals 36 and the like is increased due to multi-functionality, it is possible to easily integrate and cope with the device with a small size.

【００１７】尚、本発明は上記の実施例のみに限定され
るものではなく、要旨を逸脱しない範囲内で適宜変更し
て実施し得るものである。It should be noted that the present invention is not limited to only the above-described embodiment, but can be implemented with appropriate modifications without departing from the scope of the present invention.

【００１８】[0018]

【発明の効果】以上の説明から明らかなように、本発明
は、電源端子部のコンデンサを電源端子の形成部分に基
板の厚さ方向に設け、また電源端子と半導体素子もしく
は回路素子とをリード線によって接続する構成としたこ
とにより、電源端子部の実装面積が小さくできて装置の
小型化及び軽量化を容易に実現することができ、また電
源ラインからの雑音をより効果的に防止することができ
る。 As is apparent from the above description, according to the present invention, the capacitor of the power supply terminal portion is based on the portion where the power supply terminal is formed.
Provided in the thickness direction of the board, and have power terminals and semiconductor elements or
Is configured to connect circuit elements with lead wires.
With this, the mounting area of the power supply terminal can be reduced,
Size and weight reduction can be easily realized, and
Noise from the source line can be more effectively prevented
You.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施例を示す要部平面図であ
る。FIG. 1 is a main part plan view showing a first embodiment of the present invention.

【図２】図１のＡ−Ａ矢視方向の部分断面図である。FIG. 2 is a partial sectional view taken in the direction of arrows AA in FIG.

【図３】本発明の第１の実施例の回路図である。FIG. 3 is a circuit diagram of a first embodiment of the present invention.

【図４】本発明の第２の実施例を示す断面図である。FIG. 4 is a sectional view showing a second embodiment of the present invention.

【図５】従来例を示す要部平面図である。FIG. 5 is a plan view of a main part showing a conventional example.

【符号の説明】[Explanation of symbols]

１２…絶縁基板（基板） １４a ，１４b …ＧａＡｓＦＥＴ（半導体素子） １６c ，２２ …コンデンサ（回路素子） ２０…電源端子部 ２１…電源端子 ２３…下極板 ２４…誘電体層 ２５…上極板 DESCRIPTION OF SYMBOLS 12 ... Insulating board (substrate) 14a, 14b ... GaAsFET (semiconductor element) 16c, 22 ... Capacitor (circuit element) 20 ... Power supply terminal part 21 ... Power supply terminal 23 ... Lower electrode plate 24 ... Dielectric layer 25 ... Upper electrode plate

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 基板上に、所定の回路が形成されるよう
半導体素子及び回路素子を設けてなるものにおいて、前
記回路の少なくとも一つの電源端子部には、電源端子の
形成部分上に下極板が固着され、かつ該下極板と上極板
の間に誘電体層を挟んで形成したコンデンサが前記基板
の厚さ方向に設けられていると共に、該コンデンサの前
記上極板上に前記電源端子が一体化するように形成され
ており、さらに前記上極板と前記半導体素子もしくは回
路素子とがリード線によって接続されていることを特徴
とする半導体装置。A semiconductor device and a circuit element provided on a substrate so that a predetermined circuit is formed, wherein at least one power terminal portion of the circuit has a power terminal.
A lower electrode plate is fixed on the forming portion, and the lower electrode plate and the upper electrode plate are fixed.
A capacitor formed with a dielectric layer interposed between the substrate
And in front of the capacitor.
The power supply terminal is formed on the upper electrode plate so as to be integrated.
The upper electrode plate and the semiconductor element or circuit.
A semiconductor device, wherein a circuit element is connected by a lead wire .
JP12158191A 1991-05-28 1991-05-28 Semiconductor device Expired - Fee Related JP3032038B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12158191A JP3032038B2 (en) 1991-05-28 1991-05-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12158191A JP3032038B2 (en) 1991-05-28 1991-05-28 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH04349656A JPH04349656A (en) 1992-12-04
JP3032038B2 true JP3032038B2 (en) 2000-04-10

Family

ID=14814789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12158191A Expired - Fee Related JP3032038B2 (en) 1991-05-28 1991-05-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3032038B2 (en)

Also Published As

Publication number Publication date
JPH04349656A (en) 1992-12-04

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