JPH043450A - Resin sealed semiconductor device - Google Patents
Resin sealed semiconductor deviceInfo
- Publication number
- JPH043450A JPH043450A JP2105083A JP10508390A JPH043450A JP H043450 A JPH043450 A JP H043450A JP 2105083 A JP2105083 A JP 2105083A JP 10508390 A JP10508390 A JP 10508390A JP H043450 A JPH043450 A JP H043450A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- holes
- epoxy
- slippage
- recessed grooves
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 229920005989 resin Polymers 0.000 title abstract description 6
- 239000011347 resin Substances 0.000 title abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 15
- 239000003822 epoxy resin Substances 0.000 abstract description 14
- 229920000647 polyepoxide Polymers 0.000 abstract description 14
- 238000000748 compression moulding Methods 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 5
- 238000007789 sealing Methods 0.000 abstract description 5
- 230000008646 thermal stress Effects 0.000 abstract description 5
- 230000007423 decrease Effects 0.000 abstract description 2
- 230000006835 compression Effects 0.000 description 6
- 238000007906 compression Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、樹脂封止型半導体装置の内部構造に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the internal structure of a resin-sealed semiconductor device.
第５図〜第７図は一般的な樹脂封止型電力半導体装置を
示すもので、図において、１は牛導体チンプ２が搭載さ
れる金属基板、３は封止用エポキシ樹脂、４はリード線
である。５は金属基板１のチップ搭載周辺部に圧縮成形
加工を施した圧縮成形部であり、これは上記金属基板１
と封止用エポキシ樹脂３との界面面積を増すことで密奢
性企高め、また沿面距離を増加させることで、外部から
の水の浸入をより防ぎ、半導体の信頼性を向上させる目
的でなされる。Figures 5 to 7 show general resin-sealed power semiconductor devices. In the figures, 1 is a metal substrate on which a conductor chimp 2 is mounted, 3 is an epoxy resin for sealing, and 4 is a lead. It is a line. Reference numeral 5 denotes a compression molded part which is formed by compression molding the chip mounting peripheral part of the metal substrate 1.
This was done with the purpose of increasing the interface area between the epoxy resin and the sealing epoxy resin 3 to improve sealability, and increasing the creepage distance to further prevent water from entering from the outside and improve the reliability of the semiconductor. Ru.
次に作用について説明する。金属基板のチップ搭載周辺
の圧縮成形加工部５は、金属基板トエボキシ樹脂３とい
う異種材料の密着面積を増ＤＯさせ、卆の密着力Ｐ増加
させるとともに、半導体パフケージ裏面からの水の浸入
の経路を距離的に増大させることにより、半導体チップ
への影響を減少させ、信頼性の同上を可能としているこ
とは周知である。なお、その形成方法は、第８図に示す
のが一般的な方法であり、上下よりプレス金型６により
押圧して周辺部をつぶし、変形させることにより行なわ
れる。Next, the effect will be explained. The compression molding processing section 5 around the chip mounting area of the metal substrate increases the adhesion area DO of a dissimilar material called epoxy resin 3 to the metal substrate, increases the adhesion force P of the package, and prevents water from entering from the back surface of the semiconductor puff cage. It is well known that by increasing the distance, the influence on the semiconductor chip can be reduced and reliability can be improved. The general method for forming it is shown in FIG. 8, and is carried out by pressing from above and below with a press die 6 to crush and deform the peripheral portion.
しかしながら最近では、このような半導体の基板への半
田付方式が多様化しく例えば面実装）、その熱ストレス
もかなり大きくなってきている。However, recently, methods for soldering such semiconductors to substrates have diversified (for example, surface mounting), and the thermal stress has also increased considerably.
そのため、圧縮成形部５の密着力は金属基板トエボキシ
樹脂３の膨張係数の差により熱を受けた時点で異種材料
間にすべりを生ずることにより低下し、その効果はうす
れる。そして、高温での半田付時にはこの低下が大きく
、信頼性にも大きく影響するなどの問題点があった。Therefore, the adhesion force of the compression molded part 5 is reduced due to slippage between different materials when heated due to the difference in expansion coefficient of the metal substrate epoxy resin 3, and its effectiveness is diminished. When soldering is carried out at high temperatures, this reduction is large and there is a problem in that reliability is greatly affected.
この発明はこのような点に鑑みてなされたものであり、
チップ搭載基板周辺部に高温にさらされてもその接着力
を低下させない圧縮成形加工部を有する樹脂封圧型半導
体装置を得ることを目的とするＯ
〔課題を解決するための手段〕
この発明は、沿面距離を伸ばすとともに、密着、力を増
大させる目的で設けられた金属基板の圧縮成形部に、複
数個の貫通穴または凹溝を設けたものである。This invention was made in view of these points,
An object of the present invention is to obtain a resin-sealed semiconductor device having a compression-molded part that does not reduce its adhesive strength even when exposed to high temperatures around the peripheral part of a chip-mounted substrate. A plurality of through holes or grooves are provided in the compression molded portion of the metal substrate, which is provided for the purpose of increasing creepage distance, adhesion, and force.
第１図、第２図はこの発明の一実施例を示すもので、図
において、７は圧縮成形部５に配設された複数の１通穴
である。FIGS. 1 and 2 show an embodiment of the present invention, and in the figures, reference numeral 7 indicates a plurality of one-through holes provided in the compression molding section 5. FIG.
このようなものにおいて、エポキシ樹脂封止の完了した
半導体が熱ストレスを受けた場合、−船釣には膨張係数
の異なるエポキシ樹脂と金属基板の間にはすべりが生じ
、隙間が発生する場合もあるが、本発明の貫通穴７に充
てんされたエポキシ樹脂は、その材料自身の強度が保て
る限りは、丁べりを阻止する働きがある。In such devices, if the semiconductor that has been sealed with epoxy resin is subjected to thermal stress, slippage may occur between the epoxy resin and the metal substrate, which have different coefficients of expansion, and gaps may occur. However, the epoxy resin filled in the through-hole 7 of the present invention has a function of preventing collapsing as long as the strength of the material itself can be maintained.
よって、同等の熱ストレス比較においては、両材料のＴ
べり距離は、本発明の半導体装置における方が少ないこ
とは明らかである。Therefore, in comparing equivalent thermal stress, T of both materials is
It is clear that the slip distance is smaller in the semiconductor device of the present invention.
これによりエポキシ樹脂−金属基板間の密着力をより低
下させずに、半田付することが可能であり、信頼性が同
上する。As a result, soldering can be performed without reducing the adhesion between the epoxy resin and the metal substrate, and reliability is improved.
なお上記実施例では、貫通穴７を設けたが、Ｔペリに対
して阻止する方向にエポキシ樹脂を充てんする構造であ
れば効果のあることから、この部分に第８図、第４図の
ように穴に代えて凹溝８を設けても同様の効果がある。In the above embodiment, the through hole 7 was provided, but since it is effective if the structure is filled with epoxy resin in the direction of blocking the T-periphery, this part is provided as shown in FIGS. 8 and 4. A similar effect can be obtained by providing grooves 8 instead of holes.
以上のようにこの発明によれば、金属基板の圧縮成形加
工部に複数個の貫通穴また凹溝を設けるという簡琳な構
成にて、接着力の低下をきたさない信頼性の高い樹脂封
止型半導体装置が得られる効果がある。As described above, according to the present invention, highly reliable resin sealing that does not cause a decrease in adhesive strength is achieved by providing a plurality of through holes or grooves in the compression molded part of the metal substrate. This has the effect that a type semiconductor device can be obtained.
第１図はこの発明の一実施例を示す平面図、第２図は第
１図のＴＩ−ＴＩ線の断面図、第８図はこの発明の他の
実施例を示す平面図、第４図は第８図のＩＶ−ＩＶ線の
断面図、第５図、第６図は従来の樹脂封止型半導体の一
般例を示す斜視図と平面図、第７図は第６図の■−■線
の断面図、第８図は一般的金属基板の圧縮成形部の成形
方法を示す説明図である。
図中、１は金属基板、２は半導体チップ、３は封止樹脂
、５は圧縮成形部、７は貫通穴、８は凹溝である。
なお図中同一符号に同−丁たけ相当部分をボす。FIG. 1 is a plan view showing one embodiment of this invention, FIG. 2 is a sectional view taken along the line TI-TI in FIG. 1, FIG. 8 is a plan view showing another embodiment of this invention, and FIG. is a sectional view taken along line IV-IV in FIG. 8, FIGS. 5 and 6 are perspective views and plan views showing general examples of conventional resin-sealed semiconductors, and FIG. 7 is a sectional view taken along line IV-IV in FIG. 6. The cross-sectional view of FIG. 8 is an explanatory view showing a method of forming a compression molded part of a general metal substrate. In the figure, 1 is a metal substrate, 2 is a semiconductor chip, 3 is a sealing resin, 5 is a compression molded part, 7 is a through hole, and 8 is a groove. In the drawings, the same reference numerals indicate the same parts.
Claims (1)
、チップをとりまくように配置されてなる複数個の貫通
穴または凹溝を形成したことを特徴とする樹脂封止型半
導体装置。1. A resin-sealed semiconductor device characterized in that a plurality of through holes or grooves are formed in a compression-molded thin part of a metal substrate on which a semiconductor chip is mounted, and are arranged so as to surround the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2105083A JPH043450A (en) | 1990-04-19 | 1990-04-19 | Resin sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2105083A JPH043450A (en) | 1990-04-19 | 1990-04-19 | Resin sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH043450A true JPH043450A (en) | 1992-01-08 |
Family
ID=14398032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2105083A Pending JPH043450A (en) | 1990-04-19 | 1990-04-19 | Resin sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH043450A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5328870A (en) * | 1992-01-17 | 1994-07-12 | Amkor Electronics, Inc. | Method for forming plastic molded package with heat sink for integrated circuit devices |
| US5701034A (en) * | 1994-05-03 | 1997-12-23 | Amkor Electronics, Inc. | Packaged semiconductor die including heat sink with locking feature |
| US6455348B1 (en) | 1998-03-12 | 2002-09-24 | Matsushita Electric Industrial Co., Ltd. | Lead frame, resin-molded semiconductor device, and method for manufacturing the same |
| JP2011077216A (en) * | 2009-09-30 | 2011-04-14 | Shindengen Electric Mfg Co Ltd | Semiconductor package and method for manufacturing the same |
| JP2011077215A (en) * | 2009-09-30 | 2011-04-14 | Shindengen Electric Mfg Co Ltd | Semiconductor package |
| US8629566B2 (en) * | 2000-03-17 | 2014-01-14 | International Rectifier Corporation | Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance |
| JP6457144B1 (en) * | 2018-09-19 | 2019-01-23 | 株式会社加藤電器製作所 | Semiconductor module |
| JP2019207998A (en) * | 2018-09-19 | 2019-12-05 | 株式会社加藤電器製作所 | Semiconductor module |
| US10777489B2 (en) | 2018-05-29 | 2020-09-15 | Katoh Electric Co., Ltd. | Semiconductor module |
| IT201900025009A1 (en) * | 2019-12-20 | 2021-06-20 | St Microelectronics Srl | LEADFRAME FOR SEMICONDUCTOR DEVICES, SEMICONDUCTOR PRODUCT AND CORRESPONDING PROCEDURE |
| US11056422B2 (en) | 2018-05-29 | 2021-07-06 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor module |
-
1990
- 1990-04-19 JP JP2105083A patent/JPH043450A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5328870A (en) * | 1992-01-17 | 1994-07-12 | Amkor Electronics, Inc. | Method for forming plastic molded package with heat sink for integrated circuit devices |
| US5455462A (en) * | 1992-01-17 | 1995-10-03 | Amkor Electronics, Inc. | Plastic molded package with heat sink for integrated circuit devices |
| US5701034A (en) * | 1994-05-03 | 1997-12-23 | Amkor Electronics, Inc. | Packaged semiconductor die including heat sink with locking feature |
| US5722161A (en) * | 1994-05-03 | 1998-03-03 | Amkor Electronics, Inc. | Method of making a packaged semiconductor die including heat sink with locking feature |
| US6455348B1 (en) | 1998-03-12 | 2002-09-24 | Matsushita Electric Industrial Co., Ltd. | Lead frame, resin-molded semiconductor device, and method for manufacturing the same |
| US8629566B2 (en) * | 2000-03-17 | 2014-01-14 | International Rectifier Corporation | Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance |
| JP2011077215A (en) * | 2009-09-30 | 2011-04-14 | Shindengen Electric Mfg Co Ltd | Semiconductor package |
| JP2011077216A (en) * | 2009-09-30 | 2011-04-14 | Shindengen Electric Mfg Co Ltd | Semiconductor package and method for manufacturing the same |
| US10777489B2 (en) | 2018-05-29 | 2020-09-15 | Katoh Electric Co., Ltd. | Semiconductor module |
| US11056422B2 (en) | 2018-05-29 | 2021-07-06 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor module |
| JP6457144B1 (en) * | 2018-09-19 | 2019-01-23 | 株式会社加藤電器製作所 | Semiconductor module |
| JP2019207998A (en) * | 2018-09-19 | 2019-12-05 | 株式会社加藤電器製作所 | Semiconductor module |
| JP2019207999A (en) * | 2018-09-19 | 2019-12-05 | 株式会社加藤電器製作所 | Semiconductor module |
| IT201900025009A1 (en) * | 2019-12-20 | 2021-06-20 | St Microelectronics Srl | LEADFRAME FOR SEMICONDUCTOR DEVICES, SEMICONDUCTOR PRODUCT AND CORRESPONDING PROCEDURE |
| US11557547B2 (en) | 2019-12-20 | 2023-01-17 | Stmicroelectronics S.R.L. | Leadframe for semiconductor devices, corresponding semiconductor product and method |
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