JPH04344735A - Header detection circuit - Google Patents

Abstract

PURPOSE:To surely detect a header and to prevent it from being misdiscriminated as the end of data transfer when the header cannot be once detected due to any fault in the header detection circuit detecting the header added to the head of the data inputted in the unit of frames. CONSTITUTION:Upon the detection of a header pattern in a data D1, a comparison section 1 outputs a pulse P1 and 1-frame delay sections 3,4 output pulses P2, P3 resulting from delaying the pulse P1 by 1 frame and 2 frames respectively. AND gates 7-9 and an OR gate 10 output a pulse P4 by receiving at least two of the pulses P1-P3 simultaneously. A header number counter 5 counts the pulse P4 and outputs a processing start pulse P6 when the count reaches a prescribed value or over. The frame counter 6 outputs a processing stop pulse P5 when the counter 6 loses the application of the pulse P4 for one frame or over.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a header detection circuit that detects a header added to the beginning of data sent in frames.

0002

[Prior Art] In a decoding device etc. that decodes encoded data sent in frame units, a message is added to the beginning of the data in order to determine the timing to start the decoding process, etc. It is necessary to detect the header that contains the

FIG. 3 is a block diagram showing an example of the configuration of a conventional header detection circuit, in which a header generation section 32 generates a header pattern D32, data D31 in units of frames and a pattern D32 output from the header generation section 32. A comparison section 31 outputs a processing start pulse P31 when the comparison matches, and a clock that is cleared every time a processing start pulse P31 is output from the comparison section 31 and is synchronized with data D31 is counted, and the count value is The frame counter 33 outputs a processing stop pulse P32 when the number of data in one frame becomes slightly larger than the number of data in one frame.

FIG. 4 is a timing chart of FIG.
As shown in the figure, when the transfer of data in units of frames is started, the comparator 31 compares the data D31 with the header generator 3.
Compare it with the header pattern D32 output from 2,
When a match between the two is detected, a processing start pulse P31 is output. A decoding device or the like that processes the data D31 starts the decoding process etc. from the timing when the first process start pulse P31 is output.

[0005] Also, when the data transfer is completed, the comparator 31
When the processing start pulse P31 is no longer output, the count value of the frame counter 33 becomes equal to or greater than a predetermined value, and the frame counter 33 outputs the processing stop pulse P32. By outputting the processing stop pulse P32,
The decoding device or the like ends its processing.

[0006]

[Problems to be Solved by the Invention] As described above, the conventional header detection circuit detects a problem when the header pattern D32 outputted from the header generation section 32 and the data D31 sent from the transmitting side match only once. Processing start pattern P31
data D sent from the sending side.
Even if there is an error in P.31 and the data contains the same pattern as the header, a processing start pulse P31 is output, and decoding processing etc. are started. That is, since the decoding process and the like are started at the wrong timing, there is a problem in that the decoding process and the like may not go well. Further, in the conventional example described above, if a header cannot be detected even once, a processing stop pulse P32 is output from the frame counter 33, and the decoding process etc. are stopped.

[0007] An object of the present invention is to provide a header that can reliably detect a header added to the beginning of data sent in frames, and that does not output a processing stop pulse even if the header cannot be detected once. The object of the present invention is to provide a detection circuit.

[0008]

[Means for Solving the Problems] In order to achieve the above object, the present invention generates a pattern of the header in a header detection circuit that detects a header added to the beginning of data input in units of frames. a header generation section that compares the input data with the header pattern output from the header generation section and outputs a pulse when the comparison matches, and a comparison section that compares the pulse output from the comparison section for one frame. a first frame delay unit that delays the pulse outputted from the comparison unit; a second frame delay unit that delays the pulse output from the comparison unit by two frames; the comparison unit, the first frame delay unit, and the second frame delay unit; at least two of the
a pulse generating section that outputs a pulse by simultaneously outputting a pulse from the two; a stop pulse output means that outputs a processing stop pulse when the pulse generating section does not output a pulse for one frame period or more; A count value is cleared every time a processing stop pulse is applied from the output means, the count value is incremented every time a pulse is applied from the pulse generator, and a processing start pulse is output when the count value becomes a predetermined value or more. A counter for counting the number of headers is provided.

[0009]

[Operation] When the input data matches the pattern output from the header generation section, a pulse is output from the comparison section. The pulse output from the comparison section is delayed by one frame by the first frame delay section, and delayed by two frames by the second frame delay section. The pulse generating section outputs a pulse by simultaneously outputting a pulse from at least two of the comparing section, the first frame delay section, and the second frame delay section. That is, the pulse generator outputs a pulse even if the comparator does not output a pulse once, and stops outputting a pulse for the first time when the comparator does not output a pulse twice in a row. The stop pulse output means outputs a processing stop pulse when no pulse is output from the pulse generator for one frame period or more. Therefore, even if the comparison section fails to detect a header once, a processing stop pulse will not be output. The header number counting counter clears its count value every time a processing stop pulse is applied from the stop pulse output means, and increments the count value every time a pulse is applied from the pulse generator until the count value exceeds a predetermined value. As a result, a processing start pulse is output. That is, a processing start pulse is output only when a header is detected several times in succession with frame synchronization.

0010

Embodiments Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which includes a comparison section 1, a header generation section 2, and a one-frame delay section 3.
, 4, a header count counter 5, a frame counter 6, AND gates 7 to 9, and an OR gate 10.

The comparator 1 compares the frame unit data D1 sent from the transmission source with the header pattern D2 output from the header generator 2, and outputs a match detection pulse P1 based on a comparison match.

The one-frame delay section 3 outputs a pulse P2 that is obtained by delaying the coincidence detection pulse P1 outputted from the comparison section 1 by one frame. The one-frame delay section 4 outputs a pulse P3 that is obtained by delaying the pulse P2 outputted from the one-frame delay section 3 by one frame.

The AND gate 7 performs the logical product of the coincidence detection pulse P1 outputted from the comparison section 1 and the pulse P3 outputted from the one frame delay section 4. The AND gate 8 takes the logical product of the coincidence detection pulse P1 outputted from the comparator 1 and the pulse P2 outputted from the 1-frame delay unit 3. The AND gate 9 takes the AND of the pulses P2 and P3 output from the one-frame delay sections 3 and 4. The OR gate 10 takes the logical sum of the pulses P1 to P3 output from the AND gates 7 to 9, and outputs the pulse P4. That is, the pulse P
When at least two of P1 to P3 become low level at the same time, OR gate 10 outputs pulse P4.

The frame counter 6 is cleared by the pulse P4 output from the OR gate 10, counts the clock synchronized with the data D1, and when the count value becomes slightly larger than the number of data in one frame, a processing stop pulse P is issued.
Outputs 5.

The header number counter 5 is an n-ary (in this embodiment, it is a hexadecimal) that increments every time a pulse P4 is applied.
It is a counter and outputs a processing start pulse P6 every time the count value reaches "5". Further, the header number counter 5 is cleared every time the processing stop pulse P5 is applied.

FIG. 2 is a timing chart of FIG. 1 from the start to the end of transmission of data D1 in units of frames, and the operation of this embodiment will be explained below with reference to FIGS. 1 and 2.

When transmission of the data D1 in units of frames is started, the header is detected by the comparator 1 at time t1, and a coincidence detection pulse P1 is output. This coincidence detection pulse P1 is delayed by one frame in the one frame delay section 3 and inputted to the AND gates 8 and 9 and the one frame delay section 4. Further, at time t2, which is delayed by one frame from time t1, the header is detected by the comparator 1, and the coincidence detection pulse P
1 is output. At time t2, the AND gate 8 outputs a pulse because the pulses P1 and P2 become low level at the same time, and the OR gate 10 outputs the pulse P4 because the AND gate 8 outputs a pulse. By outputting the pulse P4 from the OR gate 10 at time t2, the header number counter 5 sets its count value to "1".

[0019] Thereafter, the time t at which the header is supposed to be detected
3, t4 (time delayed by 2 or 3 frames from time t2)
Assume that the header is not detected by the comparison unit 1 in . At time t3, since pulses P2 and P3 are output, the AND gate 9 outputs a pulse, and the OR gate 10 outputs a pulse P4. However, time t4
Since only the pulse P3 is output at the time, the OR gate 10 does not output the pulse P4. As a result, the processing stop pulse P5 is output from the frame counter 6, and the count value of the frame number counting counter 5 is cleared to "0".

Thereafter, when the header is detected in the comparator 1 at times t5 and t6, which are one or two frames behind time t4, the pulses P1 and P2 become low level at the same time at time t6, so the OR gate is activated. Pulse signal P4 from 10
is output, and the count value of header number counter 5 becomes "
1”.

[0021] Thereafter, if the comparator 1 erroneously detects a header at time t7, which is one frame later than time t6 and before time t8, the comparator 1 detects the erroneous match shown in (a). Outputs detection pulse P1. However, time t
7, only pulse P1 of pulses P1 to P3 is output, so pulse P4 is not output from OR gate 10, and the count value of header number counter 5 is held as "1". Ru.

Thereafter, at times t8, t9, t10, and t11, which are delayed by 1, 2, 3, and 4 frames from time t6, the OR gate 10 outputs the pulse P4, thereby increasing the count value of the header number counter 5. is “2”, “3”
”, “4”, and “5”, and at time t11 when the count value becomes “5”, a processing start pulse P6 is output. A decoding device or the like that processes the data D1 starts processing such as decoding processing at the timing when the processing start pulse P6 is first output. In addition, the header number counter 5
The data sent from the transmitting side will not be processed and will be discarded before the processing start pulse P6 is output from , but at the start of transmission, the transmitting side will transmit data that may be discarded for several frames. If you do that, there will be no problem.

Assume that after the process is started, the comparison unit 1 does not detect a header at time t12, when the header is supposed to be detected. At time t12, AND gate 9
A pulse is output from the OR gate 10, and a pulse P4 is output from the OR gate 10.
Therefore, the processing stop pulse P5 is not outputted from the frame counter 6. Furthermore, at times t13 and t14, which are one or two frames later than time t12, the AND gates 7 and 8 output pulses, and the OR gate 10 outputs pulse P4, so the frame counter 6 outputs a processing stop pulse. P5 is never output. That is, even if the header cannot be detected once, the processing for the data D1 does not stop.

Thereafter, when the transmission of the data D1 is completed at time t15, the pulse P4 is no longer output from the OR gate 10 at time t16, which is two frames later than time t15, so the processing stop pulse P5 is output from the frame counter 6. is output. After starting the process, the device that processes the data D1 stops the process at the timing when the first process stop pulse P5 is output.

[0025]

[Effects of the Invention] As explained above, the present invention allows only when a header is input multiple times in succession with frame synchronization.
Since the header is detected, even if data contains the same pattern as a header, it will not be mistakenly determined as a header. Therefore, according to the present invention, it is possible to ensure the start timing of processing such as decoding processing that starts processing according to the header detection timing.

Furthermore, the present invention provides a pulse output from the comparison section and a pulse output from the first and second frame delay sections which are delayed by one or two frames. When at least two of these are output simultaneously, a pulse generator is provided that outputs a pulse, and the output pulse is output to stop pulse output means such as the frame counter 6, so the header is Even if it is not detected once, the processing stop pulse will not be output from the stop pulse output means. Therefore, according to the present invention, there is an effect that even if a header cannot be detected once due to some abnormality, the decoding process etc. will not be stopped.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the invention.

FIG. 2 is a timing chart of FIG. 1;

FIG. 3 is a block diagram of a conventional example.

FIG. 4 is a timing chart of FIG. 3;

[Explanation of symbols]

1, 31...Comparison section 2, 32...Header generation section 3, 4...1 frame delay section 5...Header number counter 6, 33...Frame counter 7-9…and gate 10...Or Gate

Claims (2)

[Claims] 1. A header detection circuit that detects a header added to the beginning of data input in units of frames, comprising: a header generation section that generates a pattern of the header; and a header generation section that generates a pattern of the header; a first frame delay section that delays the pulse output from the comparison section by one frame; a first frame delay section that delays the pulse output from the comparison section by one frame; Pulses are simultaneously output from at least two of a second frame delay section that delays the output pulse by two frames, the comparison section, the first frame delay section, and the second frame delay section. By doing so, the pulse generating section that outputs the pulse and the one from the pulse generating section.
If a pulse is not output for a frame period or longer, a stop pulse output means outputs a processing stop pulse, and a count value is cleared every time a processing stop pulse is added from the stop pulse output means, and a pulse is added from the pulse generator. 1. A header detection circuit comprising: a header number counter that increments a count value every time the count value reaches a predetermined value, and outputs a processing start pulse when the count value exceeds a predetermined value. 2. The pulse generating section includes a first AND gate receiving the pulse output from the comparing section and the pulse output from the first frame delay section, and the first frame delay section. The pulse output from the second
a second AND gate that receives as input the pulse output from the frame delay section; and a third AND gate that receives as input the pulse output from the comparison section and the pulse output from the second frame delay section. and gate, the first, second,
2. The header detection circuit according to claim 1, further comprising an OR gate whose input is the output of the third AND gate.