JPS632436A - Frame synchronizing system - Google Patents

Abstract

PURPOSE:To quickly restore a synchronized state when a pseudo synchronizing state is set, by counting synchronization error pulses and forcibly clearing a synchronization protecting circuit when the pulses are counted more than the prescribed number of times within a fixed time. CONSTITUTION:Frame synchronizing error pulses in a pseudo synchronizing state are inputted to a synchronization protecting circuit 10 and counting means 12. When the count value of the synchronizing error pulses of the counting means 12 exceeds a set value in a prescribed time fixed by a timer 14, a signal is outputted to a synchronization protecting circuit clearing means 16 to forcibly clear the circuit 10 so as to set a hunting state again and a synchronizing state is restored. Since the circuit 10 has a prescribed number of protecting stages, the re-hunting state is not set unless the synchronization error pulses are continuously inputted for the prescribed number of times and a state where the pseudo synchronizing state is continued for a long time may be occurred. In order to prevent the occurrence of such state, the re-hunting state is forcibly set by means of the above-mentioned circuits so that the synchronizing-state can be quickly restored.

Description

[Detailed description of the invention] Overview Frame synchronization error pulses in a pseudo-synchronization state are counted by a counting means and crystallized within a predetermined time determined by a timer]
When the count value by the multiple means exceeds a certain set value, the synchronization protection circuit is forcibly cleared by the synchronization protection circuit clearing means, thereby restarting hunting, making it easier to escape from the pseudo synchronization state, and returning to the synchronization state. A frame synchronization method that can be quickly drawn in.

INDUSTRIAL APPLICATION FIELD OF THE INVENTION The present invention relates to a frame synchronization method in a digital transmission device used for PCM communications, etc.

In digital data transmission, information is conveyed using binary codes V] encoded using binary numbers. Data transmission methods include a serial transmission method in which the units (bits) that make up a code are transmitted one by one in time order, and a parallel transmission method in which the information to be transmitted is divided into two or more communication channels and transmitted simultaneously. It can be broadly divided into methods. The serial transmission method is characterized by the fact that the number of communication paths is small, so the transmission band of the line can be used widely, and the transmission band can be used effectively, so this serial transmission method is widely used in recent data transmission systems. used in In this serial transmission system, synchronization is required between the transmitting side and the receiving side, and a frame synchronization system in which this synchronization is performed using a frame composed of a plurality of bits is widely used.

BACKGROUND OF THE INVENTION The upper part of FIG. 2 shows an example of a frame structure of line data applicable to the frame synchronization method of the present invention. As is clear from the frame configuration example in Figure 2, one frame is 12
It is assumed that the frame is composed of subframes, and frame synchronization I signals F 1 and F 2 exist at No. 1 and No. 5 of each frame F. The frame synchronization signals QF and Fo are distinguished from other data signals @D in the frame synchronization circuit by taking the logical values "1.1" and "O" for each successive frame F.

In the frame configuration example shown in FIG. .8.9.10, 11.1
Data signals such as an order-waiting 7 and a counter electrode alarm are inputted to the 2WF.

However, even though it is a data signal, it may temporarily exhibit the same pattern as the frame synchronization signal F (hereinafter referred to as a full-room synchronization pattern). So-called n4-way protection is required to identify the synchronization signals F and Fo.Also, once identified frame 1111 signals F and F
0 temporarily deviates from the synchronization pattern due to noise etc., it is likely to recover soon and the same 1!10. A so-called backward protection is required to prevent frame synchronization signals F1 and Fo from being misidentified as L deviation and re-identifying due to °C hunting.

As one method for such forward protection and backward protection, a signal that matches the frame synchronization pattern for a predetermined number of consecutive frames is transmitted to the same frame as the same one! I] Signal ", F.

When the frame synchronization signal "Fo" differs from the room synchronization pattern for a predetermined number of consecutive frames, it is determined that the synchronization is out of synchronization. Synchronous methods are known.

However, in such a conventional frame synchronization method,
The detection unit may be affected by external noise etc. and become out of synchronization, even though it was in a synchronized state.
111 when repeatedly entering a synchronized state]
Because the protection circuit has multiple backward protection stages, it is difficult to get out of synchronization 1 or out of sync, and the pseudo sync state continues for a long time due to the action of the sync protection circuit even though it is actually out of sync 1 or out of sync 1. There is. If this pseudo-synchronization state continues for a long time, 1. ! , data transmission becomes impossible because the sender and receiver are not synchronized.

The present invention was made in view of the above points, and its purpose is to completely prevent a pseudo-synchronized state from continuing for a long time, and to quickly bring the device into a synchronized state when it becomes a pseudo-synchronized state. The objective is to provide a frame synchronization method.

Means for Solving the Problems The present invention, as shown in the block diagram of FIG. 1, is a synchronization protection circuit 10 that controls the number of protection stages. Consists of a counting means 12 for counting synchronization error pulses, a timer 14, and a synchronization protection circuit clearing means 16 for forcibly clearing (resetting) the synchronization protection circuit when the synchronization error pulse exceeds a set value within a predetermined time. This solves the problems of the prior art described above.

Operation: A frame synchronization error pulse in a pseudo synchronization state is simultaneously input to the synchronization protection circuit 10 and the counting means 12. timer 14
J: If the count of synchronization error pulses by the counting means 12 exceeds a set value within a predetermined time, a signal is output to the synchronization protection circuit clearing means 1G, and the synchronization protection circuit clearing means 16, the synchronization protection circuit 10 is forcibly cleared and returned to the initial state, and the synchronization is brought into the hunting state again.

In this way, in the present invention, since the synchronization protection circuit 10 has a predetermined number of protection stages, if the synchronization error pulse is not inputted consecutively a predetermined number of times, the pseudo synchronization state continues for a long time without entering the rehunting state. However, in order to prevent this kind of pseudo-synchronization state from continuing for a long time, if a synchronization error pulse is counted over a certain set value within a predetermined period of time, a rehunting state is forced. ,
This speeds up the return from a pseudo-synchronized state to a synchronized state.

Embodiments The present invention will be explained in detail below based on embodiments shown in the drawings.

Referring again to FIG. 2, an example of a frame structure in which one frame F is constructed from 12 subframes is shown in the upper row. The above-mentioned J: sea urchin, the first bit and the fifth to third bit are each "1", and the interframe IvI signal F of rOJ
F is inserted, and the other bits are dequis 1' for order wires, counter electrode alarms, etc.

The number is stamped. Furthermore, FIG. 2 shows a time chart of clock pulses and frame pulses of the frame synchronization signals F and Fo in relation to the frame structure.

The frame synchronization signal 1:1 ratio pulse is at a high level every F1, and for example, when the frame synchronization signal is 1/2 as shown in the figure.
It has a day ratio. Similarly, frame synchronization signal 1: o paste 1 Kotoku pulse becomes high level every Fo and becomes 1/2
The frame pulse has a high level at the beginning of each frame F, and has a duty ratio of, for example, 1/2.

Referring now to FIG. 3, a two-dimensional circuit diagram of the present invention is shown, in which the data signal and frame synchronization signal F
, the received data including Fo clears the flop 18.20
is input. The flip-flop 18 receives the Fl 1 clock signal, and the flip-flop 20 receives the 0 clock signal. The output Q of the flip-flop L1 tip 18 is input to the AND gate 22, and the output Q of the flip-flop L1 tip 20 is input to the AND gate 22. AN
The output of the D gate 22 is input to the synchronization protection circuit 10 and also to the counter 12 via the impark 24. Furthermore, a frame pulse that becomes a torque signal at the beginning of each frame F is also input to the synchronization protection circuit 10. The force 1 counter 12 is, for example, a hexadecimal counter, and when the synchronization error pulse is counted 16 times within a predetermined time determined by the timer 14, the output signal of the trubel is applied to the AND gate 2.
Output to 6.

Same one in sync! The JJ protection circuit 10 outputs a trubel signal q, and in an asynchronous state, a 1 level signal is output. This output signal is passed through the inverter 28 to A
The signal is input to the ND gate 26. Furthermore, the same 1g1 protection circuit 1
The output signal from the AND gate 26 is input to the NOR gate 30, and the output signal from the AND gate 26 is also input to the NOR gate 30.
is input. N.

The output signal of the R gate 30 is input to one of the NAND gates 1-32, and a timer 40 with a cycle shorter than one frame is input to the other side of the NAND gate 32, and its output is input to the AND gates 1-34. .

The NO gate 34 has a power supply reset circuit 36 that instantaneously becomes a torque level when the voltage VA is immersed and outputs its restored torque level.
The output signal of the AND gate 34 is input to the synchronization protection circuit 10, and when this signal is a torque signal, the multiple stages of flip-flops are forcibly cleared and the synchronization protection circuit 10 is returned to its initial state. It has become.

However, in the case of a synchronized state, 11 "1" is manually input to the flip-flop [1 knob 18 and "0" is input to the flip-flop 20 for each predetermined I cock signal, so that the output Q of the flip-flop 18 is IJ 1, the output Q of the flip flop 20 also becomes 1.

Therefore, the output of the AND gate 22 becomes "1", which is inverted by the inverter 24 and rOJ is input to the counter 12, so the counter 12 does not count up.

On the other hand, if the detection unit is affected by external noise and becomes out of synchronization, the flip-flop 18.2
Since the logic value "1", rl, is no longer continuously input to 0, the output of the AND gate 22 becomes "1" or rl.
Tsuzuru became OJ. That is, the AND gate 22 comes to output the synchronous error pulse "0" discontinuously or continuously. If the JIJI error pulse is not output a predetermined number of times in succession, the synchronization protection circuit 10 protects the synchronization state, resulting in a so-called pseudo synchronization state.

When this pseudo synchronization state is entered, the frame synchronization error pulse "0" output from the AND gate 22 is inverted by the inverter 24 and input to the counter 12, and the counter 12 is incremented by one. counter 1
As mentioned above, 2 is composed of, for example, a hexadecimal counter, and when the count value of the counter 12 reaches 16 within a predetermined time determined by the timer 14 (for example, the time corresponding to 40 frames), the trubel The signal is output to the AND gate 26. At this time, the synchronization 1 degree circuit 10 is still in the synchronous state, so it outputs a 1-level signal, which is inverted by the inverter 28, and a 1-level signal is input to the AND gate 26. Therefore, the Trubel signal is input to the NOR gate 30 from the AND groups 1 to 26, and the Trubel signal is input from the synchronous cold storage circuit 10. As a result, from NOR goo l-30)
- The signal of the reference signal is output, and this signal is input to the NAND gate 32, thereby outputting a clock (output of the timer 40) with a cycle shorter than one frame length.

Since the input for using the ANDNO gate is the trubel except when the power is turned on, the clock with the period of the timer 40 is output as the output of the △NO gate j.34, so this signal is input to the synchronization protection circuit 10. to forcibly clear (reset) the multiple stages of flip-flops, and
0 is returned to the initial state and re-hunting is started.

According to the embodiment described above, a hexadecimal counter is used as the counter 12, but the counter of the present invention is of course not limited to this, and the predetermined time by the timer 14 can also be set as appropriate. It is.

Effects of the Invention As detailed above, the present invention counts the synchronization error pulses that occur during the process of synchronization when a pseudo synchronization state occurs for some reason, and detects the error pulses more than a predetermined number of times within a certain period of time. By forcibly clearing the synchronization protection circuit and returning to the initial state when the count is counted, the hunting state will be re-entered (h1 has been achieved, so if it becomes a pseudo-synchronization state, it will be pulled into the synchronization state again. This has the effect of quickly achieving the following.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of the present invention, FIG. 2 is a frame configuration example of the present invention and the time cisode of each pulse, and FIG. 3 is a circuit diagram showing an embodiment of the frame synchronization method of the present invention. . 10... Synchronous protection circuit, 12... Counting means (counter), 14.40... Timer, 16... Synchronous protection circuit clearing means, 18.20... Flip flip 11 knob, 22.26. 3
4...AND gate, 24.28...Inverter, 30...NOR gate, 32...NANO gate, 36...Power supply reset circuit.

Claims (1)

[Claims] In a frame synchronization method in digital transmission, in which when frame synchronization is lost and synchronization protection by a synchronization protection circuit (10) is cleared, a synchronization signal is hunted and frame synchronization is again established.Pseudo synchronization Means for counting frame synchronization error pulses in the state (
12), and when the counted value by the counting means (12) exceeds a set value within a predetermined time determined by the timer (14), synchronization protection forcibly clears the synchronization protection circuit (10). A frame synchronization method characterized by providing a circuit clearing means (16) and starting rehunting.