JPH04344711A - Frequency divider - Google Patents

Abstract

PURPOSE:To realize the frequency divider able to reduce the test time by providing the mode to output an input clock as it is so as to avoid frequency division. CONSTITUTION:The frequency divider consists of basic blocks connected in cascade. Each block is formed in such a way that a clock input 3 and an output 4 of a T flip-flop 1 are inputted to a multiplexer 2 and a control signal 5 is used to switch the clock input 3 or the output 4 of the T flip-flop 4 and the output is outputted to an output 6. In the frequency divider in which the basic blocks are connected in cascade, a frequency division ratio is optionally set by setting a control signal input of each stage, and when all the stages are set to the mode not frequency-dividing the input signal at test, the clock is directly fed to the logic circuit clock of the frequency divider and the test is conducted in a short time without frequency division time.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency divider that can easily switch and output a frequency division period.

0002

2. Description of the Related Art In recent years, integrated circuits equipped with frequency dividers have been widely used, and reducing the test time thereof has become an important issue.

A conventional frequency divider will be explained below with reference to the drawings. FIG. 4 is a circuit diagram showing the configuration of a frequency divider made up of conventional T-type flip-flops. In the figure,
T-type flip-flops 1, 2, 3, 4, 5, and 6 are connected in cascade, and the clock input to clock input 7 passes through the six T-type flip-flops, is divided by 64, and is output to output 8. . When a logic circuit operated by this output signal is configured on the same chip of a semiconductor integrated circuit,
In order to test the operation of the logic circuit, this frequency divider always requires a time equal to (input clock period) x 64 (frequency division ratio).

0004

[Problem to be Solved by the Invention] In a semiconductor integrated circuit equipped with such a conventional frequency divider, when testing the operation of a logic circuit operated by the output signal of the frequency divider, it is necessary to If there are many clocks or if the period of the input clock input to the frequency divider is slow, a large amount of time is required.

The present invention solves the above-mentioned problem, and is a frequency divider having a function of shortening the test time of the logic circuit following the output of the frequency divider regardless of the number of stages of flip-flops in the frequency divider. The purpose is to provide equipment.

[0006]

[Means for Solving the Problems] In order to achieve the above object, the present invention consists of cascaded basic blocks that input a clock and output the clock or a clock whose frequency is divided by 1/2 in response to a control signal. are connected to form a frequency divider, and the basic block includes a T-type flip-flop that inputs a clock and divides the frequency by 1/2, and a control signal that switches between the clock and the output of the T-type flip-flop and outputs the output. A frequency divider with a multiplexer.

[0007]

[Operation] In the above configuration, the present invention configures a frequency divider by cascading basic blocks, and the basic blocks in each stage divide the clock frequency by 1/2 according to a control signal, or
Alternatively, the frequency division ratio of the frequency divider is set by outputting the signal as it is without frequency division.

[0008]

[Embodiment] Hereinafter, regarding a frequency divider according to an embodiment of the present invention,
This will be explained with reference to the drawings. FIG. 1 shows a circuit diagram of a basic block configuration of a frequency divider according to the present invention. In the figure, the circuit is constructed of a T-type flip-flop 1 and a multiplexer 2, and is configured to switch between a clock input 3 and an output 4 to be outputted to an output 6 using a control signal 5. Therefore, the clock input 3 can be directly output from the output 6 without being frequency-divided by the T-type flip-flop 1.

FIG. 2 is a circuit diagram showing the structure of a frequency divider constructed by connecting the basic blocks of FIG. 1 in multiple stages. In the figure, 1, 2, 3, 4, 5 and 6 are basic blocks; 9,
10, 11, 12, 13 and 14 are control signal inputs of the respective blocks. By setting all the control signal inputs to be the same, the input clock 7 can be outputted to the output 8 without being frequency-divided at all.

FIG. 3 shows a circuit diagram of an embodiment of an integrated circuit using the frequency divider of the present invention. In the figure, 1 is an oscillation circuit, 2
3 is a frequency divider of the present invention, and 3 is a clock circuit which generates a basic clock to be supplied to the microcomputer 4. In the case of self-sustained oscillation, a certain amount of time is required until the oscillation stabilizes after the oscillation starts. Therefore, the oscillation output from the oscillation circuit 1 is taken into the frequency divider 2, and after creating an oscillation stabilization time, the frequency-divided output from the frequency divider 2 and the oscillation output from the oscillation circuit 1 are taken into the clock circuit 3. The clock circuit 3 supplies a clock to the microcomputer 4 only when the output from cycle 2 is output.

[0011] When testing such a system, a clock is normally supplied from outside during the test. In this case, since a frequency divider is not required, 6, 7, 8 of frequency divider 2,
By switching the control inputs 9, 10, and 11, that is, the portion corresponding to the control input 5 in FIG. 1, the input of the frequency divider 2 in FIG. 3 can be directly output to the clock circuit 3.

As described above, according to the frequency divider according to the embodiment of the present invention, each stage of the frequency divider can be set by the control signal whether to divide the input clock by 1/2 or output it as is. By configuring this, when testing parts other than the frequency divider portion of an integrated circuit, the frequency divider is set so as not to operate at all, and the test can be performed quickly without waiting for the frequency division time.

[0013] When testing the frequency divider, by switching the control input, it is possible to group the flip-flops into small groups or to check the operation of each flip-flop individually.

[0014]

Effects of the Invention As is clear from the embodiments described above, the present invention can input a clock and convert the clock or its half
A frequency divider is configured by cascading basic blocks that output a frequency-divided clock in response to a control signal, and the basic block includes a T-type flip-flop that inputs a clock and divides the frequency by 1/2, and a T-type flip-flop that inputs a clock and divides the frequency by 1/2, and By using a frequency divider equipped with a multiplexer that switches and outputs the output of the T-type flip-flop using a control signal, if there is a logic circuit that operates based on the output of the frequency divider, that logic circuit can be tested. In this case, the frequency divider can be treated as if it were not present, making it possible to test in a short time without using extra time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of basic blocks constituting the frequency divider of the present invention.

FIG. 2 is a circuit diagram showing the configuration of a frequency divider according to an embodiment of the present invention.

[Fig. 3] A circuit diagram showing the configuration of an applied circuit using the frequency divider of the present invention.

[Figure 4] Circuit diagram showing the configuration of a conventional frequency divider

[Explanation of symbols]

1 T-type flip-flop circuit 2 Multiplexer 3 T-type flip-flop clock input 4 T-type flip-flop clock output 5 Multiplexer control signal input 6 Multiplexer output

Claims (1)

[Claims] 1. A frequency divider is configured by cascade-connecting basic blocks that input a clock and output the clock or a clock obtained by dividing the clock by 1/2 in response to a control signal, and the basic blocks input the clock and output the clock or a clock obtained by dividing the clock by 1/2. Input T to divide by 1/2
A frequency divider comprising a T-type flip-flop and a multiplexer that switches and outputs the clock and the output of the T-type flip-flop using a control signal.