JPH043443A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH043443A JPH043443A JP10555390A JP10555390A JPH043443A JP H043443 A JPH043443 A JP H043443A JP 10555390 A JP10555390 A JP 10555390A JP 10555390 A JP10555390 A JP 10555390A JP H043443 A JPH043443 A JP H043443A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- wire bond
- bond pad
- supersonic wave
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 12
- 229910000679 solder Inorganic materials 0.000 abstract description 66
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000005476 soldering Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 230000004907 flux Effects 0.000 description 3
- 238000007598 dipping method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は超音波ワイヤーボンドを行う半導体装置の製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device using ultrasonic wire bonding.
従来の半導体装置の超音波ワイヤーボンドパッドの取付
方法は第３図の様に行っていた。（ａ）図で示すように
、基板部（１）に搭載用電極（２）がパターニングしで
あるものを準備する。次に（ｂ）図で示すように、搭載
用電極（２）の所定位置にはんだペースト（３ンを印刷
法にて印刷して置く。ハンダペースト（３）ははんだの
粉末状のものとフラックス、溶剤を混ぜ合わせペースト
状にしたもので、この例のように、はんだ印刷法でよく
使用される。印刷法は所定の位置に穴が設けであるマス
クの開口より、はんだペースト（３）等ペースト状のも
のを所定の位置に落し込む方法である。この例でははん
だペースト（３）を用いたが、予め、基板部（１）を溶
融はんだの中へ浸漬して取付用電極へはんだを付けてお
いてもよい。その場合は浸漬前後にフラックスを電極面
及び、はんだ面に塗布する必要がある。次に、（Ｃ）図
で示すように、超音波ワイヤーボンド用のパッド（４）
を準備し、搭載用［極（２）の所定位置に乗せる。超音
波ワイヤーボンドは電極に直接行うことも可能であるが
、−船釣にワイヤーボンド用のパッド（４）を用いた方
が、プロセス的に安定するので前述の方法が採用されて
いる。その後、（ｄ）図に示すように、はんだが再溶融
する温度に加熱し、はんだペースト（３）中のはんだを
溶融させ、基板電極とワイヤーボンドパッドのはんだ付
けを行う。その後はんだと分離したフラックスや溶剤を
洗浄を行って洗い流す。最後に、ワイヤー（５）を超音
波を印加しながらパッド（４）の所定位置にボンディン
グをする。The conventional method of attaching an ultrasonic wire bond pad to a semiconductor device is as shown in FIG. (a) As shown in the figure, a substrate part (1) with a patterned mounting electrode (2) is prepared. Next, as shown in figure (b), solder paste (3) is printed at the predetermined position of the mounting electrode (2) using a printing method.Solder paste (3) is a combination of solder powder and flux. , is a paste made by mixing solvents, and is often used in the solder printing method, as shown in this example.The printing method uses solder paste (3) etc. through the opening of a mask with holes in predetermined positions. This is a method in which a paste-like substance is dropped into a predetermined position.In this example, solder paste (3) was used, but in advance, the board part (1) was dipped into molten solder and the solder was applied to the mounting electrode. In that case, it is necessary to apply flux to the electrode surface and the solder surface before and after dipping.Next, as shown in figure (C), add a pad (4) for ultrasonic wire bonding.
Prepare and place it on the designated position of the mounting pole (2). Although it is possible to perform ultrasonic wire bonding directly to the electrode, the above-mentioned method is adopted because the process is more stable if a wire bond pad (4) is used for boat fishing. Thereafter, as shown in Figure (d), the solder is heated to a temperature at which the solder is remelted, the solder in the solder paste (3) is melted, and the substrate electrode and wire bond pad are soldered. After that, the flux and solvent separated from the solder are washed away. Finally, the wire (5) is bonded to a predetermined position on the pad (4) while applying ultrasonic waves.
以下、（ｄ）図を更に詳しく説明する。（０図に従来の
超音波ワイヤーボンドパッドの構造例を示す。The diagram (d) will be explained in more detail below. (Figure 0 shows an example of the structure of a conventional ultrasonic wire bond pad.
この例ではアルミの超音波ワイヤーボンドを例としてい
る。囚のように、この例ではｉ４υはアルミ層、輪は銅
層、輪は予＃Ｍばんだ盾の３層構造となっている。予備
はんだ層（財）ははんだ浬漬により付けている。（２）
図は基板を側面より見たもので、基板（１）に電極（２
）が取り付けである。Φ）図は前述の超音波ワイヤーボ
ンドパッドをはんだ印刷が終了した基板部に搭載しよう
としている。（ｉ）図は所定位置に超音波ワイヤーボン
ドパッドを搭載した状態で一般的に自動化されており、
位置ずｎなくまた基板面に対して平行に置かれている。This example uses aluminum ultrasonic wire bonding. As you can see, this example has a three-layer structure: i4υ is an aluminum layer, the ring is a copper layer, and the ring is a pre-metal shield. The preliminary solder layer is attached by solder dipping. (2)
The figure shows the board viewed from the side, with the board (1) and the electrode (2
) is the installation. Φ) The figure shows the above-mentioned ultrasonic wire bond pad being mounted on a board part on which solder printing has been completed. (i) The figure shows a commonly automated system with ultrasonic wire bond pads in place;
It is placed parallel to the substrate surface without any position.
（ｊ）図ははんだペースト中のはんだを再溶融させるた
め加熱を行っている。この時に、はんだが溶融する過程
を過渡的にみると、溶けはじめは一斉にではなく部分的
に始まるので、図のような場合には、超音波ワイヤーボ
ンドパッドのはんだ層の一部が先ず溶は徐々に溶融部分
が広がるが、はんだは周知の通り溶融状態では表面張力
が大きく、先に溶けた部分に後で溶けたはんだ力・寄り
集まり、その結果、全体のはんだがアンバランスとなり
、傾きが生じる。Figure (j) shows heating to remelt the solder in the solder paste. At this time, if we look at the process of melting the solder transiently, we can see that it begins to melt not all at once but in parts, so in the case shown in the figure, part of the solder layer on the ultrasonic wire bond pad melts first. The melted part gradually spreads, but as is well known, the surface tension of solder in the molten state is large, and the force of the solder that melted later gathers in the part that melted first, resulting in the overall solder becoming unbalanced and tilted. occurs.
その状態の拡大図が（８）図である。Figure (8) is an enlarged view of this state.
従来の半導体装置の製造方法は以上のように構成されて
いたので、全体のはんだがアンバランスによる傾きによ
り、超音波ワイヤーボンドを自動機で行うときに、光学
系視覚認識装置の光を乱反射するため誤動作を誘発する
。仮に誤動作を免れてワイヤーボンドを行っても、超音
波エネルギーが充分にボンディング面に伝わらずボンデ
ィング不良が発生する。また、第３図（ト）の矩に示し
た部分は、はんだが娠り上がっており、環境温度の変化
による、基板（１）とはんだの膨張率の違いによって生
ずる応力の集中が発生し、ここから亀裂が入り電極を断
線せしめ、種々の不具合を発生させるという問題点があ
った。Conventional semiconductor device manufacturing methods were configured as described above, and due to the overall solder being tilted due to imbalance, the light from the optical visual recognition device was diffusely reflected when ultrasonic wire bonding was performed using an automatic machine. This may cause malfunction. Even if wire bonding is performed without malfunction, the ultrasonic energy will not be sufficiently transmitted to the bonding surface, resulting in defective bonding. In addition, in the area shown in the rectangle in Figure 3 (g), the solder has curled up, and stress concentration occurs due to the difference in expansion coefficient between the board (1) and the solder due to changes in environmental temperature. There has been a problem in that cracks can develop from this point, causing the electrode to break and causing various problems.
この発明は上記のような問題点を解決するためになされ
たもので、全体のはんだがアンバランスになることを防
止し傾きの生じない半導体装置の製造方法を得ることを
目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that prevents the entire solder from becoming unbalanced and does not cause tilting.
この発明に係る半導体装置の製造方法は、超音波ワイヤ
ーボンドパッドの予備はんだ層を複数に分割、独立させ
たバンプ構造を取り、同時に、これを搭載する基板の電
極パターンも分割させたものである。In the method for manufacturing a semiconductor device according to the present invention, the preliminary solder layer of the ultrasonic wire bond pad is divided into a plurality of parts to form independent bump structures, and at the same time, the electrode pattern of the substrate on which this is mounted is also divided. .
この発明における超音波ワイヤーボンドパッドは、予備
はんだ層が複数に分割、独立させであるので、はんだ溶
融の過渡期におけるはんだの葉中現象が、分割された部
分、即ちバンプ部分内にとどまる為、大きな量のはんだ
の移動が起らず、その結果超音波ワイヤーボンドパッド
は傾かず、後工程への影蕃は無くなる。In the ultrasonic wire bond pad of the present invention, the pre-solder layer is divided into a plurality of independent layers, so that the solder leaf phenomenon during the transition period of solder melting remains within the divided portions, that is, the bump portions. A large amount of solder movement does not occur, and as a result, the ultrasonic wire bond pad does not tilt, and there is no impact on subsequent processes.
以下、この発明の一実施例を図について説明する。第１
図はこの発明の一実施例である半導体装置の超音波ワイ
ヤーボンドパッドの詳細斜視図である。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a detailed perspective view of an ultrasonic wire bond pad of a semiconductor device which is an embodiment of the present invention.
この実施例では前記従来のものと対比する為、アルミの
超音波ワイヤーボンドパッドを取りあげている。なお、
図中符号は前記従来のものと同一で、アルミ層（転）、
銅層（６）、予備はんだ層（財）の３ｍ構造であるが、
銅層（転）及び予備はんだ層（転）が図の様にパターニ
ングしてあり、分離、独立している。In this example, an aluminum ultrasonic wire bond pad is used for comparison with the conventional example. In addition,
The symbols in the figure are the same as those of the conventional one, and the aluminum layer (rolling),
It has a 3m structure with a copper layer (6) and a preliminary solder layer (goods).
The copper layer (roll) and preliminary solder layer (roll) are patterned as shown in the figure, and are separated and independent.
この分離独立している１つ１つを以下バンプと称する。Each of these separate and independent bumps is hereinafter referred to as a bump.
周知の通り、はんだとアルミは通常なじみが悪く予備は
んだ層−のはんだが再溶融しても、隣接しているバンプ
（６）同士がはんだでつながることはない。As is well known, solder and aluminum usually have poor compatibility, and even if the solder in the preliminary solder layer is remelted, adjacent bumps (6) will not be connected to each other by solder.
第２図（ａ）〜（ｅ）はこの発明の半導体装置の超音波
ワイヤーボンドの接続工程を示す断画図である。FIGS. 2(a) to 2(e) are cross-sectional views showing the ultrasonic wire bonding process of the semiconductor device of the present invention.
初めに、（ａ）図で示す様に、本発明の超音波ワイヤー
ボンドパッド（４）を準備する。次に、（ｂ）図で示す
様に基板（１）を準備する。ついで、（Ｃ）図で示す様
に、基板（１）上の電極（２）へ超音波ワイヤーボンド
パッド（４）の予備半田部（転）に対応する様に半田ペ
ースト（６）を印刷して置く。さらに（ｄ）図の様に前
述の予＆ｆ田部（財）と印刷された半田ペースト（６）
の位置が合う様に、超音波ワイヤーボンドパッド（４）
を置く。First, as shown in Figure (a), an ultrasonic wire bond pad (4) of the present invention is prepared. Next, as shown in figure (b), a substrate (1) is prepared. Next, as shown in figure (C), solder paste (6) is printed on the electrode (2) on the substrate (1) so as to correspond to the preliminary solder part (roll) of the ultrasonic wire bond pad (4). Leave it there. Furthermore, (d) solder paste (6) printed with the aforementioned Yo & F Tabe (foundation) as shown in the figure.
Place the ultrasonic wire bond pads (4) so that
put
この作業は一般的に機械化されており、精度よく短くこ
とが可能である。最後に、（ｅ）図にある様に加熱再溶
融した半田ペースト（６）中の半田と超音波ワイヤーボ
ンドパッド（４）の予備半田に）が一体となり柱状とな
る。この時、前述した様に＠接する半田付部とは分離さ
れている為、溶けた半田が流出あるいは流入しない。又
、各々の半田の量はほぼ均一な為、アンバランスが生じ
ることなく、超音波ワイヤーボンドパッド（４）を基板
（１）面に、はぼ平行に固着することが可能である。This work is generally mechanized and can be shortened with high precision. Finally, as shown in Figure (e), the solder in the heated and remelted solder paste (6) and the preliminary solder on the ultrasonic wire bond pad (4) are integrated into a columnar shape. At this time, as described above, since it is separated from the soldering part in contact with @, the melted solder does not flow out or flow in. Furthermore, since the amount of each solder is approximately uniform, it is possible to fix the ultrasonic wire bond pad (4) to the surface of the substrate (1) almost in parallel without creating an imbalance.
なお、上記実施例では超音波ワイヤーボンドパッドの場
合を示したが、取付面に対して平行に半田付けを行いた
いものであれば前述の構造、即ち、搭載物の半田付面に
３点以上のバンプ部を構成し、被搭載物の半田付面にこ
れに対応する電極のパターン及び、予備半田を施せばよ
いことはいうまでもない。Note that the above example shows the case of an ultrasonic wire bond pad, but if you want to solder parallel to the mounting surface, use the above-mentioned structure, that is, 3 or more points on the soldering surface of the mounted object. Needless to say, it is only necessary to form a bump portion of 1, and apply a corresponding electrode pattern and preliminary solder to the soldering surface of the object to be mounted.
以上のようにこの発明によれば、超音波ワイヤーボンド
パッドにバンブ部を構成し、これに対応する様に基板・
電極のパターン及び予備半田を行うようにしたので、基
板に対して平行にワイヤーボンドパッドを取り付けるこ
とが可能となり、ワイヤーボンドミスを未然に防ぐこと
ができ、又半田の偏りにより生ずる応力集中が解消され
るので安価で、且つ、信頼性の高い半導体装置を得るこ
とができる。As described above, according to the present invention, the bump portion is formed on the ultrasonic wire bond pad, and the substrate and the bump portion are configured to correspond to the bump portion.
By patterning the electrodes and pre-soldering, it is possible to attach the wire bond pads parallel to the board, preventing wire bond mistakes and eliminating stress concentration caused by uneven solder. Therefore, an inexpensive and highly reliable semiconductor device can be obtained.
第１図はこの発明の一実施例である超音波ワイヤーボン
ドパッドの構造を示す斜視図、第２図（ａ）〜（ｅ）は
第１図による超音波ワイヤーボンディングの製造工程を
示す断面図、第３図（ａ）〜（ｅ）は従来の超音波ワイ
ヤーボンディングの製造工程を示す斜視図、第３図（ｆ
）〜（ｊ）は従来の製造工程で特に超音波ワイヤーボン
ドパッドの半田付は部における説明断面図、第３図（３
）は従来の製造工程での半田付は後の超音波ワイヤーボ
ンドパッドの側面よりの拡大断面図である。
図において、（１）は基板、（２）は電極、（３）は半
田ペースト、（４）は超音波ワイヤーボンドパッド、（
５）はワイヤー、（６月ヨ予備半田、（半田ペースト）
、（６）はアルミ層、（６）は銅層、輪は予備半田層を
示す。
なお、図中、同一符号は同一 または相当部分を示す。
４３ 子イ１１鴫ず１１？４FIG. 1 is a perspective view showing the structure of an ultrasonic wire bonding pad according to an embodiment of the present invention, and FIGS. 2(a) to (e) are sectional views showing the manufacturing process of the ultrasonic wire bonding according to FIG. , FIGS. 3(a) to 3(e) are perspective views showing the manufacturing process of conventional ultrasonic wire bonding, and FIG.
) to (j) are explanatory cross-sectional views of the conventional manufacturing process, especially the soldering of ultrasonic wire bond pads;
) is an enlarged cross-sectional view from the side of the ultrasonic wire bond pad after soldering in the conventional manufacturing process. In the figure, (1) is the substrate, (2) is the electrode, (3) is the solder paste, (4) is the ultrasonic wire bond pad, (
5) Wire, (June Yo preliminary solder, (solder paste)
, (6) is an aluminum layer, (6) is a copper layer, and the ring is a preliminary solder layer. In addition, the same symbols in the figures indicate the same or equivalent parts. 43 Child 11 Shizuzu 11?4
Claims (1)
ンドパットと、このワイヤーボンドパットに対応したパ
ターンを有する基板部を備えたことを特徴とする半導体
装置の製造方法。A method for manufacturing a semiconductor device, comprising: an ultrasonic wire bond pad having a bump structure divided into a plurality of parts; and a substrate portion having a pattern corresponding to the wire bond pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10555390A JPH043443A (en) | 1990-04-19 | 1990-04-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10555390A JPH043443A (en) | 1990-04-19 | 1990-04-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH043443A true JPH043443A (en) | 1992-01-08 |
Family
ID=14410756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10555390A Pending JPH043443A (en) | 1990-04-19 | 1990-04-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH043443A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7875496B2 (en) | 2005-05-17 | 2011-01-25 | Panasonic Corporation | Flip chip mounting method, flip chip mounting apparatus and flip chip mounting body |
-
1990
- 1990-04-19 JP JP10555390A patent/JPH043443A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7875496B2 (en) | 2005-05-17 | 2011-01-25 | Panasonic Corporation | Flip chip mounting method, flip chip mounting apparatus and flip chip mounting body |
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