JPS63273398A - Reflow soldering method for printed substrate - Google Patents
Reflow soldering method for printed substrateInfo
- Publication number
- JPS63273398A JPS63273398A JP10629787A JP10629787A JPS63273398A JP S63273398 A JPS63273398 A JP S63273398A JP 10629787 A JP10629787 A JP 10629787A JP 10629787 A JP10629787 A JP 10629787A JP S63273398 A JPS63273398 A JP S63273398A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- land
- printed circuit
- circuit board
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005476 soldering Methods 0.000 title claims description 35
- 238000000034 method Methods 0.000 title claims description 22
- 239000000758 substrate Substances 0.000 title abstract 4
- 229910000679 solder Inorganic materials 0.000 claims abstract description 54
- 239000006071 cream Substances 0.000 claims abstract description 33
- 238000002844 melting Methods 0.000 claims abstract description 3
- 230000008018 melting Effects 0.000 claims abstract description 3
- 238000010438 heat treatment Methods 0.000 claims description 5
- 230000004907 flux Effects 0.000 abstract description 11
- 239000000853 adhesive Substances 0.000 abstract description 5
- 230000001070 adhesive effect Effects 0.000 abstract description 5
- 230000007257 malfunction Effects 0.000 abstract 1
- 239000000843 powder Substances 0.000 abstract 1
- 239000011800 void material Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、クリームはんだを用いたプリント基板とチッ
プ部品のはんだ付け方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of soldering a printed circuit board and a chip component using cream solder.
近時の電子機器は、小型化、軽量化されてきているため
、これに使用する電子部品もチップ部品とかフラットバ
ック型部品(以下、単にチップ部品という)のように非
常に小さいものが用いられるようになってきた。Modern electronic devices are becoming smaller and lighter, so the electronic components used in them are also very small, such as chip components and flatback components (hereinafter simply referred to as chip components). It's starting to look like this.
チップ部品は、はんだ付け部が小さいため、はんだ鏝で
のはんだ付けは行えず、チップ部品のはんだ付けは一般
には「ディップはんだ付け方法」と「リフローはんだ付
け方法」が採られている。Chip components cannot be soldered with a soldering iron because the soldering area is small, so ``dip soldering'' and ``reflow soldering'' are generally used to solder chip components.
ディップはんだ付け方法とは、プリント基板の所定の箇
所にチップ部品をあらかじめ接着剤で仮固定しておき、
それをブラックス塗布、予備加熱した後、溶融はんだに
ディップ(浸漬)シてはんだ付けする方法である。また
、リフローはんだ付け方法とは、プリント基板のラント
にクリームはんだを塗布し、その上にチップ部品を搭載
してからクリームはんだを加熱溶融させることによりは
んだ付けを行う方法である。Dip soldering is a method in which chip components are temporarily fixed in place on a printed circuit board with adhesive in advance.
After coating it with black and preheating it, it is dipped in molten solder and soldered. Furthermore, the reflow soldering method is a method in which cream solder is applied to the runt of a printed circuit board, a chip component is mounted thereon, and then soldering is performed by heating and melting the cream solder.
ディップはんだ付け方法は大掛かりなはんだ付け装置を
必要とするものであり、またはんだ付け時、チップの側
面に残存するフラックスフエームがランドとチップ部品
の隅部への溶融はんだの浸入を邪魔してはんだ付け不良
を起こすという問題があった。リフローはんだ付け方法
はディップはんだ付け方法のようなはんだ付け不良を起
こさないため今回では多く採用されているものである。The dip soldering method requires large-scale soldering equipment, and during soldering, flux frames remaining on the sides of the chip prevent molten solder from penetrating into the lands and corners of the chip components. There was a problem of poor soldering. The reflow soldering method is often used this time because it does not cause soldering defects like the dip soldering method.
従来のリフローはんだ付け方法は、第6図に示すように
プリント基板(1)のランド(2)の全域にクリームは
んだ(3)を塗布しておき、その上にチップ部品(4)
を載置して(第7図)リフロー炉や高温蒸気槽のような
加熱装置で加熱してはんだ付けを行うものであった。In the conventional reflow soldering method, as shown in Figure 6, cream solder (3) is applied to the entire land (2) of the printed circuit board (1), and then the chip component (4) is applied on top of the cream solder (3).
(Fig. 7) and heated with a heating device such as a reflow oven or a high-temperature steam tank to perform soldering.
従来のリフローはんだ付け方法では、はんだ付け後、外
観は完全にはんだが付着していると思われていたもので
も少しの衝撃でチップ部品が簡単に剥離してしまうこと
が往々にしてあった。With conventional reflow soldering methods, chip components often peel off easily with the slightest impact after soldering, even if the solder appears to be completely adhered.
また、従来のリフローはんだ付け方法ではんだ付けした
プリント基板は、絶縁抵抗が悪くなることがあり、これ
が原因して電子機器の信頼性を低下させることもあフた
。Furthermore, printed circuit boards soldered using conventional reflow soldering methods sometimes have poor insulation resistance, which can sometimes reduce the reliability of electronic devices.
従来のリフローはんだ付け方法ではんだ付けしたプリン
ト基板とチップ部品の剥離面を観察してみると、はんだ
が完全に充填されていない所謂ボイドが発生しているこ
とがある。When observing the peeled surface of a printed circuit board and a chip component soldered using the conventional reflow soldering method, so-called voids, which are not completely filled with solder, may occur.
発明者らがボイドの発生について鋭意検討を加えた結果
、次のようなことが判明した。つまり、従来のリフロー
はんだ付け方法では、第7図に示すように初めからプリ
ント基板のランドとチップ部品の電極間に、粉末はんだ
と液状フラックスを混和したクリームはんだ(3)が存
在しているため、プリント基板を加熱してクリームはん
だを溶融させると、第10図に示すようにプリント基板
のランド(2)とチップ部品(4)の電極(5)で形成
されるはんだ付け部では、液状フラックス(F)が溶融
したはんだ(S)に取り囲まれる状態となり、フラック
スが抜は出ることができなくなってボイド(8)となっ
てしまうものである。また、従来のリフローはんだ付け
方法ではんだ付けしたプリント基板が絶縁抵抗を悪くさ
せていた原因もやはりプリント基板のランドとチップ部
品の電極間に初めからクリームはんだが存在しているこ
とにある。この現象は、第7図に示すようにクリームは
んだ(3)の上からチップ部品(4)を載置するため、
チップ部品で押し出されたクリームはんだがプリント基
板のランド以外の所に付着し、これが溶融してランド外
で大きなボール(Q)として残ったり、或いは小さなボ
ールに分散してランド外に付着してしまい、これらが絶
縁抵抗を低下させていたものである。As a result of intensive studies by the inventors regarding the occurrence of voids, the following findings were discovered. In other words, in the conventional reflow soldering method, as shown in Figure 7, cream solder (3), which is a mixture of powdered solder and liquid flux, is already present between the land of the printed circuit board and the electrode of the chip component. When the printed circuit board is heated to melt the cream solder, liquid flux is formed at the soldering area formed by the land (2) of the printed circuit board and the electrode (5) of the chip component (4), as shown in Figure 10. (F) is surrounded by the molten solder (S), and the flux cannot be extracted, resulting in voids (8). Furthermore, the reason why printed circuit boards soldered using conventional reflow soldering methods have poor insulation resistance is that cream solder is already present between the lands of the printed circuit board and the electrodes of the chip components. This phenomenon occurs because the chip component (4) is placed on top of the cream solder (3) as shown in Figure 7.
Cream solder extruded by chip components adheres to areas other than the lands of the printed circuit board, and this melts and remains as a large ball (Q) outside the lands, or it disperses into small balls and adheres to the outside of the lands. , these are what lowered the insulation resistance.
そこで本発明者らは、クリームはんだが初めからプリン
ト基板のランドとチップ部品の電極間に存在していなけ
ればボイドの発生や絶縁抵抗の低下を抑さえられること
に着目して本発明を完成させた。Therefore, the present inventors completed the present invention by focusing on the fact that if cream solder does not exist between the land of the printed circuit board and the electrode of the chip component from the beginning, the generation of voids and the decrease in insulation resistance can be suppressed. Ta.
本発明の特徴とするところは、クリームはんだを用いて
プリント基板とチップ部品のはんだ付けを行う方法であ
って、クリームはんだをチップ部品が載置される部分以
外のプリント基板のランドに塗布した後、該クリームは
んだがプリント基板のランドとチップ部品の電極間に挟
まらないようにしてチップ部品をプリント基板に載置し
、しかる後プリント基板を加熱してクリームはんだを溶
融させることによりプリント基板とチップ部品とを接合
するプリント基板のリフローはんだ付け方法にある。The feature of the present invention is a method of soldering a printed circuit board and chip components using cream solder, in which cream solder is applied to the land of the printed circuit board other than the part where the chip components are mounted. , the chip component is placed on the printed circuit board so that the cream solder is not caught between the lands of the printed circuit board and the electrodes of the chip component, and then the printed circuit board is heated to melt the cream solder to connect the printed circuit board. It is a reflow soldering method for printed circuit boards that connect chip components.
プリント基板のランドとチップ部品の電極間に初めから
クリームはんだが存在していないため、クリームはんだ
中のフラックスは溶融はんだに取り囲まれることがない
。Since there is no cream solder between the land of the printed circuit board and the electrode of the chip component from the beginning, the flux in the cream solder is not surrounded by molten solder.
また、ランドに塗布されたクリームはんだはチップ部品
で押し出されてランド外に付着しないことから、ランド
外でのボールの発生も起こらない。Furthermore, since the cream solder applied to the land is pushed out by the chip components and does not adhere to the outside of the land, balls do not occur outside the land.
以下図面に基づいて本発明を説明する。第1図は本発明
におけるクリームはんだの塗布状態を説明する斜流図、
第2〜δ図は本発明のはんだ付け経過を説明する断面図
、第9図は本発明におけるはんだ付け時のフラックスと
溶融はんだの流れを説明する平面図である。The present invention will be explained below based on the drawings. FIG. 1 is a diagonal flow diagram illustrating the application state of cream solder in the present invention;
2 to δ are cross-sectional views illustrating the soldering process of the present invention, and FIG. 9 is a plan view illustrating the flow of flux and molten solder during soldering in the present invention.
先ず、クリームはんだをシルクスクリーン印刷やメタル
スクリーン印刷、或いはディスペンサー等でプリント基
板(1)のランド(2)に塗布する(第2図)。ここで
のクリームはんだの塗布は、チップ部品をプリント基板
に載置した時にチップ部品の電極が載置されないところ
である。First, cream solder is applied to the lands (2) of the printed circuit board (1) using silk screen printing, metal screen printing, a dispenser, etc. (FIG. 2). The cream solder is applied here where the electrodes of the chip component are not placed when the chip component is placed on the printed circuit board.
次に、クリームはんだが塗布されたランドに所定のチッ
プ部品をチップ部品の電極(5)とプリント基板のラン
ド(2)間にクリームはんだが挟まらないようにして載
置する(第1゜3図)。この時、チップ部品が位置ずれ
しないようにチップ部品の略中央部をプリント基板に接
着剤(6)で固定しておくとよい。Next, a predetermined chip component is placed on the land coated with cream solder, making sure that the cream solder is not caught between the electrode (5) of the chip component and the land (2) of the printed circuit board. figure). At this time, it is preferable to fix the approximately central portion of the chip component to the printed circuit board with an adhesive (6) so that the chip component does not shift.
斯様にしてクリームはんだが塗布され、さらにチップ部
品が載置されたプリント基板なリフロー炉や高温蒸気槽
のような加か装置で加熱すると、初めにクリームはんだ
中のフラックス(F)が流出し、毛細管現象でプリント
基板のランド(2)とチップ部品の電極(5)間に侵入
していくく第4図)。When the cream solder is applied in this way and the printed circuit board on which the chip components are mounted is heated in a heating device such as a reflow oven or a high-temperature steam bath, the flux (F) in the cream solder first flows out. , it penetrates between the land (2) of the printed circuit board and the electrode (5) of the chip component due to capillary action (Fig. 4).
そして、さらに加熱が進むとクリームはんだ中の粉末は
んだが溶は出し、先に流出したフラックスに追従して流
れ(第9図)、ランド(2)と電極(5)間をはんだで
完全に充填するようになる。また、電極の側面にもはん
だ(5)は付着して接合部の内面、外面とも不良のない
はんだ付けがなされる(第5図)。As the heating progresses further, the powdered solder in the cream solder melts and flows following the flux that flowed out earlier (Figure 9), completely filling the space between the land (2) and the electrode (5) with solder. I come to do it. The solder (5) also adheres to the side surfaces of the electrodes, resulting in defect-free soldering on both the inner and outer surfaces of the joint (FIG. 5).
本発明によればプリント基板のランドとチップ部品の電
極問にボイドを発生させないため、接着力の強いはんだ
付け部が得られる。According to the present invention, since voids are not generated between the land of the printed circuit board and the electrode of the chip component, a soldered portion with strong adhesive strength can be obtained.
また、本発明によればプリント基板のランド以外のとこ
ろにボールが残存しないことから絶縁不良を起こさず、
信頼ある電子機器を提供できる。Further, according to the present invention, since no balls remain on the printed circuit board other than the lands, insulation failure does not occur.
We can provide reliable electronic equipment.
第1図は本発明におけるクリームはんだの塗布状態を説
明する斜視図、第2〜5図は本発明のはんだ付け経過を
説明する断面図、第6〜8図は従来のリフローはんだ付
け方法の経過を説明する断面図、第9図は本発明におけ
るはんだ付け時のフラックスと溶融はんだの流れを説明
する平面図、第10図は従来のリフローはんだ付け方法
におけるボイドやボール発生を説明する平面図である。
1・・・プリント基板 2・・・ランド3・・・クリ
ームはんだ 4・・・チップ部品5・・・電極
6・・・接着剤第1図
第6図
17図
第8図
2BQ
jI9閃
第10図Fig. 1 is a perspective view illustrating the cream solder application state in the present invention, Figs. 2 to 5 are sectional views illustrating the soldering process of the present invention, and Figs. 6 to 8 are the process of the conventional reflow soldering method. 9 is a plan view illustrating the flow of flux and molten solder during soldering in the present invention, and FIG. 10 is a plan view illustrating the occurrence of voids and balls in the conventional reflow soldering method. be. 1... Printed circuit board 2... Land 3... Cream solder 4... Chip parts 5... Electrode
6... Adhesive Figure 1 Figure 6 Figure 17 Figure 8 Figure 2BQ jI9 Flash Figure 10
Claims (1)
んだをチップ部品が搭載される部分以外のプリント基板
のランドに塗布した後、該クリームはんだがプリント基
板のランドとチップ部品の電極間に挟まらないようにし
てチップ部品をランドに搭載し、しかる後、プリント基
板を加熱してクリームはんだを溶融させることによりプ
リント基板とチップ部品とを接合するプリント基板のリ
フローはんだ付け方法。[Claims] A method of soldering a printed circuit board and chip components using cream solder, which comprises: applying the cream solder to lands of the printed circuit board other than the areas on which the chip components are mounted; The chip component is mounted on the land so that it is not caught between the land of the printed circuit board and the electrode of the chip component, and then the printed circuit board and the chip component are bonded by heating the printed circuit board and melting the cream solder. How to reflow solder a printed circuit board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10629787A JPS63273398A (en) | 1987-05-01 | 1987-05-01 | Reflow soldering method for printed substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10629787A JPS63273398A (en) | 1987-05-01 | 1987-05-01 | Reflow soldering method for printed substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63273398A true JPS63273398A (en) | 1988-11-10 |
Family
ID=14430097
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10629787A Pending JPS63273398A (en) | 1987-05-01 | 1987-05-01 | Reflow soldering method for printed substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63273398A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0424993A (en) * | 1990-05-15 | 1992-01-28 | Tamura Seisakusho Co Ltd | Soldering for preventing solder crack |
JPH08172258A (en) * | 1994-12-16 | 1996-07-02 | Sony Chem Corp | Mounting method of electronic component |
US5808358A (en) * | 1994-11-10 | 1998-09-15 | Vlt Corporation | Packaging electrical circuits |
JP2007266404A (en) * | 2006-03-29 | 2007-10-11 | Mitsubishi Materials Corp | Method for joining substrate, and element using au-sn alloy solder paste |
WO2016094915A1 (en) * | 2014-12-18 | 2016-06-23 | Zizala Lichtsysteme Gmbh | Method for void reduction in solder joints |
JP2018107400A (en) * | 2016-12-28 | 2018-07-05 | アズビル株式会社 | Component mounting device and component mounting method |
JP2019134010A (en) * | 2018-01-30 | 2019-08-08 | アズビル株式会社 | Component mounting method and printed circuit board |
JP2020129690A (en) * | 2020-05-08 | 2020-08-27 | 日亜化学工業株式会社 | Manufacturing method of light source device |
-
1987
- 1987-05-01 JP JP10629787A patent/JPS63273398A/en active Pending
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0424993A (en) * | 1990-05-15 | 1992-01-28 | Tamura Seisakusho Co Ltd | Soldering for preventing solder crack |
US5808358A (en) * | 1994-11-10 | 1998-09-15 | Vlt Corporation | Packaging electrical circuits |
JPH10303542A (en) * | 1994-11-10 | 1998-11-13 | Vlt Corp | Method for soldering electrical circuit |
US5906310A (en) * | 1994-11-10 | 1999-05-25 | Vlt Corporation | Packaging electrical circuits |
US6096981A (en) * | 1994-11-10 | 2000-08-01 | Vlt Corporation | Packaging electrical circuits |
US6119923A (en) * | 1994-11-10 | 2000-09-19 | Vlt Corporation | Packaging electrical circuits |
US6159772A (en) * | 1994-11-10 | 2000-12-12 | Vlt Corporation | Packaging electrical circuits |
JPH08172258A (en) * | 1994-12-16 | 1996-07-02 | Sony Chem Corp | Mounting method of electronic component |
JP2007266404A (en) * | 2006-03-29 | 2007-10-11 | Mitsubishi Materials Corp | Method for joining substrate, and element using au-sn alloy solder paste |
WO2016094915A1 (en) * | 2014-12-18 | 2016-06-23 | Zizala Lichtsysteme Gmbh | Method for void reduction in solder joints |
CN107113978A (en) * | 2014-12-18 | 2017-08-29 | Zkw集团有限责任公司 | Method for reducing hole in soldering point |
CN107113978B (en) * | 2014-12-18 | 2020-02-21 | Zkw集团有限责任公司 | Method for reducing voids in solder joints |
US10843284B2 (en) | 2014-12-18 | 2020-11-24 | Zkw Group Gmbh | Method for void reduction in solder joints |
JP2018107400A (en) * | 2016-12-28 | 2018-07-05 | アズビル株式会社 | Component mounting device and component mounting method |
JP2019134010A (en) * | 2018-01-30 | 2019-08-08 | アズビル株式会社 | Component mounting method and printed circuit board |
JP2020129690A (en) * | 2020-05-08 | 2020-08-27 | 日亜化学工業株式会社 | Manufacturing method of light source device |
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