JPH03196650A - Flip chip bonding - Google Patents
Flip chip bondingInfo
- Publication number
- JPH03196650A JPH03196650A JP1339293A JP33929389A JPH03196650A JP H03196650 A JPH03196650 A JP H03196650A JP 1339293 A JP1339293 A JP 1339293A JP 33929389 A JP33929389 A JP 33929389A JP H03196650 A JPH03196650 A JP H03196650A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- solder bumps
- chip
- board
- flux
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 80
- 230000004907 flux Effects 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 16
- 238000005476 soldering Methods 0.000 abstract description 5
- 230000002950 deficient Effects 0.000 abstract 4
- 239000004065 semiconductor Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3489—Composition of fluxes; Methods of application thereof; Other methods of activating the contact surfaces
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
この発明は半田バンプによるフリップチップボンディン
グ方法に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a flip chip bonding method using solder bumps.
〈従来の技術〉
第５図は従来の半田バンプによるフリップチップボンデ
ィング状態を示す概略図である。<Prior Art> FIG. 5 is a schematic diagram showing a state of flip chip bonding using conventional solder bumps.
図において、３１は半田バンプであって、この半田バン
プ３１はＩＣチップ３２上に形成されており、基板３４
上に形成された電極３５ヘフリツプチツプボンデイング
されている。このフリップチップボンディングは基板３
４上の電極３５への半田バンプ３Ｉのボンディングであ
り、以下の手順によって行われている。In the figure, 31 is a solder bump, and this solder bump 31 is formed on an IC chip 32, and is formed on a substrate 34.
Flip chip bonding is applied to the electrode 35 formed above. This flip chip bonding is done on the substrate 3.
This is the bonding of the solder bump 3I to the electrode 35 on the electrode 4, and is performed by the following procedure.
すなわち、第３図は従来のボンディングの手順を示した
ものである。That is, FIG. 3 shows the conventional bonding procedure.
ＩＣチップ２２は例えばサーマルヘッドの駆動制御用の
ＩＣであり、半田バンプ２１は直径１１０ ｐｖａ高さ
８５μ−でピッチは２１０μｍで形成されている。基板
２４上に形成された電極２５上へ半田バンプ２１を精度
よく位置合わせされた状態でＩＣチップ２２が搭載され
る。このとき、予め基板２４上には、半田フラックス２
３がスタンピングあるいはスクリーン印刷によって塗布
されており、この半田フラックス２３によりＩＣチップ
２２が基板２４上へ仮固定される。The IC chip 22 is, for example, an IC for controlling the drive of a thermal head, and the solder bumps 21 are formed with a diameter of 110 pva, a height of 85 μm, and a pitch of 210 μm. The IC chip 22 is mounted with the solder bumps 21 accurately aligned onto the electrodes 25 formed on the substrate 24. At this time, solder flux 2 is applied on the board 24 in advance.
3 is applied by stamping or screen printing, and this solder flux 23 temporarily fixes the IC chip 22 onto the substrate 24.
第４図に前記仮固定の状態を示している。符号は第３図
と同一に示しである。半田フラックス２３は予め、基板
２４上に塗布されており、半田フラックス２３は基板２
５にはよく濡れている。ＩＣチップ２２は基板２４上へ
塗布された半田フラックス２３上へ搭載されており、半
田バンプ２１へ半田フラックス２３が濡れた状態になっ
ている。第４図の状態において、はんだリフローされ、
半田バンプ２１は溶融し、基板２４上の電極２５に接着
される。FIG. 4 shows the temporarily fixed state. The symbols are the same as in FIG. 3. The solder flux 23 is applied on the board 24 in advance, and the solder flux 23 is applied onto the board 24.
It's very wet by 5. The IC chip 22 is mounted on the solder flux 23 applied to the substrate 24, and the solder bumps 21 are wetted with the solder flux 23. In the state shown in Figure 4, the solder is reflowed,
Solder bumps 21 are melted and adhered to electrodes 25 on substrate 24.
〈発明が解決しようとする課題〉
フリップチップボンディングにおいては、第５図に示す
ように、半田バンプ３１が基板２４上の電極３５へ全て
確実に接着されることが必要不可欠なことである。<Problems to be Solved by the Invention> In flip chip bonding, as shown in FIG. 5, it is essential that all solder bumps 31 be reliably bonded to the electrodes 35 on the substrate 24.
この接着は半田付けであるから、確実に接着されるため
には、充分な半田フラックスが必要となる。すなわち、
半田バンプと基板上の電極が充分半田フラックスに濡れ
ていることが必要である。Since this bonding is done by soldering, sufficient solder flux is required for reliable bonding. That is,
It is necessary that the solder bumps and the electrodes on the board are sufficiently wetted with solder flux.
しかしながら、従来例の場合、第４図の２６で示す半田
バンプのように、半田フラックスの濡れの不充分な部分
が発生しやすく、その結果、第６図の２６′で示すよう
に、半田付は不良による接続不良が起こることになる。However, in the case of the conventional example, areas where the solder flux is insufficiently wet tend to occur, such as solder bumps shown at 26 in FIG. 4, and as a result, solder bumps as shown at 26' in FIG. This will result in poor connections due to defects.
これは、ＩＣチップ２２が基板２４上へ搭載された時、
各半田パン１２１等へ半田フラックスは濡れてゆくが、
濡れ性の差により、半田フラックスの濡れの不充分な半
田バンプ２６が発生するものと考えられる。This means that when the IC chip 22 is mounted on the substrate 24,
The solder flux gets wet to each solder pan 121 etc.,
It is thought that solder bumps 26 with insufficient wettability of solder flux occur due to the difference in wettability.
本発明は上記事情に鑑みて創案されたもので、半田フラ
ックスの濡れが充分であり、フリップチップボンディン
グが確実に行える新規なフリップチップボンディング方
法を提供することを目的としている。The present invention was devised in view of the above circumstances, and an object of the present invention is to provide a novel flip chip bonding method in which solder flux is sufficiently wetted and flip chip bonding can be performed reliably.
〈課題を解決するための手段〉
本発明に係るフリップチップボンディング方法は、半田
バンプによるフリップチップボンディングにおいて、前
記半田バンプが形成されたＩＣチップが基板上へ搭載さ
れる前に、前記半田バンプ全ての被うように予めチップ
側に半田フラックスを塗布したことを特徴としている。<Means for Solving the Problems> In the flip chip bonding method according to the present invention, in flip chip bonding using solder bumps, all of the solder bumps are removed before the IC chip on which the solder bumps are formed is mounted on the substrate. It is characterized by having solder flux applied to the chip side in advance so as to cover it.
〈作用〉
半田バンプによるフリップチップボンディングにおいて
、ＩＣチップを基板上へ搭載する前に、半田フラックス
を予めチップの半田バンプ全てを被うように、塗布した
ことから、基板上へ搭載したときには、既に半田バンプ
は半田フラックスに充分濡れており、半田付は不良によ
る接着不良なしにボンディングすることができる。<Function> In flip chip bonding using solder bumps, before mounting the IC chip on the board, solder flux is applied in advance to cover all the solder bumps on the chip, so that by the time the IC chip is mounted on the board, the solder flux is already applied. The solder bumps are sufficiently wetted with solder flux, and soldering can be performed without adhesion failure due to defects.
〈実施例〉
以下、図面を参照して本発明に係る一実施例を説明する
。第１図は本発明による半田バンプによるフリップチッ
プボンディングの手順を示したものである。<Example> Hereinafter, an example according to the present invention will be described with reference to the drawings. FIG. 1 shows the procedure of flip chip bonding using solder bumps according to the present invention.
ＩＣチップ２の電極には、半田バンプ１が形成されてい
る。このＩＣチップ２は従来例で示したものと同じく、
例えばサーマルヘッドの駆動制御用ＩＣであり、半田バ
ンプ１は直径１１０μ１１高さ８５μ蒙、ピッチ２１０
μ−で形成されている。Solder bumps 1 are formed on the electrodes of the IC chip 2. This IC chip 2 is the same as that shown in the conventional example,
For example, it is a drive control IC for a thermal head, and the solder bump 1 has a diameter of 110μ, a height of 85μ, and a pitch of 210μ.
It is formed by μ-.
基板４上に形成された電極５上へ半田バンプ１を精度よ
く位置合わせして、その状態でＩＣチップ２が搭載され
る。このとき、予めＩＣチップ２には半田フラックス３
を半田バンプ１の全てを被うように塗布されており、こ
の半田フラックス３により、ＩＣチップ２が基板４上へ
仮固定される。The solder bumps 1 are precisely aligned onto the electrodes 5 formed on the substrate 4, and the IC chip 2 is mounted in this state. At this time, solder flux 3 is applied to the IC chip 2 in advance.
The solder flux 3 is applied to cover all of the solder bumps 1, and the IC chip 2 is temporarily fixed onto the substrate 4 by this solder flux 3.
第２図に仮固定の状態を示している。符号は第１図と同
一で示す。半田フラックス３はＩＣチップ２側半田バン
プ１にも基板４側電極５にもよく濡れた状態が得られる
。FIG. 2 shows the temporarily fixed state. The symbols are the same as in FIG. The solder flux 3 can be well wetted on both the solder bumps 1 on the IC chip 2 side and the electrodes 5 on the substrate 4 side.
第２図の状態にて、はんだリフローされ、半田バンプ２
１は溶融し、基板４上の電極５に接着される。第５図の
ように、半田バンプが基板上の電極へ全て確実に接着す
ることができる。In the state shown in Figure 2, the solder is reflowed and the solder bump 2
1 is melted and adhered to the electrode 5 on the substrate 4. As shown in FIG. 5, all solder bumps can be reliably bonded to the electrodes on the substrate.
なお、ＩＣチップの半田バンプへの半田フラックスの塗
布は、ボンディング直前のチップをボンディングコレッ
トに吸着した状態、あるいは吸着する直前の状態で半田
フラックス浴へ半田バンプ面をデイツプすることによっ
て簡単に行える。The solder flux can be easily applied to the solder bumps of an IC chip by dipping the solder bump surface into a solder flux bath while the chip is adsorbed to a bonding collet immediately before bonding, or just before being adsorbed.
〈発明の効果〉
本願発明に係るフリップチップボンディング方法は、半
田バンプによるフリップチップボンディングにおいて、
前記半田バンプが形成されたＩＣチップが基板上へ搭載
される前に、前記半田バンプ全での被うように予めチッ
プ側に半田フラックスを塗布したことを特徴とするもの
であるから、チツブ側の半田バンプと基板側の電極は充
分半田フラックスに濡れており、半田付は不良による接
着不良はなく、確実にボンディングすることができる。<Effects of the Invention> The flip chip bonding method according to the present invention has the following advantages in flip chip bonding using solder bumps:
Before the IC chip on which the solder bumps are formed is mounted on the board, solder flux is applied to the chip side in advance so as to cover all the solder bumps. The solder bumps and the electrodes on the board are sufficiently wetted with solder flux, and there are no adhesion failures due to soldering defects, allowing for reliable bonding.
その結果、製造歩留りが向上するため、製造コストが低
減でき、品質の向上が図れるという効果がある。As a result, the manufacturing yield is improved, so manufacturing costs can be reduced and quality can be improved.
第１図は本願発明による半田バンプによるフリップチッ
プボンディングの手順の説明図、第２図は第１図によっ
てチップを搭載した仮固定の状態の説明図、第３図、第
４図は従来例を示す説明図である。第５図は確実に半田
バンプが接着された状態の説明図、第６図は半田バンプ
の接着不良の状態の説明図である。
１ ・・・・半田バンプ
２ ・・・・ＩＣチップ
３ ・・・・半田フラックス
４ ・・・・基板
５ ・・・・電極Fig. 1 is an explanatory diagram of the flip chip bonding procedure using solder bumps according to the present invention, Fig. 2 is an explanatory diagram of the temporarily fixed state with the chip mounted according to Fig. 1, and Figs. 3 and 4 are the conventional example. FIG. FIG. 5 is an explanatory diagram of a state in which solder bumps are reliably bonded, and FIG. 6 is an explanatory diagram of a state in which solder bumps are poorly bonded. 1 ...Solder bump 2 ...IC chip 3 ...Solder flux 4 ...Substrate 5 ...Electrode
Claims (1)
おいて、前記半田バンプが形成されたＩＣチップが基板
上へ搭載される前に、前記半田バンプ全ての被うように
予めチップ側に半田フラックスを塗布したことを特徴と
するフリップチップボンディング方法。(1) In flip chip bonding using solder bumps, before the IC chip on which the solder bumps are formed is mounted on the substrate, solder flux is applied to the chip side in advance so as to cover all the solder bumps. Features flip chip bonding method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1339293A JPH03196650A (en) | 1989-12-26 | 1989-12-26 | Flip chip bonding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1339293A JPH03196650A (en) | 1989-12-26 | 1989-12-26 | Flip chip bonding |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03196650A true JPH03196650A (en) | 1991-08-28 |
Family
ID=18326085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1339293A Pending JPH03196650A (en) | 1989-12-26 | 1989-12-26 | Flip chip bonding |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03196650A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19511898A1 (en) * | 1995-03-31 | 1996-10-02 | Fraunhofer Ges Forschung | Process for surface contacting of electronic components |
| US6147870A (en) * | 1996-01-05 | 2000-11-14 | Honeywell International Inc. | Printed circuit assembly having locally enhanced wiring density |
| US6199139B1 (en) | 1998-01-27 | 2001-03-06 | International Business Machines Corporation | Refresh period control apparatus and method, and computer |
| US6246014B1 (en) | 1996-01-05 | 2001-06-12 | Honeywell International Inc. | Printed circuit assembly and method of manufacture therefor |
-
1989
- 1989-12-26 JP JP1339293A patent/JPH03196650A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19511898A1 (en) * | 1995-03-31 | 1996-10-02 | Fraunhofer Ges Forschung | Process for surface contacting of electronic components |
| DE19511898C2 (en) * | 1995-03-31 | 1999-09-23 | Fraunhofer Ges Forschung | Method for connecting contact surfaces of an electronic component and a substrate |
| US6147870A (en) * | 1996-01-05 | 2000-11-14 | Honeywell International Inc. | Printed circuit assembly having locally enhanced wiring density |
| US6246014B1 (en) | 1996-01-05 | 2001-06-12 | Honeywell International Inc. | Printed circuit assembly and method of manufacture therefor |
| US6199139B1 (en) | 1998-01-27 | 2001-03-06 | International Business Machines Corporation | Refresh period control apparatus and method, and computer |
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