JPH04340806A - Comparator circuit - Google Patents

Abstract

PURPOSE:To suppress a chattering due to the follow of an input potential IN and a threshold potential by decreasing the level of the deterioration of the threshold potential. CONSTITUTION:Transistors Q5 and Q6, resistances R4 and R5, and constant current source 12 are added to a current mirror type differential amplifier circuit constituted of transistors Q1-Q4, and an input potential is compared with the threshold potential obtained from the junction of the resistance R1 and R2. Moreover, the resistances R4 and R5 are directly connected between the correcter of the output transistor Q4 of the current mirror, and the bases of the transistors Q5 and Q6.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator circuit, and more particularly to a comparator circuit in which a reference potential has hysteresis.

0002

2. Description of the Related Art A conventional comparator circuit, particularly a comparator circuit with hysteresis, will be explained with reference to FIGS. 2 and 3.

FIG. 2 is a circuit diagram of a comparator with hysteresis showing an example of a conventional comparator. As shown in FIG. 2, the conventional comparator circuit with hysteresis includes first and second PNP transistors Q1 and Q2 as a differential input stage, and first and second NPN transistors Q3 and Q2 that constitute a current mirror circuit. Q4, constant current source I1, and power supply VCC
and the first to third resistors R1 to R connected between
3. Furthermore, two resistors R4 and R5, three NPN transistors Q8 to Q10, and constant power supplies I3 to I5
, an NPN transistor Q7 and a resistor R6 forming an output stage. In such a comparator circuit, when the input potential, which is the base potential of the transistor Q1, is higher than the threshold potential level, which is the base potential of the transistor Q2, the NPN transistor Q4 on the output side of the current mirror circuit is cut off, and the NPN transistor Q8 in the next stage is turned off. Due to the saturation state and the next stage NPN transistor Q7 being cut off, the output potential level of the output terminal OUT becomes high level. On the other hand, when the input potential of input terminal IN is lower than the threshold potential level, NP
N transistor Q4 is saturated, next stage NPN transistor Q8 is cut off, and next stage output stage NPN transistor Q7
is saturated, the output potential level of the output terminal OUT becomes low level. Further, in order to stabilize the output logic, when the output potential level is high level, the NPN transistor Q9 is cut off and the NPN transistor Q10 is saturated, so that the threshold potential level becomes low level. Also, when the output potential level is low level,
When the transistor Q9 is saturated and the transistor Q10 is cut off, the threshold potential level becomes high level.

FIG. 3 is a potential waveform diagram for explaining the difference in chattering level depending on the input conditions of the circuit shown in FIG. As shown in FIG. 3, changes in the input potential and threshold potential, and changes in the base potential of the NPN transistor Q8 based thereon are shown here. first,
At times t=t1, t3, and t5, the relationship of input potential<threshold potential is established due to a decrease in the input potential. Also, time t1<t≦t3, t3<t≦t5, t5<t≦
At t7, due to a decrease in the threshold potential, the input potential>
It represents the time from the time when the threshold potential is reached until the time when the input potential becomes less than the threshold potential due to the return of the threshold potential. Furthermore, time t=t2, t
4, t6 represents the time when the threshold potential decreases below the low level potential to a maximum.

Next, the circuit operation will be further explained. First, when the input potential, which is the base potential of the PNP transistor Q1, decreases from a high level to a low level with respect to the threshold potential, which is the base potential of the PNP transistor Q2, the base potential of the NPN transistor Q10 changes from the high level potential to the low level potential. , and the collector potential is inverted from a low level potential to a high level potential. At this time, the drop in the base potential of the transistor Q10 from the high level potential to the low level potential is transmitted to the collector of the transistor Q10 by the collector-base capacitance of the transistor Q10, so the collector potential of the transistor Q10, that is, the threshold potential is Immediately before the low level potential is inverted to the high level potential, the potential drops below the low level potential.

For example, the base potential of transistor Q10 when QN6 is saturated is VB, the collector-base capacitance of transistor Q10 is C, and the process of lowering the base potential of transistor Q10 as transistor Q9 changes from cutoff to saturation state. At time t=0, the base potential of Q10 is VB0<t<T and Q
The base potential of 10 is VB-VB. t/Tt=Q10 at T
If the base potential of is expressed as 0, then the transistor Q at time 0≦t≦T
The collector potential VC(t) of 10 is

[0007]

[0008] That is, the shorter the time (T) for the base potential of the transistor Q10 to fall, the greater the level at which the threshold potential, which is the collector potential of the transistor Q10 and the base potential of the transistor Q2, decreases to a potential below the low level potential.

As described above, in the above-described configuration of the comparator circuit, the time for the base potential of the transistor Q10 to fall, that is, the level at which the threshold potential drops to a potential below the low level potential, is approximately determined by the gm of the transistor Q9, and is determined by the gm of the transistor Q9. Almost unaffected by degradation time. Therefore, when the input potential drops below the low level potential when the input potential crosses the threshold potential due to a continuous decrease in the input potential, the threshold potential returns from the time when the input potential becomes greater than the threshold potential due to the decrease in the threshold potential. , the time T0 until the input potential becomes less than the threshold potential depends on the speed at which the input potential decreases. Therefore, the slower the input potential decreases, the longer the time T0 becomes.

0010

[Problems to be Solved by the Invention] In the conventional comparator circuit described above, when T0, which depends on the speed at which the input potential decreases, is long enough to invert the base potential of transistor Q8 to a high level, the threshold potential and the input potential are The disadvantage is that chasing occurs and the output chattering.

An object of the present invention is to provide a comparator circuit that can suppress output chattering caused by such input potential and threshold potential chasing each other.

0012

[Means for Solving the Problems] A comparator circuit of the present invention includes a first PNP transistor whose base is connected to an input terminal, and first, second, and second transistors connected in series between a first power source and a second power source. a third resistor and a base connected to the first and second resistors;
a second PNP transistor connected to the intersection of the resistors;
a first constant current source connected between the emitters of the first and second PNP transistors connected to each other and the first power source; a first constant current source connected between the collector and the base of the first PNP transistor and the emitter of the first PNP transistor; The second
a first PNP transistor connected to a power supply of the second PNP transistor, and a second NPN transistor whose base is connected to the base of the first NPN transistor and whose collector and emitter are respectively connected to the collector of the second PNP transistor and the second power supply. a third NPN transistor whose collector is connected to the intersection of the second and third resistors and whose emitter is connected to the second power supply; the base of the third NPN transistor and the a fourth resistor connected between the collector of the second NPN transistor; a fourth NPN transistor whose emitter is connected to the second power supply; a base of the fourth NPN transistor and the second NPN transistor; a fifth NPN transistor whose base is connected to the collector of the fourth NPN transistor and whose emitter is connected to the second power supply; and the fourth NPN transistor. a second constant current source connected between the collector of the fifth NPN transistor and the first power source, and a sixth resistor connected between the collector of the fifth NPN transistor and the first power source; NP of 5
It is constructed by connecting the output terminal to the collector of an N transistor.

[0013]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a comparator with hysteresis showing an embodiment of the present invention. As shown in FIG. 1, this embodiment is different from the conventional example shown in FIG.
and fifth PNP transistors Q1, Q2, Q7, first and second NPN transistors Q3, Q4,
The constant current source I1 and the resistors R1, R2, R3 and R6 are the same, and the third and fourth NPN transistors Q5 and Q6, the resistors R4 and R5, and the constant current source I2 are different. . Regarding the fifth transistor Q7,
The base connections are different. Such an element is used to prevent output chattering due to threshold potential and input potential chasing each other.

First, when the potential of the input terminal IN, which is the base potential of the transistor Q1, is higher than the threshold potential level, which is the base potential of the transistor Q2, the second
NPN transistor Q4 is cut off, the third NPN transistor Q5 is saturated, the fourth NPN transistor Q6 is saturated, and the fifth NPN transistor Q7 is cut off, so that the output potential level of the output terminal OUT is high level and threshold potential. The level will be low level. Conversely, when the potential of the input terminal IN is lower than the threshold potential level, the second NPN transistor Q4 is saturated, the third NPN transistor Q5 is cut off, the fourth NPN transistor Q6 is cut off, and the fifth NPN transistor When Q7 is saturated, the output potential level of the output terminal OUT is low level, and the threshold potential level is high level. Furthermore, when the potential of the input terminal IN crosses the threshold potential level due to a continuous decrease, the base potential of the third NPN transistor Q5 decreases as the second NPN transistor Q4 changes from the cutoff state to the saturated state. , the third NPN transistor Q5 changes from the saturated state to the cut-off state. The falling time of the base potential of the third NPN transistor Q5 is the same as that of the second NPN transistor Q5.
It is determined by the time for the collector current of the N transistor Q4 to increase from 0 to the first constant current source I1. Moreover, in the case of the differential amplifier circuit of this embodiment, the time for the collector current of transistor Q4 to increase from 0 to I1 is approximated by the time for the input potential to change from [threshold potential +25 mV] to [threshold potential -25 V]. can do. That is, the increasing time from 0 to I1 is directly influenced by the decreasing time of the potential at the input terminal IN. Therefore, the comparator circuit of this embodiment can make the level at which the threshold potential drops to a potential below the low level immediately before it is inverted from the low level to the high level depend on the falling time of the input potential.

[0016]

Effects of the Invention As explained above, the comparator circuit of the present invention has an advantage in that the input signal decreases as the input signal decreases.
The falling time of the base potential of the NPN transistor Q5, that is, the falling potential immediately before the threshold potential is inverted from the low level potential to the high level potential becomes small. Therefore, when comparing the level of decrease in the threshold potential under the same input conditions as in the prior art, the level of decrease in the threshold potential is reduced in the present invention, and chattering caused by chasing each other between the input potential and the threshold potential can be suppressed.

[Brief explanation of drawings]

FIG. 1 is a comparator circuit with hysteresis showing one embodiment of the present invention.

FIG. 2 shows a conventional example of a comparator circuit with hysteresis.

FIG. 3 is a potential waveform diagram for explaining differences in chattering levels depending on input conditions of the circuit in FIG. 2;

[Explanation of symbols]

IN Input terminals Q1, Q2 PNP transistors Q3 to Q7
NPN transistors R1 to R6 Resistors I1, I2 Constant current source VCC First power supply GND Second power supply OUT Output terminal

Claims (2)

[Claims] [Claim 1] A first P whose base is connected to an input terminal.
an NP transistor, first, second, and third resistors connected in series between a first power source and a second power source; and a second PNP transistor whose base is connected to the intersection of the first and second resistors. a first constant current source connected between the emitters of the first and second PNP transistors connected to each other and the first power supply;
a first PNP transistor whose base is connected to the collector of the PNP transistor and whose emitter is connected to the second power supply, and whose base is connected to the base of the first NPN transistor and whose collector and emitter are respectively connected to the second PN transistor.
In a comparator circuit including a collector of a P transistor and a second NPN transistor connected to the second power source, the collector is connected to the intersection of the second and third resistors, and the emitter is connected to the second power source. Third NP
a fourth resistor connected between the base of the third NPN transistor and the collector of the second NPN transistor; a fourth NPN transistor having an emitter connected to the second power supply; 4th N
a fifth resistor connected between the base of the PN transistor and the collector of the second NPN transistor; and a fifth resistor whose base is connected to the collector of the fourth NPN transistor and whose emitter is connected to the second power supply. NPN of
a second constant current source connected between the transistor, the collector of the fourth NPN transistor and the first power source, and a sixth constant current source connected between the collector of the fifth NPN transistor and the first power source. A comparator circuit having a resistor, and having an output terminal connected to the collector of the fifth NPN transistor. 2. The comparator circuit according to claim 1, wherein the first power supply uses a + side power supply, and the second power supply uses a ground.