JPH0675017U - Reference power supply circuit - Google Patents

Abstract

(57) [Summary] (Modified) [Objective] To provide a reference power supply circuit having a simple circuit configuration that is not easily affected by fluctuations in the power supply voltage and that can output a stable reference output voltage Vt. [Structure] Transistors Q1 and Q2 forming a current mirror circuit 5, a first series circuit composed of resistors R0 and R1 connected between the transistor Q1 and a common terminal 3, and between a transistor Q2 and a common terminal 3. A differential amplifier circuit 6 including a second series circuit including the formed resistors R2, R3, R4 and a transistor Q7, and a transistor Q1 formed between the transistor Q1 and the common terminal 3.
A third series circuit through the collector-emitter path of 2, and
A reference voltage output terminal 4 coupled to the transistor Q2,
The base is connected to the control output terminal a of the differential amplifier circuit 6, and the transistor Q11 is connected to the reference voltage output terminal 4 and the common terminal 3.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a reference power supply circuit, and more specifically, to a reference power supply circuit used in electric devices such as communication devices and OA and AV.

[0002]

[Prior art]

 Generally, in a power supply circuit composed of semiconductor elements used in this type of device, in recent years, a single dry cell is used for driving in order to reduce the size and weight. In such a power supply circuit, when driving the circuit of the product used, it is required that the reference power supply has a low voltage and is stable. An example of such a reference power supply circuit that has been conventionally used is shown in FIG. In FIG. 2, 1 is a power supply terminal (Vin), 2 is a power output terminal (Vout), 3 is a common terminal (GND), 4 is a reference voltage output terminal (Vt), 5 is a current mirror circuit, and 6 is It is a differential amplifier circuit. Q1 to Q4 and Q9 are PNP transistors, Q5 to Q8, Q10 and Q11 are NPN transistors, and R0 to R4 are resistors.

Between the power supply terminal 1 and the power output terminal 2, both emitters of the transistors Q1 and Q2 forming the current mirror circuit 5 are commonly connected, and between the collector of the transistor Q1 and the common terminal 3, A series circuit of resistors R0 and R1 is connected. The base of the transistor Q1 is directly connected to the connection point between the resistors R0 and R1, and the base of the transistor Q2 is directly connected to the connection point between the collector of Q1 and the resistance R0. That is, the bases of the transistors Q1 and Q2 are connected via the resistor R0.

On the other hand, a series circuit is connected between the collector of the transistor Q2 and the common terminal 3 via resistors R2, R3, R4 for level adjustment and a collector-emitter path of the transistor Q7. At the connection point between the collector of the transistor Q2 and the resistor R2, both emitters of the transistors Q3 and Q4 that form the differential amplifier circuit 6 are commonly connected, both bases thereof are short-circuited, and both collectors of the differential amplifier 61 are connected. They are connected to the collectors of the pair of NPN transistors Q5 and Q6, respectively. Both emitters of Q5 and Q6 are commonly connected and connected to the common terminal 3 through the collector-emitter path of the transistor Q8. The base of the transistor Q5 is connected to the connection point of the resistors R2 and R3, and the base of Q6 is connected to the connection point of the resistors R3 and R4.

The collector of the transistor Q5 is connected to the base of a transistor Q9 whose emitter is connected to the reference voltage output terminal 4, and its collector is commonly connected to the bases of the transistors Q7 and Q8 and a common terminal. 3 is connected to the collector of a transistor Q10 whose emitter is connected to 3. At the connection point of the collectors of the transistors Q9 and Q10, that is, at the control output terminal a, the collector is connected to the reference voltage output terminal 4 and the base of the transistor Q11 whose emitter is connected to the common terminal 3 is connected. There is. Here, the resistor R4 provided between the resistor R3 and the transistor Q7 is for biasing the transistors Q5 and Q6 forming the differential amplifier 61 to a predetermined operating point. The transistors Q9, Q10, and Q11 form an output control circuit provided to prevent fluctuations in the output voltage of the reference voltage output terminal 4.

In such a reference power supply circuit, when the power supply Vin is supplied to the power supply terminal 1, the current I1 flows through the common terminal 3 via the emitter / collector of Q1 and the resistors R0 and R1. At the same time, the current I2 also flows through the emitter and collector of the transistor Q2, but since the resistor R0 is inserted between the base and collector of the transistor Q1, the base potential of the transistor Q2 is controlled by the resistor R0 and the power supply voltage fluctuates. It is formed so as to reduce the fluctuation of the current I2 due to. When the current I2 flows, the differential amplifier circuit 6 including the transistors Q3, Q4, Q5, Q6 also operates. Along with this, the transistor Q11 which is the control element is also turned on, and the reference output voltage Vt is taken out from the reference voltage output terminal 4. The transistor 6 of the differential amplifier 61 has a configuration in which eight transistors are connected in parallel (not shown). Therefore, the emitter area of the transistor Q6 is eight times as large as that of the transistor Q5.

From such a state, when the output voltage Vt of the reference voltage output terminal 4 changes, for example, in a direction of increasing due to a load change or the like, the transistor Q11 is turned on more strongly and the collector-emitter current increases. As a result, the current supplied from the constant current circuit in the preceding stage is reduced, so that the output voltage Vt supplied from the current mirror circuit 5 is lowered. On the other hand, when the output voltage Vt changes in a decreasing direction, it operates so as to increase the output voltage Vt contrary to the above, and as a result, the output voltage Vt is kept constant.

[0008]

[Problems to be solved by the device]

 However, the conventional circuit configuration as described above has the following problems. The conventional example shown in FIG. 2 has a configuration in which a resistor R0 is inserted and connected between the base and collector of the transistor Q1 so that the variation of the current I2 due to the variation of the power supply voltage is reduced, and as a result, a differential amplifier is used. The operating point of the transistor Q11, which is the control element of the output stage for outputting the reference output voltage Vt, is designed so as not to fluctuate significantly. This type of reference power supply circuit is used for cordless telephone devices, etc. When used in other communication equipment, stricter stability may be required, which is not practically sufficient, stable circuit operation cannot be performed, and it is susceptible to fluctuations in power supply voltage. was there. An object of the present invention is to eliminate the above-mentioned conventional problems, and to provide a reference power supply circuit having a simple circuit configuration that is not easily affected by fluctuations in the power supply voltage and that can output a stable reference output voltage Vt. Especially.

[0009]

[Means for Solving the Problems]

 To achieve this object, the present invention provides PNP transistors Q1 and Q2 forming a current mirror circuit 5 having both emitters commonly connected between a power supply terminal 1 and a power output terminal 2, and a collector of the PNP transistor Q1. And a first series circuit composed of resistors R0 and R1 connected between the common terminal 3 and the base of the PNP transistor Q2, and the base of the PNP transistor Q2 is connected to the connection point between the collector of the PNP transistor Q1 and the resistor R0. A differential amplifier circuit connected to the collector and including resistors R2, R3, R4 formed between the collector and the common terminal 3 and a second series circuit via the collector-emitter path of the NPN transistor Q7. 6, the base of the PNP transistor Q1 is connected to the connection point of the resistors R0 and R1, and the base and the common terminal A third series circuit formed between the collector and emitter paths of an NPN transistor Q12, a reference voltage output terminal 4 coupled to the collector of the transistor Q2, and a control output terminal a of the differential amplifier circuit 6. The NPN transistor Q11 has a base connected to it, a collector connected to the reference voltage output terminal 4, and an emitter connected to the common terminal 3.

[0010]

【Example】

 Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit configuration diagram of a reference power supply circuit showing an embodiment of the present invention. In FIG. 1, the same symbols as those in FIG. 2 indicate the same things. Q12 is an NPN transistor. The emitters of the transistors Q1 and Q2 forming the current mirror circuit 5 are commonly connected between the power supply terminal 1 and the power output terminal 2, and a resistor R0 and a resistor R0 are connected between the collector of the transistor Q1 and the common terminal 3. A first series circuit with R1 is connected. The base of the transistor Q1 is directly connected to the connection point between the resistors R0 and R1, and a third series circuit is formed between the base of Q1 and the common terminal 3 via the collector-emitter path of the transistor Q12. ing. The base of the transistor Q2 is directly connected to the connection point between the collector of Q1 and the resistor R0. That is, the bases of the transistors Q1 and Q2 are connected through the resistor R0.

On the other hand, between the collector of the transistor Q2 and the common terminal 3, a second series circuit is connected via resistors R2, R3, R4 for level adjustment and a collector-emitter path of the transistor Q7. At the connection point between the collector of the transistor Q2 and the resistor R2, both emitters of the transistors Q3 and Q4 that constitute the differential amplifier circuit 6 are commonly connected, both bases thereof are short-circuited, and both collectors of the differential amplifier 61 are connected. The collectors of the pair of NPN transistors Q5 and Q6 to be formed are respectively connected. Both emitters of Q5 and Q6 are commonly connected and connected to the common terminal 3 through the collector-emitter path of the transistor Q8. The base of the transistor Q5 is connected to the connection point of the resistors R2 and R3, and the base of Q6 is connected to the connection point of the resistors R3 and R4.

The collector of the transistor Q5 is connected to the base of a transistor Q9 whose emitter is connected to the reference voltage output terminal 4, and the collector is commonly connected to the bases of the transistors Q7 and Q8 and its base. The common terminal 3 is connected to the collector of a transistor Q10 whose emitter is connected. At the connection point of the collectors of the transistors Q9 and Q10, that is, at the control output terminal a, the base of the transistor Q11 whose collector is connected to the reference voltage output terminal 4 and whose emitter is connected to the common terminal 3 is connected. Here, the resistor R4 provided between the resistor R3 and the transistor Q7 is for biasing the transistors Q5 and Q6 forming the differential amplifier 61 to a predetermined operating point. The transistors Q9, Q10, and Q11 form an output control circuit provided to prevent fluctuations in the output voltage of the reference voltage output terminal 4.

In such a reference power supply circuit, when the power supply Vin is supplied to the power supply terminal 1, the current I1 is supplied to the common terminal 3 in the first series circuit via the emitter / collector of Q1 and the resistors R0 and R1. Flowing. At the same time, the current I2 also flows in the second series circuit through the emitter-collector path of the transistor Q2, the resistors R2, R3, R4, and the collector-emitter path of the transistor Q7, but between the base of the transistor Q1 and the collector. Since the resistor R0 is inserted, the base potential of the transistor Q2 is controlled by the resistor R0 so as to reduce the fluctuation of the current I2 due to the fluctuation of the power supply voltage.

On the other hand, since a third series circuit is provided between the base of the transistor Q1 and the common terminal 3 via the collector-emitter path of the transistor Q12, the current flowing in the emitter-collector path of the transistor Q1 is , The resistor R1 causes a larger current I3 to flow in the loop of the transistor Q12. That is, since the current I1 << I3 is established, the current I2 flowing through the second series circuit is extremely small. Therefore, the fluctuation of the current I2 due to the fluctuation of the power supply voltage can be further reduced as compared with the conventional circuit shown in FIG. When the current I2 flows, the differential amplifier circuit 6 including the transistors Q3, Q4, Q5, Q6 also operates. Along with this, the transistor Q11 which is the control element is also turned on, and the reference output voltage Vt is taken out from the reference voltage output terminal 4.

[0015]

[Effect of device]

 As is apparent from the above description, in the present invention, the current I2 flowing through the second series circuit can be made extremely small by providing the third series circuit between the base of the transistor Q1 and the common terminal 3. Therefore, there is a practical advantage that the circuit can be taken out with a simple circuit configuration and the fluctuation of the output voltage Vt due to the fluctuation of the power supply voltage can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a reference power supply circuit showing an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing an example of a conventional reference power supply circuit.

[Explanation of symbols]

1 Power Supply Terminal (Vin) 2 Power Supply Output Terminal (Vout) 3 Common Terminal (GND) 4 Reference Voltage Output Terminal (Vt) 5 Current Mirror Circuit 6 Differential Amplifier Circuit 61 Differential Amplifier Q1, Q2, Q3, Q4, Q9 PNP transistors Q5, Q6, Q7, Q8, Q10, Q11, Q12 N
PN transistor R0 to R4 resistance

Claims (1)

[Scope of utility model registration request] 1. A power supply terminal 1 and a power output terminal 2,
A first series circuit composed of transistors Q1 and Q2 forming a current mirror circuit 5 having both emitters connected in common, and resistors R0 and R1 connected between the collector of the transistor Q1 and a common terminal 3, and the transistor. The base of Q2 is connected to the connection point between the collector of the transistor Q1 and the resistor R0, and is also connected to the collector thereof, and the resistors R2, R3, R4 formed between the collector and the common terminal 3 and the collector of the transistor Q7. A differential amplifier circuit 6 including a second series circuit via an emitter path, the base of the transistor Q1 is connected to the connection point of the resistors R0 and R1, and the base and the common terminal 3 A third series circuit formed between the collector and emitter paths of the transistor Q12 and a collector of the transistor Q2. The base is connected to the combined reference voltage output terminal 4 and the control output terminal a of the differential amplifier circuit 6, the collector is connected to the reference voltage output terminal 4, and the emitter is connected to the common terminal 3. A reference power supply circuit comprising: