JPH04339483A - Caption decoder circuit - Google Patents

Abstract

PURPOSE:To normally detect the field even if a phase difference of a horizontal synchronizing signal to a vertical synchronizing signal of a television signal is arbitrary. CONSTITUTION:By a load signal (g), data is set to a programmable counter 6, and from a detection window controller 7, an output signal (J) is outputted within a certain range. By an output signal (k) of AND of the output signal (j) of the detection window controller 7 and a horizontal synchronizing signal (c), an RSflip-flop circuit 9 is set, and by a signal (u) corresponding to a rise edge of a vertical synchronizing signal (b), this circuit 9 is reset by which a field permission output signal (m) is generated. In the case a phase difference of the vertical synchronizing signal (b) and the horizontal synchronizing signal (c) is different, a phase of the output signal (j) of the detection window controller 7 is moved, and allowed to correspond to the phase difference of both the signals (b), (c) by varying the data set to the programmable counter 6.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention uses a device that separates a vertical synchronization signal and a horizontal synchronization signal from a video signal to selectively capture caption data superimposed within a horizontal synchronization signal section of a video signal. This relates to a caption decoder circuit.

0002

2. Description of the Related Art In recent years, it has become necessary to add a telecaption function to television receivers in consideration of the hearing-impaired. Therefore, one-chip microcomputers with a built-in caption decoder have come into use.

[0003] Caption data is superimposed on a video signal like the character data of conventional teletext broadcasting, and is
After decoding, it is displayed as a character.

An NTSC type teletext decoder will be described below as a conventional technology for caption decoders.

FIG. 7 shows an NTSC video signal. In FIG. 7, a is a video signal, b is an example of a vertical synchronization signal separated from video signal a, c is an example of a horizontal synchronization signal separated from the video signal, and t1 is the 10th horizontal synchronization signal section (hereinafter simply referred to as 10 lines). ) to the 21st horizontal synchronization signal section (
The character signal superimposition section up to (hereinafter simply referred to as 21 lines),
t2 indicates a character signal superimposition interval from the 273rd horizontal synchronizing signal interval (hereinafter referred to as the 273rd line) to the 284th horizontal synchronizing signal interval (hereinafter referred to as the 284th line).

FIG. 1 is a diagram showing an example of the configuration of a teletext decoder. In FIG. 1, 1 is a device that separates a vertical synchronization signal and a horizontal synchronization signal from a video signal (hereinafter referred to as an HV separator), and 2 is a teletext decoder, which separates the vertical synchronization signal and horizontal synchronization signal from the HV separator 1. This signal is used to select character data. 3 is an operational amplifier, a is a video signal, b is a vertical synchronization signal, c is a horizontal synchronization signal, d is caption data, and e is a reference voltage.

In the NTSC system text broadcasting, the 10th line to the 21st line and the 273rd line to the 284th line within the vertical retrace period of the video signal a are character signal superimposition sections.
The character data in this section was selectively extracted and displayed as an image. Among them, it is necessary to distinguish between the data superimposed on the 10th line to the 21st line and the data superimposed on the 273rd line to the 284th line, and to selectively extract the data. The generated vertical synchronization signal b and horizontal synchronization signal c are used to detect the phase difference between them (hereinafter, such detection will be referred to as field detection). One of these fields
Odd field from line to 262.5 line,
The line from line 262.5 to line 525 is called an even field.

The operation of the conventional field detector will now be explained. FIG. 5 shows the configuration of a conventional field detector for detecting odd fields. FIG. 6 is a timing diagram of the operation of this conventional example. However, it is assumed that the odd field has the phase relationship between the vertical synchronizing signal and the horizontal synchronizing signal shown in FIG.

In FIG. 5, b is a vertical synchronization signal, 10 is an edge detector for detecting the rising edge of the vertical synchronization signal b, p is an output signal of the edge detector 10, c is a horizontal synchronization signal, and 11 is an output signal p. and a horizontal synchronizing signal c as inputs, r is the output signal of the AND circuit 11, n is the clock signal, 12 operates with the clock signal n,
Counter reset by output signal p, q is counter 1
2 is an output signal, 13 is an RS-flip-flop circuit (hereinafter simply referred to as RS-FF) which is set by an output signal r and reset by an output signal q, and s is a field enable output signal.

In the field detector having the configuration shown in FIG. 5, when the rising edge of the vertical synchronizing signal b overlaps the pulse of the horizontal synchronizing signal c to detect an odd field, the field enable output signal s is set to a logical value of '1'. ' to. Also, since the output signal p, which means the rising edge of the vertical synchronization signal b, resets the counter 12, the output signal q is obtained by calculating the period of the clock signal n and the count number of the counter 12, and the field permission output signal s Set to logical value '0'.

With this configuration, the field enable output signal s is set to the logical value '0' at every rising edge of the vertical synchronization signal b.
', field enable output signal s in odd field
is set to logical value '1'.

0012

[Problems to be Solved by the Invention] However, the vertical synchronizing signal b and horizontal synchronizing signal c shown in FIG. Since the phase difference between the synchronization signal and the horizontal synchronization signal is about half the period of the horizontal synchronization signal,
Unless the configuration of the field detector is changed every time the timing of the HV separator changes, errors in field detection have occurred.

SUMMARY OF THE INVENTION The present invention has been made to solve these problems, and an object of the present invention is to construct a caption decoder circuit that can normally detect a field even if the phase difference between a horizontal synchronizing signal and a vertical synchronizing signal is arbitrary.

[0014]

[Means for Solving the Problem] In order to solve this problem, the present invention provides a method for detecting the phase difference between a vertical synchronization signal and a horizontal synchronization signal within one section (hereinafter referred to as a detection window) of a vertical synchronization signal. To realize a caption decoder circuit that normally detects a field even if the phase difference between a horizontal synchronizing signal and a vertical synchronizing signal is arbitrary by determining whether there is a horizontal synchronizing signal pulse in the field and arbitrarily setting a detection window. It made it possible.

[0015]

[Operation] With such a configuration, it is possible to realize an excellent caption decoder circuit that can normally detect fields regardless of differences in HV separators.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the basic configuration diagram shown in FIG.

FIG. 2 shows the structure of one embodiment of a field detector included in the caption decoder circuit of the present invention.

FIG. 3 is a timing diagram of the vertical synchronizing signal b and horizontal synchronizing signal c inputted from the HV separator to the field detector included in the caption decoder circuit, and each signal shown in FIG. 2.

FIG. 4 is a timing diagram of each signal shown in FIG. 2 when the vertical synchronization signal b and the horizontal synchronization signal c shown in FIG. 3 have different phase differences.

The configuration of FIG. 1 is as described above. Figure 2
4, an edge detector 4 detects the rising edge of the vertical synchronizing signal b and generates an output signal u. 5
is an inverter that inverts the vertical synchronizing signal b to produce a signal f. 6 is a programmable counter which operates with a 500 kHz clock signal i and takes in data h with a load signal g. Then, it is reset by the output signal f of the inverter 5. 7 is a detection window controller, the output signal of the programmable counter 6 is supplied to its input terminal, and it generates an output signal j. 8 is an AND circuit which generates an output signal k of the logical product of the horizontal synchronizing signal c and the output signal j of the detection window controller 7. Reference numeral 9 denotes an RS-FF which is set by the output signal k of the AND circuit 8 and reset by the output signal u of the edge detector 4 to generate a field permission output signal m.

The output signal u generated by the edge detector 4 when it detects the rising edge of the vertical synchronizing signal b is equivalent to the output signal p of the conventional example shown in FIG. Since the programmable counter 6 is reset by the signal f obtained by inverting the vertical synchronizing signal b by the inverter 5, its operation period is only the pulse period t3 of the vertical synchronizing signal b.

FIG. 3 shows operating waveforms when the vertical synchronizing signal b and horizontal synchronizing signal c having the phase relationship shown in FIG. 6 are input to the field detector 2. Note that t3 is a pulse section of the vertical synchronization signal b.

By setting certain data h in the programmable counter 6 using the load signal g, the output signal j of the detection window controller 7 is output within a certain range. The AND circuit 8 detects whether or not there is a horizontal synchronizing signal c in the section of the output signal j of the detection window controller 7, sets the RS-FF 9 with the output signal k, and sets the RS-FF 9 with the output signal u of the edge detector 9. The reset generates a field enable output signal m.

If the phase difference between the vertical synchronizing signal b and the horizontal synchronizing signal c is different from the conventional one, as shown in FIG.
By shifting the phase of the output signal j of the detection window controller 7, the field permission output signal m is generated normally. To shift the phase of the output signal j of the detection window controller 7, for example, change the data set in the programmable counter 6 and change the vertical synchronization signal b and the horizontal synchronization signal c.
What is necessary is to correspond to an arbitrary phase difference.

[0025]

As described above, according to the present invention, it is possible to construct an excellent caption decoder circuit that can normally perform field detection even if the phase difference between the vertical synchronization signal and the horizontal synchronization signal is arbitrary.

[Brief explanation of drawings]

[Fig. 1] A diagram showing the basic configuration of a caption decoder circuit of the present invention.

[Fig. 2] A configuration diagram of an embodiment of a field detector included in the caption decoder circuit of the present invention.

[Figure 3] Vertical synchronization signal b and horizontal synchronization signal c input from the HV separator to the field detector in the caption decoder circuit, and a timing diagram of each signal in the circuit of Figure 2.

[Fig. 4] Timing diagram of each signal when the vertical synchronization signal b and horizontal synchronization signal c shown in Fig. 3 have different phase differences.

[Figure 5] Configuration diagram of a conventional example of a field detector that detects odd fields

[Figure 6] Timing diagram of the operation of the field detector in Figure 5.

[Figure 7] Timing diagram of NTSC video signal

[Explanation of symbols]

1 HV separator 2 Teletext decoder 3 Operational amplifier 4 Edge detector 5 Inverter 6 Programmable counter 7 Detection window controller 8 AND circuit 9 RS-Flip-flop circuit

Claims (1)

[Claims] 1. A caption decoder circuit having a field detection function for determining two types of timing using interlaced scanning even if the phase difference between a horizontal synchronizing signal and a vertical synchronizing signal in an NTSC system or the like is arbitrary.