KR0139175B1 - Sync separation and field detection circuit and method in hdtv - Google Patents

Abstract

The present invention is to separate the horizontal sync signal and the vertical sync signal from the 1050- or 1250-line interlaced composite sync signal and to detect a signal for fast and accurate field separation. It relates to a circuit and a method thereof. The present invention includes first and second amplifiers for amplifying only the negative signal and the positive signal of the composite synchronization signal, respectively, to separate the vertical synchronization signal and the horizontal synchronization signal, and to reset the horizontal synchronization signal according to the even field start signal. The field detection circuit is configured to include a counter for counting signals and a logic element for disabling the counter and outputting a signal for distinguishing fields when a preset value is input from the counter.

Description

Synchronization Signal Separation and Field Detection Circuit for High Definition Television

1 is a general NTSC composite synchronous signal waveform diagram.

2 is a composite synchronous signal waveform diagram for a 1050-line interlaced scanning high definition television.

3 is a composite synchronous signal waveform diagram for a 1250-line interlaced scanning high definition television.

4 is a synchronous signal separation circuit diagram for a high definition television according to the present invention;

5 is an application example of an inverter to an amplifier for explaining the operation of the first and second amplifiers in FIG. 4, (a) a circuit diagram, and (b) a transfer characteristic graph and an input / output signal waveform diagram.

6 is a field detection circuit diagram for a high definition television according to the present invention;

7 is a waveform diagram of each part of FIGS. 4 and 6;

* Description of the symbols for the main parts of the drawings *

10: first amplifier 20: second amplifier

30: Counter INVI-INV6: Inverter

NAND1-NAND3: NAND Gate

The present invention separates the horizontal and vertical sync signals from a composite sync signal for high-definition television (HD-TV) with a 1050-line 2: 1 interlace scan and a 1250-line 2: 1 interlace scan. The present invention relates to a synchronization signal separation and field detection circuit for a high-definition television that detects a signal for classification and a method thereof.

In general, 525-line 2: 1 interlaced (NTSC) television signals or 625-line 2: 1 interlaced (SECAM, PAL) television signals have an odd number of lines per frame. Each cycle produces a composite sync signal.

At this time, both the horizontal synchronizing signal and the vertical synchronizing signal are binary (0,1) synchronizing signals. The horizontal sync signal and the vertical sync signal are separated from the complex sync signal as follows.

When the composite synchronization signal is applied to the differential circuit and passes through the differential circuit, the horizontal synchronization signal can be separated, and when the composite synchronization signal passes through the integration circuit, the vertical synchronization signal can be separated.

However, the horizontal synchronizing signal disappears in the portion where the horizontal synchronizing signal overlaps with the vertical synchronizing signal. As shown in FIG. 1, an equalization pulse is applied to the horizontal synchronizing signal during each 3H period before and after the vertical synchronizing signal and the vertical synchronizing signal. Do not lose.

Therefore, the horizontal synchronizing signal separated from the composite synchronizing signal includes not only a pulse of a horizontal (H) period but also a pulse of a horizontal half (H / 2) period by a moving picture pulse.

The television receiver is configured with a phase locked loop (PLL) circuit which inputs a separate horizontal sync signal. However, there is a problem that the phase locked loop circuit becomes unstable in a signal section in which an equalization pulse is present.

In addition, in an apparatus for processing an image in a frame unit divided into odd and even fields, such as a picture-in-picture (PIP) circuit, a circuit for detecting a signal for dividing a field is required. Form.

However, the concept of high-definition television has emerged. In the United States and Europe, in selecting a signal format of the high-definition television, the 1050-line (525 × 2) interlaced scanning method is considered in consideration of compatibility with current signal sources such as NTSC and PAL. (See FIG. 2), the 1250-line (625x2) interlaced scanning method (refer to FIG. 3) is a trend.

The synchronization signal of the high definition television signal has several characteristics as follows.

(1) A tri-level (-, 0, +) sync signal is used.

(2) the width of the vertical synchronization signal is small

(3) Since the number of lines constituting one frame is even, the number of lines allocated to the odd field and the even field is different.

1050 line format (524.5 lines, 525.5 lines)

1250 line format (624.5 lines, 625.5 lines)

(4) Although the number of lines varies depending on the field, the vertical synchronization signal is contained in a period of 525 lines or 625 lines.

Therefore, as described above, a problem arises in that a new circuit different from the conventional one is required to separate the horizontal sync signal and the vertical sync signal from the composite sync signal for high-definition television having a different characteristic from the general television signal, and to detect the field.

SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to isolate a synchronization signal for a high definition television, which separates a horizontal synchronization signal and a vertical synchronization signal using a level difference in a composite synchronization signal for a high definition television. To provide a circuit.

Another object of the present invention is to provide a field detection circuit and a method for a high-definition television which can obtain a signal for quickly and accurately classifying a field using the detected even field start signal and the horizontal synchronizing signal.

An object of the present invention as described above comprises: first amplifying means for inverting, amplifying and filtering only a negative signal having a predetermined level or less in a composite synchronization signal; First inverting means for inverting the output signal of the first amplifying means and outputting the vertical synchronizing signal in an inverted state; Second amplifying means for inverting and amplifying only a positive signal of a predetermined level or more among the composite synchronization signals; Second inverting means for inverting an output signal of the second amplifying means and outputting a signal including a horizontal synchronizing signal and an even field start signal; This is achieved by a logic element that negatively multiplies the vertical synchronizing signal output from the first inverting means and the output signal of the second inverting means and outputs the horizontal synchronizing signal in an inverted state.

Another object of the present invention is to provide a first logic element which outputs an even field start signal by a negative AND of a signal including a horizontal sync signal, an even field start signal, and a vertical sync signal; A counter which is reset according to an even field start signal output from the first logical element and counts a horizontal synchronization signal; When a preset value is input by negating the output signals of the counter and inputting a preset value, this is achieved by a second logic element that disables the counter and outputs a signal for classifying the fields.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 through 7.

4 is a synchronous signal separation circuit diagram for a high definition television according to the present invention.

As shown in the drawing, the vertical synchronizing signal separation circuit inverts, amplifies, filters, and outputs only the negative signal having a predetermined level or less among the composite synchronizing signals input through the input terminal consisting of the capacitor C1 and the resistor R1. And an inverter INV3 for inverting the output signal of the first amplifier 10 and outputting the inverted vertical synchronizing signal A. FIG.

Here, the first amplifier 10 is connected to the condenser C2 connected to the input terminal, the inverter INV1 acting as an amplifier at the rear end of the condenser C2, and feedback from the input terminal and the output terminal of the inverter INV1 to increase the amplification factor. The resistors R2 and R3, which are set between the input terminal of the inverter INV1 and the DC power supply Vcc and determine the operating point, are fed back to the inverter INV1 and low-pass filtering the signal. It consists of the capacitor | condenser C3.

In addition, the horizontal synchronization signal separation circuit outputs the second amplifier 20 and the second amplifier 20 which inverts and outputs only positive (+) polar signals of a predetermined level or more among the composite synchronization signals inputted through the input terminal. A second inverter INV4 for inverting the signal and outputting a signal B including a horizontal sync signal and an even field start signal, and an inverted vertical sync signal A and a second inverter output from the first inverter INV3 The NAND gate NAND1 outputs an inverted horizontal synchronizing signal C by performing an AND logic on the output signal of INV4.

Here, the second amplifier 20 is connected to the condenser C4 connected to the input terminal, the inverter INV2 acting as an amplifier at the rear end of the condenser C4, and feedback from the input terminal and the output terminal of the inverter INV2, thereby increasing the amplification factor. A resistor R5 and R6 to be set and a resistor R7 connected between the input terminal of the inverter INV2 and ground to determine an operating point.

The operation of the vertical / horizontal sync signal separation circuit configured as described above will be described based on the waveform diagram of FIG.

When a composite synchronizing signal for a high definition television as shown in FIG. 7A is input, the signal is inputted through the capacitor C1 and the resistor R1 for termination and the first amplifier 10 and the first amplifier 10. It is input to the 2 amplification unit 20.

5 shows an example of the use of the amplification ratio of the inverter to explain the operation of the first and second amplification units 10 and 20. (A) is a circuit diagram, and (B) is a transfer characteristic graph and input / output. Signal waveform diagram.

As shown in (a) of FIG. 5, a circuit is formed by connecting _a capacitor (C _a ) and a resistor (R _a ) (R _b ) to an inverter (INC), and a transfer characteristic graph as shown in ( _b ) of _FIG . The operating point is at point A, and the amplification factor Av is operated as an amplifier with Av ≒ -R _b / R _a .

At this time, if the resistor R _c of proper value is connected between the input terminal of the inverter INV and the ground, the operating point moves to the point B, and the resistor R _c is connected between the input terminal of the inverter INV and the DC power supply. The operating point moves to the C point.

Therefore, if the resistor R _C is connected to the ground in the state where the tri-level synchronizing signal is input to the circuit of FIG. 5, only a signal (+ signal of the tri-synchronizing signal) of a predetermined level or more is amplified and output, and the resistor R _c When connected to a power supply, only a signal of a predetermined level or less (a -signal of the tri-synchronization signal) is amplified and output.

Referring to the description of FIG. 5 as described above, the operation of the second amplifier 20 is described. Since the resistor R7 is connected to the ground, the composite synchronization signal input through the capacitor C4 is converted to the inverter INV2. By passing through, only the positive signal of the tri-level synchronizing signal is separated and output.

At this time, since the inverted amplification at the amplification ratio of -R6 / R5, if the signal output from the second amplifier 20 is inverted through the second inverter INV4, the horizontal synchronization signal is even and as shown in (b) of FIG. The signal B including the field start signal is output.

Meanwhile, referring to the description of FIG. 5 as described above, the operation of the first amplifier 10 will be described. Since the resistor R4 is connected to the DC power supply Vcc, the composite synchronization input through the capacitor C2 is performed. The signal passes through the inverter INV1, and only the negative signal of the tri-level synchronizing signal is separated and output.

In this case, since the negative signal is inverted and amplified at an amplification rate of -R 3 / R 2 and low-pass filtered by the capacitor C3, the first amplifier 10 outputs a signal as shown in (C) of FIG. 7. do.

The first inverter INV3, which receives the output signal of the first amplifier 10, presets a threshold voltage (parts indicated by dotted lines in FIG. 7C) and is input from the first amplifier 10. If the signal is less than the predetermined threshold voltage outputs a high level signal, and if the predetermined threshold voltage or more outputs a low level signal. Therefore, since the signal (C) of FIG. 7 passes through the first inverter INV3, the vertical synchronization signal A of the square wave is output as an inverted signal as shown in (D) of FIG. 7 to the NAND gate NAND1. Is entered.

The inverted vertical synchronizing signal A output from the first inverter INV3, the horizontal synchronizing signal output from the second inverter INV4, and the signal B including the even field start signal are input to the NAND gate NAND1. Here, the inverted horizontal synchronizing signal C from which the even field start signal is removed is output from the NAND gate NAND1 by being negatively multiplied as shown in FIG.

6 is a field detection circuit diagram for a high-definition television of the present invention, and is configured to be suitable for a 1050-line 2: 1 interlaced scanning method.

In this circuit, the input signals use a signal B including the horizontal sync signal and the even field start signal detected in FIG. 4, an inverted vertical sync signal A, and an inverted horizontal sync signal C. .

In FIG. 6, the field detection circuit NAND2 outputs an even field start signal by performing an NOR operation on a time signal B including a horizontal sync signal and an even field start signal and a vertical sync signal input through an inverter INV5. ) And a counter 30 which is reset according to the even field start signal output from the NAND gate NAND2 and counts the horizontal synchronization signal inputted through the inverter INV6, and output signals of the counter 30 are negative logic. When a preset value is multiplied and input, the NAND gate NAND3 outputs a signal for disabling the counter 30 and dividing a field.

In the field detection circuit configured as described above, the NAND gate NAND2 is inverted vertical sync inverted through the inverter INV5 and the signal B including the horizontal sync signal and the even field start signal, as shown in FIG. 7B. A signal A (refer to (d) in FIG. 7) is input and an even field start signal as shown in (f) of FIG. 7 is output as a reset signal of the counter 30.

In addition, the inverted horizontal synchronization C as shown in FIG. 7E is input to the clock terminal CLK of the counter 30 in an inverted state by the inverter INV6.

The counter 30 is a 1024-degree counter, which is reset at the start of the even field to count the horizontal synchronization signal.

The NAND gate NAND3 configured to output “0” is connected to the output terminal of the counter 30 when 526 ₍₁₀₎ = 1000001110 ₍₂₎ is input. As shown in FIG. When the output value of the?) Is 526 ₍₁₀₎ , "0" is output from the NAND gate NAND3 as shown in (a) of FIG.

Since this signal is input to the enable terminal EN of the counter 30, the operation of the counter 30 is stopped, and is reset again by the even field start signal output from the NAND gate NAND2 to count the horizontal synchronization signal. do.

Then, a field detection signal as shown in (a) of FIG. 7 is output from the NAND gate NAND3 so that the field can be distinguished at the point where the field starts.

In FIG. 6, the NAND gate NAND3 is configured to output “0” when 526 ₍₁₀₎ is input. However, when the NAND gate NAND3 is configured to output “0” when 626 ₍₁₀₎ is input, 1250. It can also be used as a field detection circuit for high-definition television of the line interlaced scanning method.

As described above, the present invention separates the horizontal synchronizing signal and the vertical synchronizing signal by using the level difference in the composite synchronizing signal for high-definition television, so that the circuit using the synchronizing signal, for example, the phase synchronizing loop circuit, can be stably operated. Can be.

In addition, it is possible to obtain a fast and accurate field detection signal using the detected even field start signal and the horizontal synchronization signal.

Claims (8)

In a high-definition television that receives a composite video signal transmitted from a broadcasting station, separates a composite synchronization signal, and divides the video frame into odd fields and even fields, and displays them by interlaced scanning. First amplifying means for inverting, amplifying, and filtering only negative signals having a predetermined level or less among the input composite synchronization signals; First inverting means for inverting the output signal of the first amplifying means and outputting the vertical synchronizing signal in an inverted state; Second amplifying means for inverting and outputting only the positive signal of a predetermined level or more among the input composite synchronization signals; Second inverting means for inverting an output signal of the second amplifying means and outputting a signal including a horizontal synchronizing signal and an even field start signal; And a logic element for negatively multiplying the vertical synchronizing signal output from the first inverting means and the output signal of the second inverting means and outputting the horizontal synchronizing signal in an inverted state. In a high-definition television that receives a composite video signal transmitted from a broadcasting station, separates a horizontal sync signal from a vertical sync signal, divides the video frame into odd fields and even fields, and displays the interlaced scan method. A first logical element configured to negatively multiply the signal including the signal and the vertical synchronization signal to output an even field start signal; A counter which is reset according to an even field start signal output from the first logic element and counts a horizontal synchronization signal; And And a second logic element which disables the counter and outputs a signal for classifying a field when a predetermined value is input by negatively multiplying the output signals of the counter. The method of claim 2, And the image frame is 1050 lines. The method of claim 3, And a preset value of said second logic element is 526 ₍₁₀₎ . The method of claim 2, And the image frame is 1250 lines. The method of claim 5, And a preset value of said second logic element is 626 ₍₁₀₎ . In the method for separating the field detection signal from the composite synchronization signal, Separating the inverted vertical sync signal from the negative signal equal to or less than a predetermined level of the complex sync signal; Separating a signal including a horizontal sync signal and an even field start signal from a positive signal of a predetermined level or more of the complex sync signal; Generating an inverted horizontal synchronization signal by performing an AND-OR on the signal including the vertical synchronization signal and the horizontal synchronization signal and the even field start signal; Separating the even field start signal by performing a negative AND operation on the separated vertical sync signal and the horizontal sync signal and the signal including the even field start signal; Counting a horizontal synchronization signal using the even field start signal as a reset signal; And Generating a signal for discriminating a field when a predetermined value is input by negatively multiplying said coefficient value. The method of claim 1, wherein the first inverting means outputs a high level signal when the output signal of the first amplifying means is less than or equal to a preset threshold voltage, and outputs a low level signal when it is greater than or equal to a predetermined threshold voltage. Sync signal separation circuit for high definition television.