JPH0432924A - Maximum value detector and minimum value detector - Google Patents

Abstract

PURPOSE:To search for a maximum value with a constant machine cycle by searching for discordance information from the MSB to the LSB, storing a numeral which is 1 at the closest discordant bit position to the MSB, and deleting a numeral which is 0 from the storage at each discordant bit position in order thereafter. CONSTITUTION:A bit searching circuit 13 starts the search at the MSB of a 1st decision register 11 and stores plural numerals which are 1 at the bit position where discordant information is stored for the 1st time in storage means X15, Y16, and Z17, and W18. At every following bit position where 2nd or succeeding discordant information is stored, a corresponding bit position of a 2nd decision register 12 is searched for to carry on operation for deleting numerals which are 0 at the bit position from the storage when presence information is found or regards the remaining numeral left in the storage by performing retrieval up to the LSB as a maximum value when no presence information is found. Consequently, maximum value detection is speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a maximum value/minimum value device that detects maximum and minimum values from a plurality of values at high speed.

Conventional technology Conventionally, when searching for the maximum or minimum value from among multiple values, two values are selected, their magnitude relationship is clarified, and if the value is the maximum value, the larger one is selected, and if the value is the minimum value, the smaller value is selected. , and repeat this one after another to finally obtain a large value,
Select small values. A method of subtracting using an arithmetic logic unit (hereinafter referred to as ALU) has been considered as a method of clarifying the magnitude relationship between two values, but this method requires comparison cycles equal to the number of times the magnitude comparison is performed, and it is difficult to do so using software. A process of sequential comparison is required.

Even if ALUs are provided for the number of times of size comparison, the circuit scale will increase and the maximum or minimum value cannot be determined unless the comparison is repeated several times. The number of cycles to find the maximum and minimum values also increased proportionally.

Problems to be Solved by the Invention The present invention solves the above conventional problems, and provides a maximum value/minimum value device that can find the maximum value or minimum value in a constant machine cycle even if the number of data changes. The purpose is to

Means for Solving the Problems In order to achieve the above objects, the present invention provides the following: (1) A plurality of numerical values represented by parallel data in which each bit is composed of 0 or 1 are connected to each numerical input terminal as parallel data. A device for detecting the maximum value of the plurality of numerical values inputted at the same time, comprising a determination register having the number of digits of the numerical value and a storage means, for detecting a mismatch by inputting the value of the same significant bit from the plurality of numerical values. and a bit search circuit for searching the content of the judgment register and controlling the storage, the bit search circuit storing the MSB of the judgment register. , and store the plurality of numerical values having 1 in the bit position where the first mismatch information is stored in the determination register in the storage means, and thereafter, for each bit position where the second and subsequent mismatch information is stored. , continues the operation of deleting the numerical value having 0 at that bit position from the memory, searches up to the LSB, and uses the numerical value remaining in the memory as the maximum value, and (2) each bit is 0. A determination register having the number of digits of the number of digits of the number of digits of the number of digits of the number of digits of the number of digits of the number of digits of the number of digits of the number of digits of the number of digits of the number of digits of the number of digits of the number of digits of the number of digits of the number of digits of the number of digits of the number of digits of the number of digits of the number of digits of the number detected is detected. a discrepancy determining unit, comprising a storage unit, inputting values of the same bits from the plurality of numerical values, detecting discrepancies, and storing discrepancy information in corresponding bit positions of the determination register; and contents of the determination register. A bit search circuit is provided to search for and control the storage, and the bit search circuit searches from the MSB of the determination register, and the plurality of bits having 0 in the bit position where mismatch information is stored first in the determination register. The numerical value of 1 is stored in the storage means, and thereafter, for each bit position where the second and subsequent mismatch information is stored, the operation of deleting the numerical value having 1 at that bit position is continued from the memory, and searching up to the LSB is performed. A minimum value detection device that takes the memorized numerical value as the minimum value.

Operation In the above configuration, the mismatch determining means detects the bit position related to the magnitude relationship and stores it in the determination register (if all are 0 or 1, it is a bit position where no magnitude relationship occurs). The bit search circuit selects the determination register from the MSB
MS
A numerical value having 1 or 0 (possible maximum value or minimum value) at the mismatching bit position closest to B is stored in the storage means, and from then on, 0 is sequentially stored at each mismatching bit position.
Alternatively, numerical values having 1 (numerical values that have no possibility of being the maximum value or the minimum value) are deleted from the memory.

EXAMPLE Hereinafter, a maximum value detection device according to an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a maximum value detection device according to an embodiment of the present invention. In this embodiment, means for setting a flag is used as the storage means. Further, although the auxiliary second determination register is used to search for mismatch information, this is not contrary to the means of the present invention. Further, although a case will be described in which the number of numerical values to be input is four, the same configuration can be made even if other numbers are input.

Data AI+data B2+data C3 and data D4 are input data and are composed of 4 bits.

Data A is A blllt + A b in order from MSB
It has bit data of o3+A b p 21 A b p + + (hereinafter referred to as A<, A3, A2.AI), and data B2 is B4, B3.

B2 + B+ 1 data C3 is C4, C3, C2,
C data D4 is D4, D3, D2 . Consists of D+ data. Data A+, data B2. Each bit of MSH of data C3 and data D4 is input to pit comparison/judgment circuit 5. The pit comparison/judgment circuit 5 consists of an exclusive NOR circuit 9 and an AND-OR circuit 10, and the pit comparison/judgment circuit 5 consists of an exclusive NOR circuit 9 and an AND-OR circuit 10. B4. C
4. Exclusive NOR when D4 is all “1” or “0”
The bit position (
Hereinafter, ``1'' is set in bp)4. Also, data A<
,B4.

AND-OR when two or more of C4 and D4 are “1”
The circuit 10 sets bp4 of the determination register B12 to "1". bp3°bp2 of each data. bpl is similarly determined by the bit comparison/judgment circuit 6.7°8 in the determination register A11. As an example where a value is set to B12, data A1 is (1010) and data B2 is (1001).
), data C3 is (101,0), data D4 is (10
Considering the case of 11), the bit comparison judgment circuits 5, 6,
According to 7.8, judgment register A 11 has (1100):
(1011) is set in the judgment register B1°.

The bit search circuit 13 first examines the contents of the determination register A1.

The bit search circuit 13 examines the values of the bits configuring the register in order from the MSB or LSB direction, and in the case of 1 bit search "1", outputs the bit position information where "1" is found first, and performs the bit search "0". ”, it has the function of outputting the focus position information with the first “0”. Bit search of judgment register All is MS
The process starts from B and detects the position of the first "0". In the case of the above example, since the value of the determination register A11 is (1100), bp2 is detected. At this time, judgment register B
The value of 1° is (1011) and bp2 is "1".

This indicates that the maximum value can be determined from data AI, B2°C3, and D4 by checking the bp2 value of each data from the value of the judgment register A++, but the bp2 of each data is " There are multiple cases where the value is 1'', indicating that it is not possible to make a determination just by examining bp2. Each data AI, B2+ C3+ C4
is the maximum value, but if the LSB is not checked further, the flag X indicating that it is the maximum value data candidate.
+s, Y 16+ Z 17°W+8.

Flag X amount St y16. Z, +7. The setting operation of w18 is performed by the flag setting section X19. Y20.
Performed by Z2W22. When the maximum value candidate is found by the bit search circuit 13, the information signal 14 at the bit position (b p 2 in the example) determined when the maximum value candidate was selected is sent to the flag set section X+9. Y 20
．． 22W 2 M, the bit position information signal 14 and the data A based on the information of the bit position signal 14
I, B2. The flag X15°Y is set by the data of C3 and D4.
1111. 2171 W Ill is set.

In the case of the above example, Te9 A I, B2. C3, D4
Nob I) 2 The data are 1, 0, and 1.1, respectively, so the flag set section X+9・Y2O・ZQ
1 for flag X15 and flag YI6 due to l・W 22
is set to 0, flag Z17 is set to 1, and flag W+8 is set to 1, indicating that the three data of data AI and C3°D4 are maximum value data candidates. Next, the bit search circuit 13 checks the bpl of the judgment register 8. In the case of the above example, it is "0", and it can be seen that the maximum value is determined by checking the bpl of each data. Information signal 14 of the bit position (bpl in the example) from the bit search circuit 13
is the flag set part X19. Y2O,z211 W22
This bit position information signal 14 and each data AI, B2 . C3, D< value and current flag X+s・Y
+a+ z171 W2B(') value Niyori new shift rack X151Y 16+ 217. The value of WH is determined. In the above example, each data A+, B2 . bp of C3, D4
The value of i is 0.1.0. 1, flag X 15+
The value of Y 16 + Z + 7°W + s is 1,0
．． It is 1.1. When these two values are both 1'', flags X+s+ YI6+217 and W2B are set, and flags X +5+ Y, 6°Z l 71 W + s
Each data A, only at the bit position where the value is “0”
, B2. c3. If the value of D is “1”, the flag
I5. Yes, Zl? , the value of W+8 does not change. Newly set flag X15゜Yes, Z
17. A search operation is performed by the bit search circuit 13 (not shown) for the W vine 8, and the data set to 1" becomes the maximum value. Normally, the flags X's and Y+
a+ Z17. If only one flag is set to “1” by the pit search operation for W2B, or if the LSB (bpl) of judgment register Az
If the search has been performed up to this point, the operation ends. Even if the number of data changes, the maximum value can be determined in a fixed cycle, reducing the burden on the software.

FIG. 2 is a block diagram showing the configuration of the minimum value device of the present invention. The MSB bits of data AI, B2+C3, and D4 are input to the pit comparison and determination circuit 24. The pit comparison/judgment circuit 24 includes the exclusive NOR circuit 9 and N0R-O.
Consists of R circuit 23, data A4, Bc, C4, D4
are all 1'' or 0, the exclusive NOR circuit 9 sets bp4 of the determination register All to 1'. Also, two or more of the data A4, B1, C4, and D4 are 0. At this time, the N0R-OR circuit 23 sets bp4 of the determination register 1312 to '1'. bp3 of each data. bp2. Similarly, bit comparison and judgment circuits 25, 26, 27, and 28 select judgment registers A, B12, . The value is set to . As an example, data A
1 is (1010), data B, , (1001), data C3 (1010), data D, (1011). (1100), and (0101) is set in the determination register B+2. The bit search circuit 13 first examines the contents of the A-th determination register. The bit search operation is performed starting from the MSB, and the first “0”
” is detected. In the above example, the determination register Al
Since the value of l is (1100), bp2 is detected. At this time, the value of the judgment register 1312 is (0101) and bp2 is 0". This can be determined by checking the value of bp2 of each data from the value of the judgment register A1□. Indicates that the minimum value can be determined, and the bp of each data is determined from the value of the determination register BI2.
2 is 0" is one, and the bp2 of each data is checked, and the one with "0" is the minimum value.

The information that it is necessary to check bp2 of each data is sent to the flag set section X19 by the bit position information signal 14. Y
20. Z21. Flag X + s + Y + 6 + 217 that is transmitted to W22 and corresponds to data where the bp2 value of each data A+, B=, C3, D4 is "0"
, "1" is set in W+8. In the case of the above example, only the flag Y16 is set to "1", indicating that the data B2 is the minimum value. Even if the number of data changes, the minimum value can be found in a constant cycle, reducing the burden on the software.

As described above, according to the maximum value detection device according to the embodiment of the present invention,
In a device that detects the maximum value among a plurality of numerical values represented by parallel data in which each bit is 0 or 1 and is simultaneously input as parallel data to each numerical input terminal, the number of digits of the numerical value is a first determination register and a second determination register having the following values; and a storage means, inputting the values of the same bits from the plurality of numerical values, detecting a mismatch, and detecting the corresponding bit position of the first determination register. and presence/absence determining means for storing existence information in the second determination register in response to the presence of two or more 1's in the same bits; A bit search circuit is provided to search the contents of the second judgment register and control the storage, and the bit search circuit searches from the MSB of the first judgment register to find the first mismatch in the first judgment register. storing the plurality of numerical values having 1 in the bit position storing information in the storage means;
searching for a corresponding bit position in the second determination register for each bit position storing second and subsequent mismatch information;
When there is existence information, the operation of erasing the numerical value having 0 at that bit position is continued from the memory, and when there is no existence information, or the maximum value is detected by searching up to the LSB and making the numerical value remaining in the memory the maximum value. By using this device, the machine cycle for the maximum value detection operation becomes a cycle in which the bit search circuit searches the first and second determination registers from the MSB to the LSB (4 bits in the embodiment), and the machine cycle for the maximum value detection operation is a cycle in which the bit search circuit searches the first and second determination registers from the MSB to the LSB (in the embodiment, it is 4 bits). No matter how much the number increases, the machine cycle remains the same, which has the effect of speeding up maximum value detection. A similar effect can be obtained in minimum value detection.

In the embodiment, means for setting a flag is used as the storage means, but it goes without saying that the corresponding numerical value itself may be stored, or the number assigned to the numerical value may be stored. In addition, in the embodiment, a second judgment register is provided, and the search result is used to proceed to the next mismatch information search, thereby avoiding the next unnecessary mismatch search when the maximum value is determined up to the LSB. It goes without saying that the maximum value can be detected by providing only the first determination register and sequentially detecting mismatched bit positions up to the LSB, as described in . Note that if all the entered numerical values are the same, the maximum value or minimum value cannot be defined, but in such a case, the present invention prevents the numerical value from being stored in the storage means, causing no inconvenience. do not.

Effects of the Invention As is clear from the embodiments described above, a plurality of numerical values represented by parallel data in which each bit is 0 or 1 are simultaneously input as parallel data to each numerical input terminal. A device for detecting a maximum value, comprising a determination register having the number of digits of the numerical value, and a storage means, inputting the values of the same bits from the plurality of numerical values, detecting a mismatch, and detecting the corresponding bit of the determination register. A discrepancy determining means for storing discrepancy information in a position, and a bit search circuit for searching the contents of the determination register and controlling the storage, the bit search circuit searching from the MSB of the determination register, de1
The plurality of numerical values having 1 at the bit position where the mismatch information is stored in the storage means are stored in the storage means;
For each bit position where mismatch information below the th is stored, the operation of deleting the numerical value having 0 at that bit position from the memory is continued, and the maximum value is detected by searching up to the LSB and making the numerical value remaining in the memory the maximum value. Due to the nature of the device, the machine cycle for the maximum value detection operation is a cycle in which the bit search circuit searches the first and second determination registers from the MSB to the LSB (4 bits in this embodiment), and No matter how much the number increases, the machine cycle remains the same, which has the effect of speeding up maximum value detection.

A similar effect can also be achieved in minimum value detection.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a maximum value detection device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a minimum value detection device according to an embodiment of the present invention. 1... Parallel numerical data input, 2...
... Parallel numerical data input, 3... Parallel numerical data input, 4... Parallel numerical data input, 9... Exclusive NOR circuit (discrepancy judgment means) , 23... Exclusive NOR circuit (mismatch determining means), 24... Exclusive NOR circuit (mismatch determining means), 25... Exclusive NOR circuit (mismatch determining means) ), 11... Judgment register, 13
...Bit search circuit, 15...Flag (storage means), 16...Flag (storage means) 17...Flag...Flag ( (memory means) (memory means)

Claims (2)

[Claims] (1) In a device that detects the maximum value among a plurality of numerical values represented by parallel data in which each bit is 0 or 1, which is simultaneously input as parallel data to each numerical input terminal, the numerical value a determination register having a number of digits, and a storage means, a discrepancy determination unit that inputs the value of the same bit from the plurality of numerical values, detects a discrepancy, and stores discrepancy information in a corresponding bit position of the determination register. and a bit search circuit that searches the contents of the judgment register and controls the storage, and the bit search circuit searches from the MSB of the judgment register to find the first bit in the judgment register that stores the mismatch information. The plurality of numerical values having 1 in the position are stored in the storage means, and thereafter, for each bit position in which the second and subsequent mismatch information is stored, the operation of deleting the numerical value having 0 in that bit position is continued from the memory. , LSB and sets the stored numerical value as the maximum value. (2) In a device that detects the maximum value among a plurality of numerical values represented by parallel data in which each bit is 0 or 1, which is simultaneously input as parallel data to each numerical input terminal, the numerical value a determination register having a number of digits, and a storage means, a discrepancy determination unit that inputs the value of the same bit from the plurality of numerical values, detects a discrepancy, and stores discrepancy information in a corresponding bit position of the determination register. and a bit search circuit that searches the contents of the judgment register and controls the storage, and the bit search circuit searches from the MSB of the judgment register to find the first bit in the judgment register that stores the mismatch information. The plurality of numerical values having 0 in the position are stored in the storage means, and thereafter, for each bit position in which the second and subsequent mismatch information is stored, the operation of deleting the numerical value having 1 in that bit position is continued from the memory. , LSB and sets the stored numerical value as the minimum value.