JPH01100634A - Data processor - Google Patents

Abstract

PURPOSE:To remarkably improve the transfer efficiency of list information by providing a main memory, a main and sub-arithmetic units and an information transfer control device, separating the assignment of a transfer destination sub-arithmetic unit and an information transfer by a transfer device and executing them in parallel by a pipe line processing. CONSTITUTION:The list information processing of a main memory 1 is transferred to a processing part 4 in a main arithmetic unit 8 and sub-arithmetic units 12, the identification information of the list information is transferred to registers 2 of the list information processing part 4, at the same time, the elements of the list information are separately transferred by a transfer device 13 to element registers 9 of the sub-arithmetic unit assigned by a transfer control device 15 for the elements and the registers 2 of the main arithmetic unit 8 correspond to each of the register 9 of the sub-arithmetic units 12. Assignment start signals are inputted in parallel from the sub-arithmetic units 12 to respective parallel look ahead circuits in an assignment circuit 14, the least significant assignable sub-arithmetic unit is detected and in accordance with the result, the transfer device control circuit 15 transmits a transfer start to the sub-arithmetic units 12 and instructs the transfer device 13 on an elements transfer. When the pipe line processing by the transfer control device 16 and the transfer device 13 is executed, the transfer efficiency of the list information is remarkably improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a data processing device mainly intended for use in the field of artificial intelligence.

BACKGROUND OF THE INVENTION In recent years, the field of artificial intelligence has been actively researched as one of computer applications. In this field, it is necessary to process structured data, and therefore LISP, a language that can handle structured data, is widely used. The conventional method of representing structural data on a computer is to express the order relationship and connection method of elements using pointers (
(hereinafter referred to as the list). This method frequently appears in application programs in the field of artificial intelligence because all list operations involve sequentially following the pointer and performing zero operations.
It is qualitatively inefficient in terms of pattern matching and access to arbitrary elements. In general, a binary tree list starts from a starting node, branches sequentially to the left and right, and each branch ends at a leaf node. There are two types of leaf nodes: atom nodes and NIL nodes. Nodes that are not leaf nodes are list nodes that indicate that the branch is continuing. This list node is used to indirectly indicate the position of the leaf node. In the pointer representation, this structural representation is expressed as is by cells in which all nodes are connected by addresses.

As a result, access to each element always requires repeated indirect references to the address. In order to overcome this drawback, the following method has been proposed to change the method of expressing list data. If you can directly determine the position of a leaf node, there is no need to have list node information. Therefore, equivalent list data can be expressed by a table in which leaf position information and leaf information are sequentially arranged. A one-dimensional vector representation has been proposed as a method for expressing leaf node positions, in which numbers are sequentially assigned in the CDR direction and items are sequentially assigned in the CAR direction. FIG. 3 shows an example of list data representation. This can be expressed as 3 equations (A (
B (C) ) D) Diagrammatic representation of list data 3rd
Figure (al) and Table 2 (Figure 3(b)) are shown. In the diagrammatic representation, circles represent list nodes, and squares indicate leaf nodes. The number string added above the node indicates the position of the node created according to the method described above.The leaf part extracted and expressed in the form of a table is shown in the tabular representation in Figure 3 (
bl is composed of a table in which the ADDRESS section contains node position vectors and the VALUE section contains leaf elements. By adopting such an expression format, it becomes possible to process list data in parallel for each element without passing through pointers, and list operations such as the above-mentioned pattern matching can be performed at high speed.

An example of a conventional data processing device based on this tabular representation will be described below with reference to the drawings.

FIG. 4 shows a conventional processing device. In FIG. 4, 1 is a main memory device for storing tabular list data, 2 is a main processing unit, 3 is element calculation means for processing each element of list data, and 4 is for storing each element of list data. a sub-memory device; 5, a sub-processing device comprising the sub-processing device 3 and the sub-memory device 4; 6, a list data processing device comprising a plurality of sub-processing devices 3; 7, processing the list data from the main memory device 1; This is a transfer device that sequentially allocates each element of tabular data to each sub-processing device 5 in the device 6.

The operation of the data processing apparatus configured as described above will be described below. First, normal numerical data, character data, etc. are processed only by the main processing unit.

The list data is transferred from the main memory device 1 to the sub-processing device 5 by the transfer device 7 for each element. At this time, the transfer device 7 sequentially queries each sub-processing device 5 in the list data processing device 6 to find a vacant sub-processing device,
Transfer is performed to that sub-processing unit. After the transfer is completed, the list data is processed in parallel by each sub-processing unit. In this way, the present invention has the above-described configuration, and by having a unique memory for each of the plurality of sub-processing units that process list data in tabular format, the transfer from the memory device is performed once for each sub-processing unit. After that, the information is stored in each sub-processing unit and can be used for subsequent processing. As a result, it is possible to avoid transferring data every time processing is performed, so the overall amount of data transferred can be reduced.

Problems to be Solved by the Invention However, in the above configuration, when data is transferred from the memory device to each sub-processing device in the list data processing device, the transfer device sequentially queries each sub-processing device. Because of this, it takes time to find an unused sub-processing unit, and since the transfer operation is sequential processing, there is a problem in that the efficiency of list data transfer is low.

Means for Solving the Problems In order to solve the above problems, the data processing device of the present invention includes a main memory device that stores the position of each node of list data as tabular data expressed as a vector, and a main processing unit consisting of a list data processing section consisting of a plurality of list registers for storing identification information of list data in the table format and a list operation means; and a non-list data processing section consisting of a plurality of registers and arithmetic means; a plurality of sub-processing units that have a plurality of element registers for storing each element of the list data, an element calculation means, and a sub-memory device, and process each element of the list data in parallel under the control of the main processing unit; , a transfer control device that allocates the sub-processing device and controls the transfer device during data transfer; and elements of tabular data stored in the main memory device for each sub-processing device allocated by the transfer control device. The device is equipped with a transfer device that transfers the information.

Effect of the Invention With the above-described configuration, the present invention can significantly improve transfer efficiency by separating assignment of a transfer destination sub-processing unit and data transfer by a transfer device and performing parallel processing using pipeline processing.

Embodiment Hereinafter, a data processing apparatus according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of a data processing device in an embodiment of the present invention. In FIG. 1, 1 is a main memory device, 2 is a list register, and 3 is a list calculation means, and the list data processing section 4 is a general term for a plurality of list registers and list calculation means. 5 is a register, 6 is a calculation means, and the atom data processing section 7 is a general term for a plurality of registers and calculation means. Furthermore, the main processing unit 8 is a general term for the list data processing section and the atom data processing section. 9 is an element register, 10 is an element calculation means, and 11 is a sub memory device. The sub-processing device 12 is a general term for element registers, element calculation means, and sub-memory device. 13 is a transfer device.

14 is a sub-processing device allocation circuit, and 15 is a transfer device control circuit. Reference numeral 16 denotes a transfer control device consisting of a sub-processing device allocation circuit 14 and a transfer device control circuit 15.

FIG. 2 is a block diagram of the sub-processing unit allocation circuit.

21 is a parallel look-ahead circuit, which includes a plurality of input terminals 22, the same number of output terminals 23 as the input terminals 22, an allocation start signal input terminal 24, and an allocation start signal output terminal 25.
and a latch 26 for holding the contents of the output terminal 23.
has. The sub processing unit allocation circuit is a plurality of parallel lookahead circuits connected in series using the input terminal 24 and output terminal 25 of the allocation start signal, and the input terminal 24 of each parallel lookahead circuit 21 and the latch 2
The output terminals 6 serve as input terminals and output terminals of the sub-processing unit allocation circuit, respectively. The data processing device configured as above will be explained below with reference to FIGS. 1 and 2. First, a reference to atom data is stored in the VALUE section of each element of list data. Processing of numerical and character data, which are their actual values, is performed using the register 5 and calculation means 6 in the atom data processing section 7. These atom data are stored in the main memory. Next, list data processing is carried out by the list data processing unit 4 in the main processing unit 8 and the sub processing unit 12.
carried out by. Element register 9 in each sub-processing unit for one list register 2 of the list data processing unit
One of them corresponds. That is, identification information of list data is stored in a list register, and each element of list data is stored in a plurality of corresponding element registers, representing one list data as a whole. When an operation is performed on the list register, necessary operations are simultaneously performed on the corresponding element register. When the list data stored in the main memory device 1 is processed, the data is transferred to the main processing unit and the sub processing unit, and then the processing is performed in parallel. - Data of each element transferred once is placed under the management of each sub-processing unit and stored in the sub-memory device 12 of each sub-processing unit, and unnecessary data transfer between the main memory device and the sub-processing unit is not performed. . Data transfer to the sub-processing unit is performed as follows. Among the list data stored in the main memory device 1, the identification information of the list data is transferred to the list register in the list data processing section in the main processing unit, and at the same time, each element of the list data is transferred by the transfer device 13 under transfer control. The data is transferred separately to the element register of the sub-processing unit assigned to each element by the device 15. This assignment operation is performed as follows. First, signals indicating whether allocation is possible or not output from each sub-processing unit are input in parallel to a plurality of input terminals of each parallel look-ahead circuit in the sub-processing unit allocation circuit. This parallel look-ahead circuit is a circuit in which only the output terminal corresponding to the lowest H input among a plurality of inputs is set to H. The output of this circuit is an assignment signal indicating that the corresponding sub-processing unit can be assigned when it is at H level.

Each parallel lookahead circuit generates an allocation signal from its own input only when the allocation start signal from the lower parallel lookahead circuit is at H level, and outputs the logical sum of the allocation signals as the allocation start signal to the upper level. . When the allocation start signal from the lower level is L, all outputs including the allocation start signal output to the higher level are set to L.

Allocation is started when H is input to the allocation start signal input of the lowest parallel lookahead circuit. As a result, at most one output terminal of the sub-processing unit allocation circuit becomes H, and the lowest assignable sub-processing unit is detected. According to the result, the transfer control circuit notifies the sub-processing unit of the start of transfer and instructs the transfer device to transfer the element data. The next allocation operation and the current transfer operation are independent, so
When there is next element data to be transferred, the next allocation can be determined without waiting for the completion of the current transfer device. If pipeline processing is performed by the transfer control device and the transfer device in this way, the time required for the allocation operation is smaller than the time required for the transfer, so when transferring a large number of element data, the time required for the allocation operation can be reduced.は上O
It can be done. As described above, according to this embodiment, it is possible to minimize the time required for data transfer.

Effects of the Invention As described above, the present invention provides a main memory device that stores the position of each node of list data as tabular data expressed as a vector, and a plurality of lists that stores identification information of the tabular list data. a main processing unit consisting of a list data processing unit including a register and a list calculation means, a non-list data processing unit including a plurality of registers and a calculation means, and a plurality of element registers for storing each element of the list data in the table format; a plurality of sub-processing units that have element calculation means and a sub-memory device and process each element of list data in parallel under the control of the main processing unit; and a plurality of sub-processing units that allocate and transfer the sub-processing units when transferring data. A transfer control device that controls a device, and a transfer device that transfers elements of tabular data stored in the main memory device to each sub-processing device assigned by the transfer control device, and a list of tabular data. The present invention provides a data processing device that can minimize the time required for data transfer in parallel data processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention, FIG. 2 is a block diagram of a sub-processing unit allocation circuit, and FIGS. 3(a) and 3(b) are examples of tabular representations of list data. The explanatory diagram shown in FIG. 4 is a block diagram of a conventional data processing device. 1...Main memory device, 2...List register, 3...List calculation means, 4...
・List data processing unit, 5...Register, 6.
...Arithmetic means, 7...Atom data processing unit, 8...Main arithmetic unit, 9...Element register, 10...Element operation Means, 11...
...Sub-memory device, 12...Sub-processing device, 13
...Transfer device, 14...Sub-processing device allocation circuit, 15...Transfer device control circuit, 16
・・・・・・Transfer control device.

Claims (1)

[Claims] A list data processing unit comprising a main memory device that stores the position of each node of list data as tabular data expressed as a vector, a plurality of list registers that store identification information of the tabular list data, and list calculation means. and a main arithmetic unit comprising a non-list data processing section comprising a plurality of registers and arithmetic means, a plurality of element registers for storing each element of the tabular list data, an element arithmetic means, and an auxiliary memory device. a plurality of sub-processing devices that process each element of list data in parallel under the control of the main processing device; a transfer control device that allocates the sub-processing devices during data transfer and controls the transfer device; A data processing device comprising: a transfer device that transfers elements of tabular data stored in the main memory device to each sub-processing device assigned by a transfer control device.