JPS58146947A - Logical simulator - Google Patents

Abstract

PURPOSE:To execute the logical simulation of a large scale logical operation device at a high speed, by finding out a processor connected through a wiring from a connection memory in accordance with the change of an output pin and processing the information of change while transmitting the change information simultaneously to the processor through a coupled network. CONSTITUTION:Each processor PJ takes out the logical status of an I/O pin corresponding to an integrated circuit to be simulated from a status memory SJ. The logical operation of the integrated circuit is executed by an integrated circuit logical operator IJ, the status memory SJ is updated and the integrated circuit connected through the wiring is found from a connection memory CJ. The processor PJ is connected to any one of processors P1-PN divided through a coupling network 1. Said operation is executed in parallel in respective processors P1-PN. The status memories I1-IN and connection memories C1-CN are accessed independently. The integrated circuit logical operators I1-IN also execute the opration of integrated circuits independently.

Description

[Detailed description of the invention] The present invention relates to a logic simulator.

When developing a logic device that uses a large number of integrated circuits, it is difficult to correct the circuit if an error is discovered after the device is actually distributed and tested. The number of days and costs will increase. Furthermore, in recent years L
8I. As custom ICs come into widespread use, it is necessary to find logical design errors as soon as possible, as it may become necessary to modify the integrated circuit. Logic simulators are often used to test devices from the previous stage. A logic simulator uses a simulation to perform the same operation as the target logic device, and is often performed by software.

Logic! Since the data processing is sequentially processed by software, as the logical scale of the target device increases, the processing time increases, and it may take several years to process one OPU, making it impractical. There is a drawback that it becomes something that does not exist.

It is an object of the present invention to provide a logic simulator that eliminates such conventional drawbacks and performs logic simulators of large-scale logic devices at high speed.

According to the logic stain controller of the present invention, if one type and one number of integrated circuits constitute a logic device to be simulated, the stains, radiation, and n of each integrated circuit can be removed by multiple blocks. A state memory that stores logical states corresponding to the input/output bins for the number of integrated circuits divided into t, and an integrated circuit that performs logical operations for the pole classes of the divided round integrated circuits. A logic operation unit, a connection memory that stores a wiring table of output pins for the number of integrated circuits assigned to it, and a plurality of
The simulator has a plurality of processors and a connected controller for mutual communication, and the logic state of the input/output bin corresponding to the target integrated circuit is retrieved from the state memory of each of the multiple processors. broth.

Since the integrated circuit logic arithmetic unit performs calculations, the state memory transmits the change information, and then the process is performed on the same W#, parallel processing is performed, and the state memory and the collection, storage, and processing can be performed. It is characterized by

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a logical stainer and a controller showing one embodiment of the present invention. Pi, P2.・,,PJ...PN is a plurality of pouse, 81, 82. ...8J...
・8NFi respective state memory, II, I2. -・I
J-・IN are respective integrated circuit logic operation units, CI, C
2,,=CJ-.

CN is 1ikI of each! ic system, and 1 is the connection network.

Each Pouse, PJ is stored in the state memory 8J! Lucy,
Input/output bin 0ili1jI corresponding to the integrated circuit to be scanned
The i state is taken out, the integrated circuit logical operation unit IJ performs a logical operation on the integrated circuit, the state memo 98J is updated, and according to the change in the output bin, the integrated circuit ahead of the cloth lII is determined from the connection memory CJ, and the connection order and network are calculated. Contact any of the below. This movement tightens each Bromo, SuPI, P2.・PJ-
This is done in parallel in the PN, and also in the power collection memory 11. I2. −
IJ-・IN and connected memory CI, C2, --・CJ・・
・Memory access to CN is independent, and integrated circuit logic operation unit 11゜■2.・、、IJ・、
Since IN also performs integrated circuit calculations independently, high-speed logic stains, storage, and input are performed.

FIG. 2 shows a plurality of bromides shown in FIG.

It is a professional diagram showing one Bromo, PJ o structure sequence in PI, -PJ-PNO.

101 is a group of connection lines with the connection network l, 102 is a group of access lines for the status memo 98J, 103 is a group of access lines with the integrated circuit logical operation unit IJ, and 104 is a group of connection lines with the connection memory CJ.
This is the access line group. 110 and 118 are a message input line group and a message output line group, respectively, of the connection line group of the connection network.

Reference numeral 10 denotes a message input control unit, which accepts a message indicating a status change to the corresponding integrated circuit from the message input line group 11G, and outputs an input message 111. Reference numeral 11 denotes a status memory access control unit, which outputs a message 111 indicating a status change to the corresponding integrated circuit.
1 Take out the input/output bin information of the integrated circuit corresponding to K from the access line 11102 and output the bin status 113, 12
is an arithmetic control unit which uses the bin state 113 to access the integrated circuit logic operator IJ from the access line group 103 and outputs a new state 11115. Access control device 11 inputs new state 115 and access line group 112
The state memory 8J is updated via the state memory 8J. 13 is a comparison section which inputs the new state @ 115 and the bottle shape [111m and outputs a change output 116 to output a change in the output. 14 is an access control section for the connected memory, which connects the access line to the connection memory CJ by the change output 116. Access 119 is performed via group 104 to find the integrated circuit of the wiring light and output change message 117. Reference numeral 15 denotes an output control section of the coupling network, which inputs the change message 117 and controls the coupling network, network 1,
Via the Sene output line group 118, a Boussesser (PK) K, which is responsible for the change mode and the seventh mode, is transmitted.

The third fat is each state memory 81 and 82 shown in Figure 1.
．． , -82-. This is an example of the configuration of one state meter 8J in 8NO.

The number address access 301 of the integrated circuit to be shared is given from the access line group 102 from the FJ,
31 is an access control unit which inputs the number 7 address access 301 and issues an address access 302; 32 stores the state of the O input/output bin for the integrated circuit shared by the state memory cell; the address access 302 is a read access; The input/output pin state value 303 is stored in it, and if the address access 302 is an update access, it is written to a new state St-state memory cell 32.

FIG. 2 is a professional diagram showing an example of the configuration of a scientific arithmetic unit IJ.

When 401 is received, the type of integrated circuit on which the operation is to be performed is determined, and one of the selected output groups 4020 is selected. 42, 42B.

-42M is an integrated circuit group and is shared. An integrated circuit that is actually used to perform the logic operation of the type of integrated circuit valve, or a group of integrated circuits that are actually used and have the same function is selected according to the type by the 0 selector 41 using an lPL system. 42mu, 42B.

-42MC11 is selected and a logical operation is performed to obtain a state value 403. 43 is a status output device, which outputs a newer status g@404t access line group 1 from the obtained status value 403.
03; The wcs diagram shows each connection memory CI shown in Figure 1,
2 is a diagram showing an example of the configuration of one connection memory CJ in C2, -CJ-CN; FIG. Reference numeral 51 denotes a pointer cheagle, which inputs a state change 501 consisting of PSET and PJ from the access line group 104, and outputs a pointer 502 of a table containing the integrated circuit name of the wiring light for the output pin. Reference numeral 53 is a connection table that stores the integrated circuit name of the wiring light corresponding to the output pin, and the name of the shared program. Reference numeral 52 denotes an access control unit which issues table access 503 when the pointer 502 is input;
The connection table 53 is accessed, the name of the integrated circuit of the wiring light and the name of the bromo and name that are shared are taken out, and the wiring party name 504 is outputted to the access line group 104.

FIG. 6 is a diagram showing an example of the configuration of the connection network l shown in FIG. 1. X11゜x, , -x, 1
1. x, 1. x, , , -xtu are each ρ
It's super quick and easy, and it's a small number of inputs.

'' are connected in multiple stages so that data can be transferred between any number of inputs (N) and outputs (N). Jl number Pouse, SuPI, P2.・-PJ-PN are access line groups 601 and 6, each of which is a pair of input/output line groups.
02. -・6ON each connected to any bromo,
PJ can transmit any message of bromo or PKK output change. Although FIG. 6 shows an example of a multi-stage configuration of the coupled network IC (IC), other systems may also be constructed using a common bus system, a single large stage loss bar system, etc.

According to the present invention, a system to be simulated is configured. The simulation of each integrated circuit is divided into multiple models depending on the type and size of the integrated circuit.

The logic state memory corresponding to the input/output pin of the target integrated circuit is taken out from each logic state memory and sent to each integrated circuit logic arithmetic unit that performs the mapped class logic operations assigned to the integrated circuit. It gives the logic state of the target integrated circuit, performs logical operations, updates the state and memory, and stores the wiring corresponding to the output pins for the number of tm to be shared according to changes in the output pins. Find the wiring light integrated circuit from the connection memory and combine Bromo and SurJJ. Sharing through a connective network. While transmitting changes in the state to the logic circuits of the target system, the integrated circuits that make up the system are subjected to multiple circuits in parallel. Therefore, there is an effect that the process can be performed quickly.

[Brief explanation of drawings]

FIG. 1 shows an example of a logic stain and a rotor showing an embodiment of the present invention, and FIGS.
FIG. 2 is a diagram illustrating examples of a state memory, an integrated circuit logic unit, a connection memory, and a connection network. 1--bond, twerk, Pl, P2. ...PJ-P
N.-Processor, 81, 82. -・8J...SN・
...state memory, II, I2.・-IJ・-・IN・-
Integrated circuit logic operator, CI. C2, -CJ...CN--connection memory, io...message input system@ section, 11, 14, 31.52-access control section, 12...arithmetic control section, 13...comparison section ,
15--output control unit, 32--state memory cell, 41-
Selector, 42M, 42B-42M, - Integrated circuit group, 4
3.-Status output device, 51... Pointer table, 53
- Connection table, Xll, X12-XIU, X21. X
22. ,,,X2U...Crossbar switch. 11th ¥] Pu51 If (:/ 5272 C2sJ IJ CJ
SPJ IA/CN Figure 2 Figure 5 4 Figure 03 Figure 5 Figure B

Claims (1)

[Claims] In a logic simulator that performs cycling of logic devices, the integrated circuits that make up the logic device are
I! A plurality of bromos, each of which is divided and distributed to perform a simulation, are stored, respectively K of the plurality of bromos, t, and logical states m of input/output bins for the number of integrated circuits to be shared. Each state memory, each integrated circuit logic operation unit that performs the logical operations of the assigned integrated circuits, and each connection memory that stores the wiring table of the output pins for the number of output pins of the assigned integrated circuits. and a connecting wire and a tweeter for connecting the plurality of posers and communicating with each other, and each of the plurality of poseurs has a configuration of each of the above.
The logic states of the integrated circuits to be stained, ranged, and scanned are taken out from the memory, and the respective integrated circuit logic arithmetic units perform calculations, the state mesori is updated, and the logic states of the integrated circuits to be detected are extracted from the respective connected memories according to the change in the output state. the Bromo, which is responsible for finding the integrated circuit to be wrapped and connecting it to the connection network;
A logic simulator, characterized in that a logic simulation is performed in parallel with the plurality of blocks by transmitting an output change to the block.